2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * PCIM_xxx: mask to locate subfield in register
34 * PCIR_xxx: config register offset
35 * PCIC_xxx: device class
36 * PCIS_xxx: device subclass
37 * PCIP_xxx: device programming interface
38 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
40 * PCIY_xxx: capability identification number
41 * PCIZ_xxx: extended capability identification number
44 /* some PCI bus constants */
45 #define PCI_DOMAINMAX 65535 /* highest supported domain number */
46 #define PCI_BUSMAX 255 /* highest supported bus number */
47 #define PCI_SLOTMAX 31 /* highest supported slot number */
48 #define PCI_FUNCMAX 7 /* highest supported function number */
49 #define PCI_REGMAX 255 /* highest supported config register addr. */
50 #define PCIE_REGMAX 4095 /* highest supported config register addr. */
51 #define PCI_MAXHDRTYPE 2
53 #define PCIE_ARI_SLOTMAX 0
54 #define PCIE_ARI_FUNCMAX 255
56 #define PCI_RID_DOMAIN_SHIFT 16
57 #define PCI_RID_BUS_SHIFT 8
58 #define PCI_RID_SLOT_SHIFT 3
59 #define PCI_RID_FUNC_SHIFT 0
61 #define PCI_RID(bus, slot, func) \
62 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
63 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \
64 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
66 #define PCI_ARI_RID(bus, func) \
67 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
68 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
70 #define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)
71 #define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
72 #define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
74 #define PCIE_ARI_RID2SLOT(rid) (0)
75 #define PCIE_ARI_RID2FUNC(rid) \
76 (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX)
78 #define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
79 #define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
81 /* PCI config header registers for all devices */
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
90 #define PCIM_CMD_SPECIALEN 0x0008
91 #define PCIM_CMD_MWRICEN 0x0010
92 #define PCIM_CMD_PERRESPEN 0x0040
93 #define PCIM_CMD_SERRESPEN 0x0100
94 #define PCIM_CMD_BACKTOBACK 0x0200
95 #define PCIM_CMD_INTxDIS 0x0400
96 #define PCIR_STATUS 0x06
97 #define PCIM_STATUS_INTxSTATE 0x0008
98 #define PCIM_STATUS_CAPPRESENT 0x0010
99 #define PCIM_STATUS_66CAPABLE 0x0020
100 #define PCIM_STATUS_BACKTOBACK 0x0080
101 #define PCIM_STATUS_MDPERR 0x0100
102 #define PCIM_STATUS_SEL_FAST 0x0000
103 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
104 #define PCIM_STATUS_SEL_SLOW 0x0400
105 #define PCIM_STATUS_SEL_MASK 0x0600
106 #define PCIM_STATUS_STABORT 0x0800
107 #define PCIM_STATUS_RTABORT 0x1000
108 #define PCIM_STATUS_RMABORT 0x2000
109 #define PCIM_STATUS_SERR 0x4000
110 #define PCIM_STATUS_PERR 0x8000
111 #define PCIR_REVID 0x08
112 #define PCIR_PROGIF 0x09
113 #define PCIR_SUBCLASS 0x0a
114 #define PCIR_CLASS 0x0b
115 #define PCIR_CACHELNSZ 0x0c
116 #define PCIR_LATTIMER 0x0d
117 #define PCIR_HDRTYPE 0x0e
118 #define PCIM_HDRTYPE 0x7f
119 #define PCIM_HDRTYPE_NORMAL 0x00
120 #define PCIM_HDRTYPE_BRIDGE 0x01
121 #define PCIM_HDRTYPE_CARDBUS 0x02
122 #define PCIM_MFDEV 0x80
123 #define PCIR_BIST 0x0f
125 /* PCI Spec rev 2.2: 0FFFFh is an invalid value for Vendor ID. */
126 #define PCIV_INVALID 0xffff
128 /* Capability Register Offsets */
130 #define PCICAP_ID 0x0
131 #define PCICAP_NEXTPTR 0x1
133 /* Capability Identification Numbers */
135 #define PCIY_PMG 0x01 /* PCI Power Management */
136 #define PCIY_AGP 0x02 /* AGP */
137 #define PCIY_VPD 0x03 /* Vital Product Data */
138 #define PCIY_SLOTID 0x04 /* Slot Identification */
139 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
140 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
141 #define PCIY_PCIX 0x07 /* PCI-X */
142 #define PCIY_HT 0x08 /* HyperTransport */
143 #define PCIY_VENDOR 0x09 /* Vendor Unique */
144 #define PCIY_DEBUG 0x0a /* Debug port */
145 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
146 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
147 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
148 #define PCIY_AGP8X 0x0e /* AGP 8x */
149 #define PCIY_SECDEV 0x0f /* Secure Device */
150 #define PCIY_EXPRESS 0x10 /* PCI Express */
151 #define PCIY_MSIX 0x11 /* MSI-X */
152 #define PCIY_SATA 0x12 /* SATA */
153 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */
154 #define PCIY_EA 0x14 /* PCI Extended Allocation */
156 /* Extended Capability Register Fields */
158 #define PCIR_EXTCAP 0x100
159 #define PCIM_EXTCAP_ID 0x0000ffff
160 #define PCIM_EXTCAP_VER 0x000f0000
161 #define PCIM_EXTCAP_NEXTPTR 0xfff00000
162 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID)
163 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16)
164 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
166 /* Extended Capability Identification Numbers */
168 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */
169 #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */
170 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */
171 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */
172 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */
173 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */
174 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */
175 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */
176 #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */
177 #define PCIZ_RCRB 0x000a /* RCRB Header */
178 #define PCIZ_VENDOR 0x000b /* Vendor Unique */
179 #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */
180 #define PCIZ_ACS 0x000d /* Access Control Services */
181 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */
182 #define PCIZ_ATS 0x000f /* Address Translation Services */
183 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */
184 #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */
185 #define PCIZ_MULTICAST 0x0012 /* Multicast */
186 #define PCIZ_PAGE_REQ 0x0013 /* Page Request */
187 #define PCIZ_AMD 0x0014 /* Reserved for AMD */
188 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */
189 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */
190 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */
191 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */
192 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */
193 #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */
194 #define PCIZ_PASID 0x001b /* Process Address Space ID */
195 #define PCIZ_LN_REQ 0x001c /* LN Requester */
196 #define PCIZ_DPC 0x001d /* Downstream Porto Containment */
197 #define PCIZ_L1PM 0x001e /* L1 PM Substates */
199 /* config registers for header type 0 devices */
201 #define PCIR_BARS 0x10
202 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
203 #define PCIR_MAX_BAR_0 5
204 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
205 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
206 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
207 #define PCIM_BAR_SPACE 0x00000001
208 #define PCIM_BAR_MEM_SPACE 0
209 #define PCIM_BAR_IO_SPACE 1
210 #define PCIM_BAR_MEM_TYPE 0x00000006
211 #define PCIM_BAR_MEM_32 0
212 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
213 #define PCIM_BAR_MEM_64 4
214 #define PCIM_BAR_MEM_PREFETCH 0x00000008
215 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL
216 #define PCIM_BAR_IO_RESERVED 0x00000002
217 #define PCIM_BAR_IO_BASE 0xfffffffc
218 #define PCIR_CIS 0x28
219 #define PCIM_CIS_ASI_MASK 0x00000007
220 #define PCIM_CIS_ASI_CONFIG 0
221 #define PCIM_CIS_ASI_BAR0 1
222 #define PCIM_CIS_ASI_BAR1 2
223 #define PCIM_CIS_ASI_BAR2 3
224 #define PCIM_CIS_ASI_BAR3 4
225 #define PCIM_CIS_ASI_BAR4 5
226 #define PCIM_CIS_ASI_BAR5 6
227 #define PCIM_CIS_ASI_ROM 7
228 #define PCIM_CIS_ADDR_MASK 0x0ffffff8
229 #define PCIM_CIS_ROM_MASK 0xf0000000
230 #define PCIM_CIS_CONFIG_MASK 0xff
231 #define PCIR_SUBVEND_0 0x2c
232 #define PCIR_SUBDEV_0 0x2e
233 #define PCIR_BIOS 0x30
234 #define PCIM_BIOS_ENABLE 0x01
235 #define PCIM_BIOS_ADDR_MASK 0xfffff800
236 #define PCIR_CAP_PTR 0x34
237 #define PCIR_INTLINE 0x3c
238 #define PCIR_INTPIN 0x3d
239 #define PCIR_MINGNT 0x3e
240 #define PCIR_MAXLAT 0x3f
242 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
244 #define PCIR_MAX_BAR_1 1
245 #define PCIR_SECSTAT_1 0x1e
247 #define PCIR_PRIBUS_1 0x18
248 #define PCIR_SECBUS_1 0x19
249 #define PCIR_SUBBUS_1 0x1a
250 #define PCIR_SECLAT_1 0x1b
252 #define PCIR_IOBASEL_1 0x1c
253 #define PCIR_IOLIMITL_1 0x1d
254 #define PCIR_IOBASEH_1 0x30
255 #define PCIR_IOLIMITH_1 0x32
256 #define PCIM_BRIO_16 0x0
257 #define PCIM_BRIO_32 0x1
258 #define PCIM_BRIO_MASK 0xf
260 #define PCIR_MEMBASE_1 0x20
261 #define PCIR_MEMLIMIT_1 0x22
263 #define PCIR_PMBASEL_1 0x24
264 #define PCIR_PMLIMITL_1 0x26
265 #define PCIR_PMBASEH_1 0x28
266 #define PCIR_PMLIMITH_1 0x2c
267 #define PCIM_BRPM_32 0x0
268 #define PCIM_BRPM_64 0x1
269 #define PCIM_BRPM_MASK 0xf
271 #define PCIR_BIOS_1 0x38
272 #define PCIR_BRIDGECTL_1 0x3e
274 #define PCI_PPBMEMBASE(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
275 #define PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff)
276 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
277 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
279 /* config registers for header type 2 (CardBus) devices */
281 #define PCIR_MAX_BAR_2 0
282 #define PCIR_CAP_PTR_2 0x14
283 #define PCIR_SECSTAT_2 0x16
285 #define PCIR_PRIBUS_2 0x18
286 #define PCIR_SECBUS_2 0x19
287 #define PCIR_SUBBUS_2 0x1a
288 #define PCIR_SECLAT_2 0x1b
290 #define PCIR_MEMBASE0_2 0x1c
291 #define PCIR_MEMLIMIT0_2 0x20
292 #define PCIR_MEMBASE1_2 0x24
293 #define PCIR_MEMLIMIT1_2 0x28
294 #define PCIR_IOBASE0_2 0x2c
295 #define PCIR_IOLIMIT0_2 0x30
296 #define PCIR_IOBASE1_2 0x34
297 #define PCIR_IOLIMIT1_2 0x38
298 #define PCIM_CBBIO_16 0x0
299 #define PCIM_CBBIO_32 0x1
300 #define PCIM_CBBIO_MASK 0x3
302 #define PCIR_BRIDGECTL_2 0x3e
304 #define PCIR_SUBVEND_2 0x40
305 #define PCIR_SUBDEV_2 0x42
307 #define PCIR_PCCARDIF_2 0x44
309 #define PCI_CBBMEMBASE(l) ((l) & ~0xfffff)
310 #define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff)
311 #define PCI_CBBIOBASE(l) ((l) & ~0x3)
312 #define PCI_CBBIOLIMIT(l) ((l) | 0x3)
314 /* PCI device class, subclass and programming interface definitions */
316 #define PCIC_OLD 0x00
317 #define PCIS_OLD_NONVGA 0x00
318 #define PCIS_OLD_VGA 0x01
320 #define PCIC_STORAGE 0x01
321 #define PCIS_STORAGE_SCSI 0x00
322 #define PCIS_STORAGE_IDE 0x01
323 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
324 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
325 #define PCIP_STORAGE_IDE_MODESEC 0x04
326 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
327 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
328 #define PCIS_STORAGE_FLOPPY 0x02
329 #define PCIS_STORAGE_IPI 0x03
330 #define PCIS_STORAGE_RAID 0x04
331 #define PCIS_STORAGE_ATA_ADMA 0x05
332 #define PCIS_STORAGE_SATA 0x06
333 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
334 #define PCIS_STORAGE_SAS 0x07
335 #define PCIS_STORAGE_NVM 0x08
336 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01
337 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02
338 #define PCIS_STORAGE_OTHER 0x80
340 #define PCIC_NETWORK 0x02
341 #define PCIS_NETWORK_ETHERNET 0x00
342 #define PCIS_NETWORK_TOKENRING 0x01
343 #define PCIS_NETWORK_FDDI 0x02
344 #define PCIS_NETWORK_ATM 0x03
345 #define PCIS_NETWORK_ISDN 0x04
346 #define PCIS_NETWORK_WORLDFIP 0x05
347 #define PCIS_NETWORK_PICMG 0x06
348 #define PCIS_NETWORK_OTHER 0x80
350 #define PCIC_DISPLAY 0x03
351 #define PCIS_DISPLAY_VGA 0x00
352 #define PCIS_DISPLAY_XGA 0x01
353 #define PCIS_DISPLAY_3D 0x02
354 #define PCIS_DISPLAY_OTHER 0x80
356 #define PCIC_MULTIMEDIA 0x04
357 #define PCIS_MULTIMEDIA_VIDEO 0x00
358 #define PCIS_MULTIMEDIA_AUDIO 0x01
359 #define PCIS_MULTIMEDIA_TELE 0x02
360 #define PCIS_MULTIMEDIA_HDA 0x03
361 #define PCIS_MULTIMEDIA_OTHER 0x80
363 #define PCIC_MEMORY 0x05
364 #define PCIS_MEMORY_RAM 0x00
365 #define PCIS_MEMORY_FLASH 0x01
366 #define PCIS_MEMORY_OTHER 0x80
368 #define PCIC_BRIDGE 0x06
369 #define PCIS_BRIDGE_HOST 0x00
370 #define PCIS_BRIDGE_ISA 0x01
371 #define PCIS_BRIDGE_EISA 0x02
372 #define PCIS_BRIDGE_MCA 0x03
373 #define PCIS_BRIDGE_PCI 0x04
374 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
375 #define PCIS_BRIDGE_PCMCIA 0x05
376 #define PCIS_BRIDGE_NUBUS 0x06
377 #define PCIS_BRIDGE_CARDBUS 0x07
378 #define PCIS_BRIDGE_RACEWAY 0x08
379 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
380 #define PCIS_BRIDGE_INFINIBAND 0x0a
381 #define PCIS_BRIDGE_OTHER 0x80
383 #define PCIC_SIMPLECOMM 0x07
384 #define PCIS_SIMPLECOMM_UART 0x00
385 #define PCIP_SIMPLECOMM_UART_8250 0x00
386 #define PCIP_SIMPLECOMM_UART_16450A 0x01
387 #define PCIP_SIMPLECOMM_UART_16550A 0x02
388 #define PCIP_SIMPLECOMM_UART_16650A 0x03
389 #define PCIP_SIMPLECOMM_UART_16750A 0x04
390 #define PCIP_SIMPLECOMM_UART_16850A 0x05
391 #define PCIP_SIMPLECOMM_UART_16950A 0x06
392 #define PCIS_SIMPLECOMM_PAR 0x01
393 #define PCIS_SIMPLECOMM_MULSER 0x02
394 #define PCIS_SIMPLECOMM_MODEM 0x03
395 #define PCIS_SIMPLECOMM_GPIB 0x04
396 #define PCIS_SIMPLECOMM_SMART_CARD 0x05
397 #define PCIS_SIMPLECOMM_OTHER 0x80
399 #define PCIC_BASEPERIPH 0x08
400 #define PCIS_BASEPERIPH_PIC 0x00
401 #define PCIP_BASEPERIPH_PIC_8259A 0x00
402 #define PCIP_BASEPERIPH_PIC_ISA 0x01
403 #define PCIP_BASEPERIPH_PIC_EISA 0x02
404 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
405 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
406 #define PCIS_BASEPERIPH_DMA 0x01
407 #define PCIS_BASEPERIPH_TIMER 0x02
408 #define PCIS_BASEPERIPH_RTC 0x03
409 #define PCIS_BASEPERIPH_PCIHOT 0x04
410 #define PCIS_BASEPERIPH_SDHC 0x05
411 #define PCIS_BASEPERIPH_IOMMU 0x06
412 #define PCIS_BASEPERIPH_OTHER 0x80
414 #define PCIC_INPUTDEV 0x09
415 #define PCIS_INPUTDEV_KEYBOARD 0x00
416 #define PCIS_INPUTDEV_DIGITIZER 0x01
417 #define PCIS_INPUTDEV_MOUSE 0x02
418 #define PCIS_INPUTDEV_SCANNER 0x03
419 #define PCIS_INPUTDEV_GAMEPORT 0x04
420 #define PCIS_INPUTDEV_OTHER 0x80
422 #define PCIC_DOCKING 0x0a
423 #define PCIS_DOCKING_GENERIC 0x00
424 #define PCIS_DOCKING_OTHER 0x80
426 #define PCIC_PROCESSOR 0x0b
427 #define PCIS_PROCESSOR_386 0x00
428 #define PCIS_PROCESSOR_486 0x01
429 #define PCIS_PROCESSOR_PENTIUM 0x02
430 #define PCIS_PROCESSOR_ALPHA 0x10
431 #define PCIS_PROCESSOR_POWERPC 0x20
432 #define PCIS_PROCESSOR_MIPS 0x30
433 #define PCIS_PROCESSOR_COPROC 0x40
435 #define PCIC_SERIALBUS 0x0c
436 #define PCIS_SERIALBUS_FW 0x00
437 #define PCIS_SERIALBUS_ACCESS 0x01
438 #define PCIS_SERIALBUS_SSA 0x02
439 #define PCIS_SERIALBUS_USB 0x03
440 #define PCIP_SERIALBUS_USB_UHCI 0x00
441 #define PCIP_SERIALBUS_USB_OHCI 0x10
442 #define PCIP_SERIALBUS_USB_EHCI 0x20
443 #define PCIP_SERIALBUS_USB_XHCI 0x30
444 #define PCIP_SERIALBUS_USB_DEVICE 0xfe
445 #define PCIS_SERIALBUS_FC 0x04
446 #define PCIS_SERIALBUS_SMBUS 0x05
447 #define PCIS_SERIALBUS_INFINIBAND 0x06
448 #define PCIS_SERIALBUS_IPMI 0x07
449 #define PCIP_SERIALBUS_IPMI_SMIC 0x00
450 #define PCIP_SERIALBUS_IPMI_KCS 0x01
451 #define PCIP_SERIALBUS_IPMI_BT 0x02
452 #define PCIS_SERIALBUS_SERCOS 0x08
453 #define PCIS_SERIALBUS_CANBUS 0x09
455 #define PCIC_WIRELESS 0x0d
456 #define PCIS_WIRELESS_IRDA 0x00
457 #define PCIS_WIRELESS_IR 0x01
458 #define PCIS_WIRELESS_RF 0x10
459 #define PCIS_WIRELESS_BLUETOOTH 0x11
460 #define PCIS_WIRELESS_BROADBAND 0x12
461 #define PCIS_WIRELESS_80211A 0x20
462 #define PCIS_WIRELESS_80211B 0x21
463 #define PCIS_WIRELESS_OTHER 0x80
465 #define PCIC_INTELLIIO 0x0e
466 #define PCIS_INTELLIIO_I2O 0x00
468 #define PCIC_SATCOM 0x0f
469 #define PCIS_SATCOM_TV 0x01
470 #define PCIS_SATCOM_AUDIO 0x02
471 #define PCIS_SATCOM_VOICE 0x03
472 #define PCIS_SATCOM_DATA 0x04
474 #define PCIC_CRYPTO 0x10
475 #define PCIS_CRYPTO_NETCOMP 0x00
476 #define PCIS_CRYPTO_ENTERTAIN 0x10
477 #define PCIS_CRYPTO_OTHER 0x80
479 #define PCIC_DASP 0x11
480 #define PCIS_DASP_DPIO 0x00
481 #define PCIS_DASP_PERFCNTRS 0x01
482 #define PCIS_DASP_COMM_SYNC 0x10
483 #define PCIS_DASP_MGMT_CARD 0x20
484 #define PCIS_DASP_OTHER 0x80
486 #define PCIC_ACCEL 0x12
487 #define PCIS_ACCEL_PROCESSING 0x00
489 #define PCIC_INSTRUMENT 0x13
491 #define PCIC_OTHER 0xff
493 /* Bridge Control Values. */
494 #define PCIB_BCR_PERR_ENABLE 0x0001
495 #define PCIB_BCR_SERR_ENABLE 0x0002
496 #define PCIB_BCR_ISA_ENABLE 0x0004
497 #define PCIB_BCR_VGA_ENABLE 0x0008
498 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020
499 #define PCIB_BCR_SECBUS_RESET 0x0040
500 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
501 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
502 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
503 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
504 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
506 #define CBB_BCR_PERR_ENABLE 0x0001
507 #define CBB_BCR_SERR_ENABLE 0x0002
508 #define CBB_BCR_ISA_ENABLE 0x0004
509 #define CBB_BCR_VGA_ENABLE 0x0008
510 #define CBB_BCR_MASTER_ABORT_MODE 0x0020
511 #define CBB_BCR_CARDBUS_RESET 0x0040
512 #define CBB_BCR_IREQ_INT_ENABLE 0x0080
513 #define CBB_BCR_PREFETCH_0_ENABLE 0x0100
514 #define CBB_BCR_PREFETCH_1_ENABLE 0x0200
515 #define CBB_BCR_WRITE_POSTING_ENABLE 0x0400
517 /* PCI power manangement */
518 #define PCIR_POWER_CAP 0x2
519 #define PCIM_PCAP_SPEC 0x0007
520 #define PCIM_PCAP_PMEREQCLK 0x0008
521 #define PCIM_PCAP_DEVSPECINIT 0x0020
522 #define PCIM_PCAP_AUXPWR_0 0x0000
523 #define PCIM_PCAP_AUXPWR_55 0x0040
524 #define PCIM_PCAP_AUXPWR_100 0x0080
525 #define PCIM_PCAP_AUXPWR_160 0x00c0
526 #define PCIM_PCAP_AUXPWR_220 0x0100
527 #define PCIM_PCAP_AUXPWR_270 0x0140
528 #define PCIM_PCAP_AUXPWR_320 0x0180
529 #define PCIM_PCAP_AUXPWR_375 0x01c0
530 #define PCIM_PCAP_AUXPWRMASK 0x01c0
531 #define PCIM_PCAP_D1SUPP 0x0200
532 #define PCIM_PCAP_D2SUPP 0x0400
533 #define PCIM_PCAP_D0PME 0x0800
534 #define PCIM_PCAP_D1PME 0x1000
535 #define PCIM_PCAP_D2PME 0x2000
536 #define PCIM_PCAP_D3PME_HOT 0x4000
537 #define PCIM_PCAP_D3PME_COLD 0x8000
539 #define PCIR_POWER_STATUS 0x4
540 #define PCIM_PSTAT_D0 0x0000
541 #define PCIM_PSTAT_D1 0x0001
542 #define PCIM_PSTAT_D2 0x0002
543 #define PCIM_PSTAT_D3 0x0003
544 #define PCIM_PSTAT_DMASK 0x0003
545 #define PCIM_PSTAT_NOSOFTRESET 0x0008
546 #define PCIM_PSTAT_PMEENABLE 0x0100
547 #define PCIM_PSTAT_D0POWER 0x0000
548 #define PCIM_PSTAT_D1POWER 0x0200
549 #define PCIM_PSTAT_D2POWER 0x0400
550 #define PCIM_PSTAT_D3POWER 0x0600
551 #define PCIM_PSTAT_D0HEAT 0x0800
552 #define PCIM_PSTAT_D1HEAT 0x0a00
553 #define PCIM_PSTAT_D2HEAT 0x0c00
554 #define PCIM_PSTAT_D3HEAT 0x0e00
555 #define PCIM_PSTAT_DATASELMASK 0x1e00
556 #define PCIM_PSTAT_DATAUNKN 0x0000
557 #define PCIM_PSTAT_DATADIV10 0x2000
558 #define PCIM_PSTAT_DATADIV100 0x4000
559 #define PCIM_PSTAT_DATADIV1000 0x6000
560 #define PCIM_PSTAT_DATADIVMASK 0x6000
561 #define PCIM_PSTAT_PME 0x8000
563 #define PCIR_POWER_BSE 0x6
564 #define PCIM_PMCSR_BSE_D3B3 0x00
565 #define PCIM_PMCSR_BSE_D3B2 0x40
566 #define PCIM_PMCSR_BSE_BPCCE 0x80
568 #define PCIR_POWER_DATA 0x7
570 /* VPD capability registers */
571 #define PCIR_VPD_ADDR 0x2
572 #define PCIR_VPD_DATA 0x4
574 /* PCI Message Signalled Interrupts (MSI) */
575 #define PCIR_MSI_CTRL 0x2
576 #define PCIM_MSICTRL_VECTOR 0x0100
577 #define PCIM_MSICTRL_64BIT 0x0080
578 #define PCIM_MSICTRL_MME_MASK 0x0070
579 #define PCIM_MSICTRL_MME_1 0x0000
580 #define PCIM_MSICTRL_MME_2 0x0010
581 #define PCIM_MSICTRL_MME_4 0x0020
582 #define PCIM_MSICTRL_MME_8 0x0030
583 #define PCIM_MSICTRL_MME_16 0x0040
584 #define PCIM_MSICTRL_MME_32 0x0050
585 #define PCIM_MSICTRL_MMC_MASK 0x000E
586 #define PCIM_MSICTRL_MMC_1 0x0000
587 #define PCIM_MSICTRL_MMC_2 0x0002
588 #define PCIM_MSICTRL_MMC_4 0x0004
589 #define PCIM_MSICTRL_MMC_8 0x0006
590 #define PCIM_MSICTRL_MMC_16 0x0008
591 #define PCIM_MSICTRL_MMC_32 0x000A
592 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
593 #define PCIR_MSI_ADDR 0x4
594 #define PCIR_MSI_ADDR_HIGH 0x8
595 #define PCIR_MSI_DATA 0x8
596 #define PCIR_MSI_DATA_64BIT 0xc
597 #define PCIR_MSI_MASK 0x10
598 #define PCIR_MSI_PENDING 0x14
600 /* PCI Enhanced Allocation registers */
601 #define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */
602 #define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
603 #define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */
604 #define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
605 #define PCIM_EA_ES 0x00000007 /* Entry Size */
606 #define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
607 #define PCIM_EA_BEI_OFFSET 4
608 /* 0-5 map to BARs 0-5 respectively */
609 #define PCIM_EA_BEI_BAR_0 0
610 #define PCIM_EA_BEI_BAR_5 5
611 #define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf)
612 #define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */
613 #define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */
614 #define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */
615 /* 9-14 map to VF BARs 0-5 respectively */
616 #define PCIM_EA_BEI_VF_BAR_0 9
617 #define PCIM_EA_BEI_VF_BAR_5 14
618 #define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */
619 #define PCIM_EA_PP 0x0000ff00 /* Primary Properties */
620 #define PCIM_EA_PP_OFFSET 8
621 #define PCIM_EA_SP_OFFSET 16
622 #define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */
623 #define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */
624 #define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */
625 #define PCIM_EA_P_IO 0x02 /* I/O Space */
626 #define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */
627 #define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
628 #define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
629 #define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */
630 #define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */
631 /* 0x08-0xfc reserved */
632 #define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */
633 #define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */
634 #define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */
635 #define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */
636 #define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */
637 #define PCIM_EA_BASE 4 /* Base Address Offset */
638 #define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */
639 /* bit 0 is reserved */
640 #define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */
641 #define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
642 /* Bridge config register */
643 #define PCIM_EA_SEC_NR(reg) ((reg) & 0xff)
644 #define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff)
646 /* PCI-X definitions */
648 /* For header type 0 devices */
649 #define PCIXR_COMMAND 0x2
650 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
651 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
652 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
653 #define PCIXM_COMMAND_MAX_READ_512 0x0000
654 #define PCIXM_COMMAND_MAX_READ_1024 0x0004
655 #define PCIXM_COMMAND_MAX_READ_2048 0x0008
656 #define PCIXM_COMMAND_MAX_READ_4096 0x000c
657 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
658 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
659 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
660 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
661 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
662 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
663 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
664 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
665 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
666 #define PCIXM_COMMAND_VERSION 0x3000
667 #define PCIXR_STATUS 0x4
668 #define PCIXM_STATUS_DEVFN 0x000000FF
669 #define PCIXM_STATUS_BUS 0x0000FF00
670 #define PCIXM_STATUS_64BIT 0x00010000
671 #define PCIXM_STATUS_133CAP 0x00020000
672 #define PCIXM_STATUS_SC_DISCARDED 0x00040000
673 #define PCIXM_STATUS_UNEXP_SC 0x00080000
674 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
675 #define PCIXM_STATUS_MAX_READ 0x00600000
676 #define PCIXM_STATUS_MAX_READ_512 0x00000000
677 #define PCIXM_STATUS_MAX_READ_1024 0x00200000
678 #define PCIXM_STATUS_MAX_READ_2048 0x00400000
679 #define PCIXM_STATUS_MAX_READ_4096 0x00600000
680 #define PCIXM_STATUS_MAX_SPLITS 0x03800000
681 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
682 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
683 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
684 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
685 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
686 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
687 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
688 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
689 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
690 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
691 #define PCIXM_STATUS_266CAP 0x40000000
692 #define PCIXM_STATUS_533CAP 0x80000000
694 /* For header type 1 devices (PCI-X bridges) */
695 #define PCIXR_SEC_STATUS 0x2
696 #define PCIXM_SEC_STATUS_64BIT 0x0001
697 #define PCIXM_SEC_STATUS_133CAP 0x0002
698 #define PCIXM_SEC_STATUS_SC_DISC 0x0004
699 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
700 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
701 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
702 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
703 #define PCIXM_SEC_STATUS_VERSION 0x3000
704 #define PCIXM_SEC_STATUS_266CAP 0x4000
705 #define PCIXM_SEC_STATUS_533CAP 0x8000
706 #define PCIXR_BRIDGE_STATUS 0x4
707 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
708 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
709 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
710 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
711 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
712 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
713 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
714 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
715 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
716 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
717 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
719 /* HT (HyperTransport) Capability definitions */
720 #define PCIR_HT_COMMAND 0x2
721 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
722 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
723 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */
724 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
725 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
726 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
727 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
728 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
729 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
730 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
731 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
732 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
733 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
734 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
735 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */
736 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */
737 #define PCIM_HTCAP_PM 0xe000 /* 11100 */
738 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */
740 /* HT MSI Mapping Capability definitions. */
741 #define PCIM_HTCMD_MSI_ENABLE 0x0001
742 #define PCIM_HTCMD_MSI_FIXED 0x0002
743 #define PCIR_HTMSI_ADDRESS_LO 0x4
744 #define PCIR_HTMSI_ADDRESS_HI 0x8
746 /* PCI Vendor capability definitions */
747 #define PCIR_VENDOR_LENGTH 0x2
748 #define PCIR_VENDOR_DATA 0x3
750 /* PCI Device capability definitions */
751 #define PCIR_DEVICE_LENGTH 0x2
753 /* PCI EHCI Debug Port definitions */
754 #define PCIR_DEBUG_PORT 0x2
755 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF
756 #define PCIM_DEBUG_PORT_BAR 0xe000
758 /* PCI-PCI Bridge Subvendor definitions */
759 #define PCIR_SUBVENDCAP_ID 0x4
761 /* PCI Express definitions */
762 #define PCIER_FLAGS 0x2
763 #define PCIEM_FLAGS_VERSION 0x000F
764 #define PCIEM_FLAGS_TYPE 0x00F0
765 #define PCIEM_TYPE_ENDPOINT 0x0000
766 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010
767 #define PCIEM_TYPE_ROOT_PORT 0x0040
768 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050
769 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060
770 #define PCIEM_TYPE_PCI_BRIDGE 0x0070
771 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080
772 #define PCIEM_TYPE_ROOT_INT_EP 0x0090
773 #define PCIEM_TYPE_ROOT_EC 0x00a0
774 #define PCIEM_FLAGS_SLOT 0x0100
775 #define PCIEM_FLAGS_IRQ 0x3e00
776 #define PCIER_DEVICE_CAP 0x4
777 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007
778 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018
779 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020
780 #define PCIEM_CAP_L0S_LATENCY 0x000001c0
781 #define PCIEM_CAP_L1_LATENCY 0x00000e00
782 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000
783 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000
784 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000
785 #define PCIEM_CAP_FLR 0x10000000
786 #define PCIER_DEVICE_CTL 0x8
787 #define PCIEM_CTL_COR_ENABLE 0x0001
788 #define PCIEM_CTL_NFER_ENABLE 0x0002
789 #define PCIEM_CTL_FER_ENABLE 0x0004
790 #define PCIEM_CTL_URR_ENABLE 0x0008
791 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010
792 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0
793 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100
794 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200
795 #define PCIEM_CTL_AUX_POWER_PM 0x0400
796 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800
797 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000
798 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */
799 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */
800 #define PCIER_DEVICE_STA 0xa
801 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001
802 #define PCIEM_STA_NON_FATAL_ERROR 0x0002
803 #define PCIEM_STA_FATAL_ERROR 0x0004
804 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008
805 #define PCIEM_STA_AUX_POWER 0x0010
806 #define PCIEM_STA_TRANSACTION_PND 0x0020
807 #define PCIER_LINK_CAP 0xc
808 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f
809 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0
810 #define PCIEM_LINK_CAP_ASPM 0x00000c00
811 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000
812 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000
813 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000
814 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000
815 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000
816 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000
817 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000
818 #define PCIEM_LINK_CAP_PORT 0xff000000
819 #define PCIER_LINK_CTL 0x10
820 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000
821 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001
822 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002
823 #define PCIEM_LINK_CTL_ASPMC 0x0003
824 #define PCIEM_LINK_CTL_RCB 0x0008
825 #define PCIEM_LINK_CTL_LINK_DIS 0x0010
826 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020
827 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040
828 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080
829 #define PCIEM_LINK_CTL_ECPM 0x0100
830 #define PCIEM_LINK_CTL_HAWD 0x0200
831 #define PCIEM_LINK_CTL_LBMIE 0x0400
832 #define PCIEM_LINK_CTL_LABIE 0x0800
833 #define PCIER_LINK_STA 0x12
834 #define PCIEM_LINK_STA_SPEED 0x000f
835 #define PCIEM_LINK_STA_WIDTH 0x03f0
836 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400
837 #define PCIEM_LINK_STA_TRAINING 0x0800
838 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000
839 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000
840 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000
841 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000
842 #define PCIER_SLOT_CAP 0x14
843 #define PCIEM_SLOT_CAP_APB 0x00000001
844 #define PCIEM_SLOT_CAP_PCP 0x00000002
845 #define PCIEM_SLOT_CAP_MRLSP 0x00000004
846 #define PCIEM_SLOT_CAP_AIP 0x00000008
847 #define PCIEM_SLOT_CAP_PIP 0x00000010
848 #define PCIEM_SLOT_CAP_HPS 0x00000020
849 #define PCIEM_SLOT_CAP_HPC 0x00000040
850 #define PCIEM_SLOT_CAP_SPLV 0x00007f80
851 #define PCIEM_SLOT_CAP_SPLS 0x00018000
852 #define PCIEM_SLOT_CAP_EIP 0x00020000
853 #define PCIEM_SLOT_CAP_NCCS 0x00040000
854 #define PCIEM_SLOT_CAP_PSN 0xfff80000
855 #define PCIER_SLOT_CTL 0x18
856 #define PCIEM_SLOT_CTL_ABPE 0x0001
857 #define PCIEM_SLOT_CTL_PFDE 0x0002
858 #define PCIEM_SLOT_CTL_MRLSCE 0x0004
859 #define PCIEM_SLOT_CTL_PDCE 0x0008
860 #define PCIEM_SLOT_CTL_CCIE 0x0010
861 #define PCIEM_SLOT_CTL_HPIE 0x0020
862 #define PCIEM_SLOT_CTL_AIC 0x00c0
863 #define PCIEM_SLOT_CTL_AI_ON 0x0040
864 #define PCIEM_SLOT_CTL_AI_BLINK 0x0080
865 #define PCIEM_SLOT_CTL_AI_OFF 0x00c0
866 #define PCIEM_SLOT_CTL_PIC 0x0300
867 #define PCIEM_SLOT_CTL_PI_ON 0x0100
868 #define PCIEM_SLOT_CTL_PI_BLINK 0x0200
869 #define PCIEM_SLOT_CTL_PI_OFF 0x0300
870 #define PCIEM_SLOT_CTL_PCC 0x0400
871 #define PCIEM_SLOT_CTL_PC_ON 0x0000
872 #define PCIEM_SLOT_CTL_PC_OFF 0x0400
873 #define PCIEM_SLOT_CTL_EIC 0x0800
874 #define PCIEM_SLOT_CTL_DLLSCE 0x1000
875 #define PCIER_SLOT_STA 0x1a
876 #define PCIEM_SLOT_STA_ABP 0x0001
877 #define PCIEM_SLOT_STA_PFD 0x0002
878 #define PCIEM_SLOT_STA_MRLSC 0x0004
879 #define PCIEM_SLOT_STA_PDC 0x0008
880 #define PCIEM_SLOT_STA_CC 0x0010
881 #define PCIEM_SLOT_STA_MRLSS 0x0020
882 #define PCIEM_SLOT_STA_PDS 0x0040
883 #define PCIEM_SLOT_STA_EIS 0x0080
884 #define PCIEM_SLOT_STA_DLLSC 0x0100
885 #define PCIER_ROOT_CTL 0x1c
886 #define PCIEM_ROOT_CTL_SERR_CORR 0x0001
887 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002
888 #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004
889 #define PCIEM_ROOT_CTL_PME 0x0008
890 #define PCIEM_ROOT_CTL_CRS_VIS 0x0010
891 #define PCIER_ROOT_CAP 0x1e
892 #define PCIEM_ROOT_CAP_CRS_VIS 0x0001
893 #define PCIER_ROOT_STA 0x20
894 #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff
895 #define PCIEM_ROOT_STA_PME_STATUS 0x00010000
896 #define PCIEM_ROOT_STA_PME_PEND 0x00020000
897 #define PCIER_DEVICE_CAP2 0x24
898 #define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f
899 #define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001
900 #define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002
901 #define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004
902 #define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008
903 #define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010
904 #define PCIEM_CAP2_ARI 0x00000020
905 #define PCIER_DEVICE_CTL2 0x28
906 #define PCIEM_CTL2_COMP_TIMO_VAL 0x000f
907 #define PCIEM_CTL2_COMP_TIMO_50MS 0x0000
908 #define PCIEM_CTL2_COMP_TIMO_100US 0x0001
909 #define PCIEM_CTL2_COMP_TIMO_10MS 0x0002
910 #define PCIEM_CTL2_COMP_TIMO_55MS 0x0005
911 #define PCIEM_CTL2_COMP_TIMO_210MS 0x0006
912 #define PCIEM_CTL2_COMP_TIMO_900MS 0x0009
913 #define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a
914 #define PCIEM_CTL2_COMP_TIMO_13S 0x000d
915 #define PCIEM_CTL2_COMP_TIMO_64S 0x000e
916 #define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010
917 #define PCIEM_CTL2_ARI 0x0020
918 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040
919 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080
920 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100
921 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200
922 #define PCIEM_CTL2_LTR_ENABLE 0x0400
923 #define PCIEM_CTL2_OBFF 0x6000
924 #define PCIEM_OBFF_DISABLE 0x0000
925 #define PCIEM_OBFF_MSGA_ENABLE 0x2000
926 #define PCIEM_OBFF_MSGB_ENABLE 0x4000
927 #define PCIEM_OBFF_WAKE_ENABLE 0x6000
928 #define PCIEM_CTL2_END2END_TLP 0x8000
929 #define PCIER_DEVICE_STA2 0x2a
930 #define PCIER_LINK_CAP2 0x2c
931 #define PCIER_LINK_CTL2 0x30
932 #define PCIER_LINK_STA2 0x32
933 #define PCIER_SLOT_CAP2 0x34
934 #define PCIER_SLOT_CTL2 0x38
935 #define PCIER_SLOT_STA2 0x3a
937 /* MSI-X definitions */
938 #define PCIR_MSIX_CTRL 0x2
939 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
940 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
941 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
942 #define PCIR_MSIX_TABLE 0x4
943 #define PCIR_MSIX_PBA 0x8
944 #define PCIM_MSIX_BIR_MASK 0x7
945 #define PCIM_MSIX_BIR_BAR_10 0
946 #define PCIM_MSIX_BIR_BAR_14 1
947 #define PCIM_MSIX_BIR_BAR_18 2
948 #define PCIM_MSIX_BIR_BAR_1C 3
949 #define PCIM_MSIX_BIR_BAR_20 4
950 #define PCIM_MSIX_BIR_BAR_24 5
951 #define PCIM_MSIX_VCTRL_MASK 0x1
953 /* PCI Advanced Features definitions */
954 #define PCIR_PCIAF_CAP 0x3
955 #define PCIM_PCIAFCAP_TP 0x01
956 #define PCIM_PCIAFCAP_FLR 0x02
957 #define PCIR_PCIAF_CTRL 0x4
958 #define PCIR_PCIAFCTRL_FLR 0x01
959 #define PCIR_PCIAF_STATUS 0x5
960 #define PCIR_PCIAFSTATUS_TP 0x01
962 /* Advanced Error Reporting */
963 #define PCIR_AER_UC_STATUS 0x04
964 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001
965 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010
966 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020
967 #define PCIM_AER_UC_POISONED_TLP 0x00001000
968 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000
969 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000
970 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000
971 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000
972 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000
973 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000
974 #define PCIM_AER_UC_ECRC_ERROR 0x00080000
975 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000
976 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000
977 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000
978 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000
979 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000
980 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000
981 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */
982 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */
983 #define PCIR_AER_COR_STATUS 0x10
984 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001
985 #define PCIM_AER_COR_BAD_TLP 0x00000040
986 #define PCIM_AER_COR_BAD_DLLP 0x00000080
987 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100
988 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000
989 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000
990 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000
991 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000
992 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */
993 #define PCIR_AER_CAP_CONTROL 0x18
994 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f
995 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020
996 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040
997 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080
998 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100
999 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200
1000 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400
1001 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800
1002 #define PCIR_AER_HEADER_LOG 0x1c
1003 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */
1004 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001
1005 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002
1006 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004
1007 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */
1008 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001
1009 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002
1010 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004
1011 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008
1012 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010
1013 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020
1014 #define PCIM_AER_ROOTERR_F_ERR 0x00000040
1015 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000
1016 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */
1017 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */
1018 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */
1020 /* Virtual Channel definitions */
1021 #define PCIR_VC_CAP1 0x04
1022 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007
1023 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070
1024 #define PCIR_VC_CAP2 0x08
1025 #define PCIR_VC_CONTROL 0x0C
1026 #define PCIR_VC_STATUS 0x0E
1027 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C)
1028 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C)
1029 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C)
1031 /* Serial Number definitions */
1032 #define PCIR_SERIAL_LOW 0x04
1033 #define PCIR_SERIAL_HIGH 0x08
1035 /* SR-IOV definitions */
1036 #define PCIR_SRIOV_CTL 0x08
1037 #define PCIM_SRIOV_VF_EN 0x01
1038 #define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */
1039 #define PCIM_SRIOV_ARI_EN 0x10
1040 #define PCIR_SRIOV_TOTAL_VFS 0x0E
1041 #define PCIR_SRIOV_NUM_VFS 0x10
1042 #define PCIR_SRIOV_VF_OFF 0x14
1043 #define PCIR_SRIOV_VF_STRIDE 0x16
1044 #define PCIR_SRIOV_VF_DID 0x1A
1045 #define PCIR_SRIOV_PAGE_CAP 0x1C
1046 #define PCIR_SRIOV_PAGE_SIZE 0x20
1048 #define PCI_SRIOV_BASE_PAGE_SHIFT 12
1050 #define PCIR_SRIOV_BARS 0x24
1051 #define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4)
1054 * PCI Express Firmware Interface definitions
1056 #define PCI_OSC_STATUS 0
1057 #define PCI_OSC_SUPPORT 1
1058 #define PCIM_OSC_SUPPORT_EXT_PCI_CONF 0x01 /* Extended PCI Config Space */
1059 #define PCIM_OSC_SUPPORT_ASPM 0x02 /* Active State Power Management */
1060 #define PCIM_OSC_SUPPORT_CPMC 0x04 /* Clock Power Management Cap */
1061 #define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */
1062 #define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */
1063 #define PCI_OSC_CTL 2
1064 #define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */
1065 #define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */
1066 #define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */
1067 #define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */
1068 #define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
projects / FreeBSD / FreeBSD.git / blob