2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/queue.h>
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
40 typedef uint64_t pci_addr_t;
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
51 /* Interesting values for PCI power management */
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
56 uint8_t pp_data; /* conf. space addr. of PM data reg */
60 pci_addr_t pm_value; /* Raw BAR value */
63 STAILQ_ENTRY(pci_map) pm_link;
80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
82 char *vpd_ident; /* string identifier */
84 struct vpd_readonly *vpd_ros;
86 struct vpd_write *vpd_w;
89 /* Interesting values for PCI MSI */
91 uint16_t msi_ctrl; /* Message Control */
92 uint8_t msi_location; /* Offset of MSI capability registers. */
93 uint8_t msi_msgnum; /* Number of messages */
94 int msi_alloc; /* Number of allocated messages. */
95 uint64_t msi_addr; /* Contents of address register. */
96 uint16_t msi_data; /* Contents of data register. */
100 /* Interesting values for PCI MSI-X */
102 uint64_t mv_address; /* Contents of address register. */
103 uint32_t mv_data; /* Contents of data register. */
107 struct msix_table_entry {
108 u_int mte_vector; /* 1-based index into msix_vectors array. */
113 uint16_t msix_ctrl; /* Message Control */
114 uint16_t msix_msgnum; /* Number of messages */
115 uint8_t msix_location; /* Offset of MSI-X capability registers. */
116 uint8_t msix_table_bar; /* BAR containing vector table. */
117 uint8_t msix_pba_bar; /* BAR containing PBA. */
118 uint32_t msix_table_offset;
119 uint32_t msix_pba_offset;
120 int msix_alloc; /* Number of allocated vectors. */
121 int msix_table_len; /* Length of virtual table. */
122 struct msix_table_entry *msix_table; /* Virtual table. */
123 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
124 struct resource *msix_table_res; /* Resource containing vector table. */
125 struct resource *msix_pba_res; /* Resource containing PBA. */
128 /* Interesting values for HyperTransport */
130 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
131 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
132 uint16_t ht_msictrl; /* MSI mapping control */
133 uint64_t ht_msiaddr; /* MSI mapping base address */
136 /* Interesting values for PCI-express */
138 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
139 uint8_t pcie_type; /* Device type. */
140 uint16_t pcie_flags; /* Device capabilities register. */
141 uint16_t pcie_device_ctl; /* Device control register. */
142 uint16_t pcie_link_ctl; /* Link control register. */
143 uint16_t pcie_slot_ctl; /* Slot control register. */
144 uint16_t pcie_root_ctl; /* Root control register. */
145 uint16_t pcie_device_ctl2; /* Second device control register. */
146 uint16_t pcie_link_ctl2; /* Second link control register. */
147 uint16_t pcie_slot_ctl2; /* Second slot control register. */
151 uint16_t pcix_command;
152 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
159 struct pci_ea_entry {
163 uint64_t eae_max_offset;
164 uint32_t eae_cfg_offset;
165 STAILQ_ENTRY(pci_ea_entry) eae_link;
169 int ea_location; /* Structure offset in Configuration Header */
170 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
173 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
175 /* config header information common to all header types */
176 typedef struct pcicfg {
177 struct device *dev; /* device which owns this */
179 STAILQ_HEAD(, pci_map) maps; /* BARs */
181 uint16_t subvendor; /* card vendor ID */
182 uint16_t subdevice; /* card device ID, assigned by card vendor */
183 uint16_t vendor; /* chip vendor ID */
184 uint16_t device; /* chip device ID, assigned by chip vendor */
186 uint16_t cmdreg; /* disable/enable chip and PCI options */
187 uint16_t statreg; /* supported PCI features and error state */
189 uint8_t baseclass; /* chip PCI class */
190 uint8_t subclass; /* chip PCI subclass */
191 uint8_t progif; /* chip PCI programming interface */
192 uint8_t revid; /* chip revision ID */
194 uint8_t hdrtype; /* chip config header type */
195 uint8_t cachelnsz; /* cache line size in 4byte units */
196 uint8_t intpin; /* PCI interrupt pin */
197 uint8_t intline; /* interrupt line (IRQ for PC arch) */
199 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
200 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
201 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
203 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
204 uint8_t nummaps; /* actual number of PCI maps used */
206 uint32_t domain; /* PCI domain */
207 uint8_t bus; /* config space bus address */
208 uint8_t slot; /* config space slot address */
209 uint8_t func; /* config space function number */
211 uint32_t flags; /* flags defined above */
213 struct pcicfg_bridge bridge; /* Bridges */
214 struct pcicfg_pp pp; /* Power management */
215 struct pcicfg_vpd vpd; /* Vital product data */
216 struct pcicfg_msi msi; /* PCI MSI */
217 struct pcicfg_msix msix; /* PCI MSI-X */
218 struct pcicfg_ht ht; /* HyperTransport */
219 struct pcicfg_pcie pcie; /* PCI Express */
220 struct pcicfg_pcix pcix; /* PCI-X */
221 struct pcicfg_iov *iov; /* SR-IOV */
222 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
223 struct pcicfg_ea ea; /* Enhanced Allocation */
226 /* additional type 1 device config header information (PCI to PCI bridge) */
229 pci_addr_t pmembase; /* base address of prefetchable memory */
230 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
231 uint32_t membase; /* base address of memory window */
232 uint32_t memlimit; /* topmost address of memory window */
233 uint32_t iobase; /* base address of port window */
234 uint32_t iolimit; /* topmost address of port window */
235 uint16_t secstat; /* secondary bus status register */
236 uint16_t bridgectl; /* bridge control register */
237 uint8_t seclat; /* CardBus latency timer */
240 /* additional type 2 device config header information (CardBus bridge) */
243 uint32_t membase0; /* base address of memory window */
244 uint32_t memlimit0; /* topmost address of memory window */
245 uint32_t membase1; /* base address of memory window */
246 uint32_t memlimit1; /* topmost address of memory window */
247 uint32_t iobase0; /* base address of port window */
248 uint32_t iolimit0; /* topmost address of port window */
249 uint32_t iobase1; /* base address of port window */
250 uint32_t iolimit1; /* topmost address of port window */
251 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
252 uint16_t secstat; /* secondary bus status register */
253 uint16_t bridgectl; /* bridge control register */
254 uint8_t seclat; /* CardBus latency timer */
257 extern uint32_t pci_numdevs;
259 /* Only if the prerequisites are present */
260 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
262 STAILQ_ENTRY(pci_devinfo) pci_links;
263 struct resource_list resources;
265 struct pci_conf conf;
273 enum pci_device_ivars {
298 * Simplified accessors for pci devices
300 #define PCI_ACCESSOR(var, ivar, type) \
301 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
303 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
304 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
305 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
306 PCI_ACCESSOR(device, DEVICE, uint16_t)
307 PCI_ACCESSOR(devid, DEVID, uint32_t)
308 PCI_ACCESSOR(class, CLASS, uint8_t)
309 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
310 PCI_ACCESSOR(progif, PROGIF, uint8_t)
311 PCI_ACCESSOR(revid, REVID, uint8_t)
312 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
313 PCI_ACCESSOR(irq, IRQ, uint8_t)
314 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
315 PCI_ACCESSOR(bus, BUS, uint8_t)
316 PCI_ACCESSOR(slot, SLOT, uint8_t)
317 PCI_ACCESSOR(function, FUNCTION, uint8_t)
318 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
319 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
320 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
321 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
322 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
323 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
328 * Operations on configuration space.
330 static __inline uint32_t
331 pci_read_config(device_t dev, int reg, int width)
333 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
337 pci_write_config(device_t dev, int reg, uint32_t val, int width)
339 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
343 * Ivars for pci bridges.
346 /*typedef enum pci_device_ivars pcib_device_ivars;*/
347 enum pcib_device_ivars {
352 #define PCIB_ACCESSOR(var, ivar, type) \
353 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
355 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
356 PCIB_ACCESSOR(bus, BUS, uint32_t)
361 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
362 * on i386 or other platforms should be mapped out in the MD pcireadconf
363 * code and not here, since the only MI invalid IRQ is 255.
365 #define PCI_INVALID_IRQ 255
366 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
369 * Convenience functions.
371 * These should be used in preference to manually manipulating
372 * configuration space.
375 pci_enable_busmaster(device_t dev)
377 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
381 pci_disable_busmaster(device_t dev)
383 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
387 pci_enable_io(device_t dev, int space)
389 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
393 pci_disable_io(device_t dev, int space)
395 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
399 pci_get_vpd_ident(device_t dev, const char **identptr)
401 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
405 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
407 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
411 * Check if the address range falls within the VGA defined address range(s)
414 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
417 return (((start >= 0x3b0 && end <= 0x3bb) ||
418 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
422 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
425 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
429 * PCI power states are as defined by ACPI:
431 * D0 State in which device is on and running. It is receiving full
432 * power from the system and delivering full functionality to the user.
433 * D1 Class-specific low-power state in which device context may or may not
434 * be lost. Buses in D1 cannot do anything to the bus that would force
435 * devices on that bus to lose context.
436 * D2 Class-specific low-power state in which device context may or may
437 * not be lost. Attains greater power savings than D1. Buses in D2
438 * can cause devices on that bus to lose some context. Devices in D2
439 * must be prepared for the bus to be in D2 or higher.
440 * D3 State in which the device is off and not running. Device context is
441 * lost. Power can be removed from the device.
443 #define PCI_POWERSTATE_D0 0
444 #define PCI_POWERSTATE_D1 1
445 #define PCI_POWERSTATE_D2 2
446 #define PCI_POWERSTATE_D3 3
447 #define PCI_POWERSTATE_UNKNOWN -1
450 pci_set_powerstate(device_t dev, int state)
452 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
456 pci_get_powerstate(device_t dev)
458 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
462 pci_find_cap(device_t dev, int capability, int *capreg)
464 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
468 pci_find_extcap(device_t dev, int capability, int *capreg)
470 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
474 pci_find_htcap(device_t dev, int capability, int *capreg)
476 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
480 pci_alloc_msi(device_t dev, int *count)
482 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
486 pci_alloc_msix(device_t dev, int *count)
488 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
492 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
494 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
498 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
500 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
504 pci_disable_msi(device_t dev)
506 PCI_DISABLE_MSI(device_get_parent(dev), dev);
510 pci_remap_msix(device_t dev, int count, const u_int *vectors)
512 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
516 pci_release_msi(device_t dev)
518 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
522 pci_msi_count(device_t dev)
524 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
528 pci_msix_count(device_t dev)
530 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
534 pci_msix_pba_bar(device_t dev)
536 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
540 pci_msix_table_bar(device_t dev)
542 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
546 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
548 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
552 * This is the deprecated interface, there is no way to tell the difference
553 * between a failure and a valid value that happens to be the same as the
556 static __inline uint16_t
557 pci_get_rid(device_t dev)
561 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
568 pci_child_added(device_t dev)
571 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
574 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
575 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
576 device_t pci_find_device(uint16_t, uint16_t);
577 device_t pci_find_class(uint8_t class, uint8_t subclass);
579 /* Can be used by drivers to manage the MSI-X table. */
580 int pci_pending_msix(device_t dev, u_int index);
582 int pci_msi_device_blacklisted(device_t dev);
583 int pci_msix_device_blacklisted(device_t dev);
585 void pci_ht_map_msi(device_t dev, uint64_t addr);
587 device_t pci_find_pcie_root_port(device_t dev);
588 int pci_get_max_read_req(device_t dev);
589 void pci_restore_state(device_t dev);
590 void pci_save_state(device_t dev);
591 int pci_set_max_read_req(device_t dev, int size);
592 uint32_t pcie_read_config(device_t dev, int reg, int width);
593 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
594 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
595 uint32_t value, int width);
598 #ifdef BUS_SPACE_MAXADDR
599 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
600 #define PCI_DMA_BOUNDARY 0x100000000
602 #define PCI_DMA_BOUNDARY 0
606 #endif /* _SYS_BUS_H_ */
609 * cdev switch for control device, initialised in generic PCI code
611 extern struct cdevsw pcicdev;
614 * List of all PCI devices, generation count for the list.
616 STAILQ_HEAD(devlist, pci_devinfo);
618 extern struct devlist pci_devq;
619 extern uint32_t pci_generation;
621 struct pci_map *pci_find_bar(device_t dev, int reg);
622 int pci_bar_enabled(device_t dev, struct pci_map *pm);
623 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
625 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
626 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
628 int vga_pci_is_boot_display(device_t dev);
629 void * vga_pci_map_bios(device_t dev, size_t *size);
630 void vga_pci_unmap_bios(device_t dev, void *bios);
631 int vga_pci_repost(device_t dev);
633 #endif /* _PCIVAR_H_ */