2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
36 #include <sys/eventhandler.h>
38 /* some PCI bus constants */
39 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
40 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
41 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
43 typedef uint64_t pci_addr_t;
45 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
46 struct pcicfg_bridge {
54 /* Interesting values for PCI power management */
56 uint16_t pp_cap; /* PCI power management capabilities */
57 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
58 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
59 uint8_t pp_data; /* conf. space addr. of PM data reg */
63 pci_addr_t pm_value; /* Raw BAR value */
66 STAILQ_ENTRY(pci_map) pm_link;
83 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
85 char *vpd_ident; /* string identifier */
87 struct vpd_readonly *vpd_ros;
89 struct vpd_write *vpd_w;
92 /* Interesting values for PCI MSI */
94 uint16_t msi_ctrl; /* Message Control */
95 uint8_t msi_location; /* Offset of MSI capability registers. */
96 uint8_t msi_msgnum; /* Number of messages */
97 int msi_alloc; /* Number of allocated messages. */
98 uint64_t msi_addr; /* Contents of address register. */
99 uint16_t msi_data; /* Contents of data register. */
103 /* Interesting values for PCI MSI-X */
105 uint64_t mv_address; /* Contents of address register. */
106 uint32_t mv_data; /* Contents of data register. */
110 struct msix_table_entry {
111 u_int mte_vector; /* 1-based index into msix_vectors array. */
116 uint16_t msix_ctrl; /* Message Control */
117 uint16_t msix_msgnum; /* Number of messages */
118 uint8_t msix_location; /* Offset of MSI-X capability registers. */
119 uint8_t msix_table_bar; /* BAR containing vector table. */
120 uint8_t msix_pba_bar; /* BAR containing PBA. */
121 uint32_t msix_table_offset;
122 uint32_t msix_pba_offset;
123 int msix_alloc; /* Number of allocated vectors. */
124 int msix_table_len; /* Length of virtual table. */
125 struct msix_table_entry *msix_table; /* Virtual table. */
126 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
127 struct resource *msix_table_res; /* Resource containing vector table. */
128 struct resource *msix_pba_res; /* Resource containing PBA. */
131 /* Interesting values for HyperTransport */
133 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
134 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
135 uint16_t ht_msictrl; /* MSI mapping control */
136 uint64_t ht_msiaddr; /* MSI mapping base address */
139 /* Interesting values for PCI-express */
141 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
142 uint8_t pcie_type; /* Device type. */
143 uint16_t pcie_flags; /* Device capabilities register. */
144 uint16_t pcie_device_ctl; /* Device control register. */
145 uint16_t pcie_link_ctl; /* Link control register. */
146 uint16_t pcie_slot_ctl; /* Slot control register. */
147 uint16_t pcie_root_ctl; /* Root control register. */
148 uint16_t pcie_device_ctl2; /* Second device control register. */
149 uint16_t pcie_link_ctl2; /* Second link control register. */
150 uint16_t pcie_slot_ctl2; /* Second slot control register. */
154 uint16_t pcix_command;
155 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
162 struct pci_ea_entry {
166 uint64_t eae_max_offset;
167 uint32_t eae_cfg_offset;
168 STAILQ_ENTRY(pci_ea_entry) eae_link;
172 int ea_location; /* Structure offset in Configuration Header */
173 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
176 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
178 /* config header information common to all header types */
179 typedef struct pcicfg {
180 device_t dev; /* device which owns this */
182 STAILQ_HEAD(, pci_map) maps; /* BARs */
184 uint16_t subvendor; /* card vendor ID */
185 uint16_t subdevice; /* card device ID, assigned by card vendor */
186 uint16_t vendor; /* chip vendor ID */
187 uint16_t device; /* chip device ID, assigned by chip vendor */
189 uint16_t cmdreg; /* disable/enable chip and PCI options */
190 uint16_t statreg; /* supported PCI features and error state */
192 uint8_t baseclass; /* chip PCI class */
193 uint8_t subclass; /* chip PCI subclass */
194 uint8_t progif; /* chip PCI programming interface */
195 uint8_t revid; /* chip revision ID */
197 uint8_t hdrtype; /* chip config header type */
198 uint8_t cachelnsz; /* cache line size in 4byte units */
199 uint8_t intpin; /* PCI interrupt pin */
200 uint8_t intline; /* interrupt line (IRQ for PC arch) */
202 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
203 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
204 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
206 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
207 uint8_t nummaps; /* actual number of PCI maps used */
209 uint32_t domain; /* PCI domain */
210 uint8_t bus; /* config space bus address */
211 uint8_t slot; /* config space slot address */
212 uint8_t func; /* config space function number */
214 uint32_t flags; /* flags defined above */
216 struct pcicfg_bridge bridge; /* Bridges */
217 struct pcicfg_pp pp; /* Power management */
218 struct pcicfg_vpd vpd; /* Vital product data */
219 struct pcicfg_msi msi; /* PCI MSI */
220 struct pcicfg_msix msix; /* PCI MSI-X */
221 struct pcicfg_ht ht; /* HyperTransport */
222 struct pcicfg_pcie pcie; /* PCI Express */
223 struct pcicfg_pcix pcix; /* PCI-X */
224 struct pcicfg_iov *iov; /* SR-IOV */
225 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
226 struct pcicfg_ea ea; /* Enhanced Allocation */
229 /* additional type 1 device config header information (PCI to PCI bridge) */
232 pci_addr_t pmembase; /* base address of prefetchable memory */
233 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
234 uint32_t membase; /* base address of memory window */
235 uint32_t memlimit; /* topmost address of memory window */
236 uint32_t iobase; /* base address of port window */
237 uint32_t iolimit; /* topmost address of port window */
238 uint16_t secstat; /* secondary bus status register */
239 uint16_t bridgectl; /* bridge control register */
240 uint8_t seclat; /* CardBus latency timer */
243 /* additional type 2 device config header information (CardBus bridge) */
246 uint32_t membase0; /* base address of memory window */
247 uint32_t memlimit0; /* topmost address of memory window */
248 uint32_t membase1; /* base address of memory window */
249 uint32_t memlimit1; /* topmost address of memory window */
250 uint32_t iobase0; /* base address of port window */
251 uint32_t iolimit0; /* topmost address of port window */
252 uint32_t iobase1; /* base address of port window */
253 uint32_t iolimit1; /* topmost address of port window */
254 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
255 uint16_t secstat; /* secondary bus status register */
256 uint16_t bridgectl; /* bridge control register */
257 uint8_t seclat; /* CardBus latency timer */
260 extern uint32_t pci_numdevs;
263 * The bitfield has to be stable and match the fields below (so that
264 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't
265 * use enums or #define constants because then the macros for subsetting matches
266 * wouldn't work. These tables are parsed by devmatch and others to connect
267 * modules with devices on the PCI bus.
269 struct pci_device_table {
270 #if BYTE_ORDER == LITTLE_ENDIAN
274 match_flag_subvendor:1,
275 match_flag_subdevice:1,
277 match_flag_subclass:1,
284 match_flag_subclass:1,
286 match_flag_subdevice:1,
287 match_flag_subvendor:1,
299 uintptr_t driver_data;
303 #define PCI_DEV(v, d) \
304 .match_flag_vendor = 1, .vendor = (v), \
305 .match_flag_device = 1, .device = (d)
306 #define PCI_SUBDEV(sv, sd) \
307 .match_flag_subvendor = 1, .subvendor = (sv), \
308 .match_flag_subdevice = 1, .subdevice = (sd)
309 #define PCI_CLASS(x) \
310 .match_flag_class = 1, .class_id = (x)
311 #define PCI_SUBCLASS(x) \
312 .match_flag_subclass = 1, .subclass = (x)
313 #define PCI_REVID(x) \
314 .match_flag_revid = 1, .revid = (x)
315 #define PCI_DESCR(x) \
317 #define PCI_PNP_STR \
318 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
319 "U16:class;U16:subclass;U16:revid;"
320 #define PCI_PNP_INFO(table) \
321 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
322 sizeof(table) / sizeof(table[0]))
324 const struct pci_device_table *pci_match_device(device_t child,
325 const struct pci_device_table *id, size_t nelt);
326 #define PCI_MATCH(child, table) \
327 pci_match_device(child, (table), nitems(table));
329 /* Only if the prerequisites are present */
330 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
332 STAILQ_ENTRY(pci_devinfo) pci_links;
333 struct resource_list resources;
335 struct pci_conf conf;
343 enum pci_device_ivars {
368 * Simplified accessors for pci devices
370 #define PCI_ACCESSOR(var, ivar, type) \
371 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
373 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
374 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
375 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
376 PCI_ACCESSOR(device, DEVICE, uint16_t)
377 PCI_ACCESSOR(devid, DEVID, uint32_t)
378 PCI_ACCESSOR(class, CLASS, uint8_t)
379 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
380 PCI_ACCESSOR(progif, PROGIF, uint8_t)
381 PCI_ACCESSOR(revid, REVID, uint8_t)
382 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
383 PCI_ACCESSOR(irq, IRQ, uint8_t)
384 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
385 PCI_ACCESSOR(bus, BUS, uint8_t)
386 PCI_ACCESSOR(slot, SLOT, uint8_t)
387 PCI_ACCESSOR(function, FUNCTION, uint8_t)
388 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
389 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
390 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
391 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
392 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
393 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
398 * Operations on configuration space.
400 static __inline uint32_t
401 pci_read_config(device_t dev, int reg, int width)
403 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
407 pci_write_config(device_t dev, int reg, uint32_t val, int width)
409 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
413 * Ivars for pci bridges.
416 /*typedef enum pci_device_ivars pcib_device_ivars;*/
417 enum pcib_device_ivars {
422 #define PCIB_ACCESSOR(var, ivar, type) \
423 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
425 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
426 PCIB_ACCESSOR(bus, BUS, uint32_t)
431 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
432 * on i386 or other platforms should be mapped out in the MD pcireadconf
433 * code and not here, since the only MI invalid IRQ is 255.
435 #define PCI_INVALID_IRQ 255
436 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
439 * Convenience functions.
441 * These should be used in preference to manually manipulating
442 * configuration space.
445 pci_enable_busmaster(device_t dev)
447 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
451 pci_disable_busmaster(device_t dev)
453 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
457 pci_enable_io(device_t dev, int space)
459 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
463 pci_disable_io(device_t dev, int space)
465 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
469 pci_get_vpd_ident(device_t dev, const char **identptr)
471 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
475 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
477 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
481 * Check if the address range falls within the VGA defined address range(s)
484 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
487 return (((start >= 0x3b0 && end <= 0x3bb) ||
488 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
492 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
495 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
499 * PCI power states are as defined by ACPI:
501 * D0 State in which device is on and running. It is receiving full
502 * power from the system and delivering full functionality to the user.
503 * D1 Class-specific low-power state in which device context may or may not
504 * be lost. Buses in D1 cannot do anything to the bus that would force
505 * devices on that bus to lose context.
506 * D2 Class-specific low-power state in which device context may or may
507 * not be lost. Attains greater power savings than D1. Buses in D2
508 * can cause devices on that bus to lose some context. Devices in D2
509 * must be prepared for the bus to be in D2 or higher.
510 * D3 State in which the device is off and not running. Device context is
511 * lost. Power can be removed from the device.
513 #define PCI_POWERSTATE_D0 0
514 #define PCI_POWERSTATE_D1 1
515 #define PCI_POWERSTATE_D2 2
516 #define PCI_POWERSTATE_D3 3
517 #define PCI_POWERSTATE_UNKNOWN -1
520 pci_set_powerstate(device_t dev, int state)
522 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
526 pci_get_powerstate(device_t dev)
528 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
532 pci_find_cap(device_t dev, int capability, int *capreg)
534 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
538 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
540 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
545 pci_find_extcap(device_t dev, int capability, int *capreg)
547 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
551 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
553 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
558 pci_find_htcap(device_t dev, int capability, int *capreg)
560 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
564 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
566 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
571 pci_alloc_msi(device_t dev, int *count)
573 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
577 pci_alloc_msix(device_t dev, int *count)
579 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
583 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
585 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
589 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
591 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
595 pci_disable_msi(device_t dev)
597 PCI_DISABLE_MSI(device_get_parent(dev), dev);
601 pci_remap_msix(device_t dev, int count, const u_int *vectors)
603 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
607 pci_release_msi(device_t dev)
609 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
613 pci_msi_count(device_t dev)
615 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
619 pci_msix_count(device_t dev)
621 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
625 pci_msix_pba_bar(device_t dev)
627 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
631 pci_msix_table_bar(device_t dev)
633 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
637 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
639 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
643 * This is the deprecated interface, there is no way to tell the difference
644 * between a failure and a valid value that happens to be the same as the
647 static __inline uint16_t
648 pci_get_rid(device_t dev)
652 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
659 pci_child_added(device_t dev)
662 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
665 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
666 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
667 device_t pci_find_device(uint16_t, uint16_t);
668 device_t pci_find_class(uint8_t class, uint8_t subclass);
670 /* Can be used by drivers to manage the MSI-X table. */
671 int pci_pending_msix(device_t dev, u_int index);
673 int pci_msi_device_blacklisted(device_t dev);
674 int pci_msix_device_blacklisted(device_t dev);
676 void pci_ht_map_msi(device_t dev, uint64_t addr);
678 device_t pci_find_pcie_root_port(device_t dev);
679 int pci_get_max_payload(device_t dev);
680 int pci_get_max_read_req(device_t dev);
681 void pci_restore_state(device_t dev);
682 void pci_save_state(device_t dev);
683 int pci_set_max_read_req(device_t dev, int size);
684 int pci_power_reset(device_t dev);
685 uint32_t pcie_read_config(device_t dev, int reg, int width);
686 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
687 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
688 uint32_t value, int width);
689 bool pcie_flr(device_t dev, u_int max_delay, bool force);
690 int pcie_get_max_completion_timeout(device_t dev);
691 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
692 int pcie_link_reset(device_t port, int pcie_location);
694 void pci_print_faulted_dev(void);
696 #ifdef BUS_SPACE_MAXADDR
697 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
698 #define PCI_DMA_BOUNDARY 0x100000000
700 #define PCI_DMA_BOUNDARY 0
704 #endif /* _SYS_BUS_H_ */
707 * cdev switch for control device, initialised in generic PCI code
709 extern struct cdevsw pcicdev;
712 * List of all PCI devices, generation count for the list.
714 STAILQ_HEAD(devlist, pci_devinfo);
716 extern struct devlist pci_devq;
717 extern uint32_t pci_generation;
719 struct pci_map *pci_find_bar(device_t dev, int reg);
720 int pci_bar_enabled(device_t dev, struct pci_map *pm);
721 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
723 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
724 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
726 int vga_pci_is_boot_display(device_t dev);
727 void * vga_pci_map_bios(device_t dev, size_t *size);
728 void vga_pci_unmap_bios(device_t dev, void *bios);
729 int vga_pci_repost(device_t dev);
732 * Global eventhandlers invoked when PCI devices are added or removed
735 typedef void (*pci_event_fn)(void *arg, device_t dev);
736 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
737 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
739 #endif /* _PCIVAR_H_ */