2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/queue.h>
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
40 typedef uint64_t pci_addr_t;
42 /* Interesting values for PCI power management */
44 uint16_t pp_cap; /* PCI power management capabilities */
45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
47 uint8_t pp_data; /* conf. space addr. of PM data reg */
51 pci_addr_t pm_value; /* Raw BAR value */
54 STAILQ_ENTRY(pci_map) pm_link;
70 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
72 char *vpd_ident; /* string identifier */
74 struct vpd_readonly *vpd_ros;
76 struct vpd_write *vpd_w;
79 /* Interesting values for PCI MSI */
81 uint16_t msi_ctrl; /* Message Control */
82 uint8_t msi_location; /* Offset of MSI capability registers. */
83 uint8_t msi_msgnum; /* Number of messages */
84 int msi_alloc; /* Number of allocated messages. */
85 uint64_t msi_addr; /* Contents of address register. */
86 uint16_t msi_data; /* Contents of data register. */
90 /* Interesting values for PCI MSI-X */
92 uint64_t mv_address; /* Contents of address register. */
93 uint32_t mv_data; /* Contents of data register. */
97 struct msix_table_entry {
98 u_int mte_vector; /* 1-based index into msix_vectors array. */
103 uint16_t msix_ctrl; /* Message Control */
104 uint16_t msix_msgnum; /* Number of messages */
105 uint8_t msix_location; /* Offset of MSI-X capability registers. */
106 uint8_t msix_table_bar; /* BAR containing vector table. */
107 uint8_t msix_pba_bar; /* BAR containing PBA. */
108 uint32_t msix_table_offset;
109 uint32_t msix_pba_offset;
110 int msix_alloc; /* Number of allocated vectors. */
111 int msix_table_len; /* Length of virtual table. */
112 struct msix_table_entry *msix_table; /* Virtual table. */
113 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
114 struct resource *msix_table_res; /* Resource containing vector table. */
115 struct resource *msix_pba_res; /* Resource containing PBA. */
118 /* Interesting values for HyperTransport */
120 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
121 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
122 uint16_t ht_msictrl; /* MSI mapping control */
123 uint64_t ht_msiaddr; /* MSI mapping base address */
126 /* Interesting values for PCI-express */
128 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
129 uint8_t pcie_type; /* Device type. */
130 uint16_t pcie_flags; /* Device capabilities register. */
131 uint16_t pcie_device_ctl; /* Device control register. */
132 uint16_t pcie_link_ctl; /* Link control register. */
133 uint16_t pcie_slot_ctl; /* Slot control register. */
134 uint16_t pcie_root_ctl; /* Root control register. */
135 uint16_t pcie_device_ctl2; /* Second device control register. */
136 uint16_t pcie_link_ctl2; /* Second link control register. */
137 uint16_t pcie_slot_ctl2; /* Second slot control register. */
141 uint16_t pcix_command;
142 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
145 /* config header information common to all header types */
146 typedef struct pcicfg {
147 struct device *dev; /* device which owns this */
149 STAILQ_HEAD(, pci_map) maps; /* BARs */
151 uint16_t subvendor; /* card vendor ID */
152 uint16_t subdevice; /* card device ID, assigned by card vendor */
153 uint16_t vendor; /* chip vendor ID */
154 uint16_t device; /* chip device ID, assigned by chip vendor */
156 uint16_t cmdreg; /* disable/enable chip and PCI options */
157 uint16_t statreg; /* supported PCI features and error state */
159 uint8_t baseclass; /* chip PCI class */
160 uint8_t subclass; /* chip PCI subclass */
161 uint8_t progif; /* chip PCI programming interface */
162 uint8_t revid; /* chip revision ID */
164 uint8_t hdrtype; /* chip config header type */
165 uint8_t cachelnsz; /* cache line size in 4byte units */
166 uint8_t intpin; /* PCI interrupt pin */
167 uint8_t intline; /* interrupt line (IRQ for PC arch) */
169 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
170 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
171 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
173 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
174 uint8_t nummaps; /* actual number of PCI maps used */
176 uint32_t domain; /* PCI domain */
177 uint8_t bus; /* config space bus address */
178 uint8_t slot; /* config space slot address */
179 uint8_t func; /* config space function number */
181 struct pcicfg_pp pp; /* Power management */
182 struct pcicfg_vpd vpd; /* Vital product data */
183 struct pcicfg_msi msi; /* PCI MSI */
184 struct pcicfg_msix msix; /* PCI MSI-X */
185 struct pcicfg_ht ht; /* HyperTransport */
186 struct pcicfg_pcie pcie; /* PCI Express */
187 struct pcicfg_pcix pcix; /* PCI-X */
190 /* additional type 1 device config header information (PCI to PCI bridge) */
192 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
193 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
194 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
195 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
198 pci_addr_t pmembase; /* base address of prefetchable memory */
199 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
200 uint32_t membase; /* base address of memory window */
201 uint32_t memlimit; /* topmost address of memory window */
202 uint32_t iobase; /* base address of port window */
203 uint32_t iolimit; /* topmost address of port window */
204 uint16_t secstat; /* secondary bus status register */
205 uint16_t bridgectl; /* bridge control register */
206 uint8_t seclat; /* CardBus latency timer */
209 /* additional type 2 device config header information (CardBus bridge) */
212 uint32_t membase0; /* base address of memory window */
213 uint32_t memlimit0; /* topmost address of memory window */
214 uint32_t membase1; /* base address of memory window */
215 uint32_t memlimit1; /* topmost address of memory window */
216 uint32_t iobase0; /* base address of port window */
217 uint32_t iolimit0; /* topmost address of port window */
218 uint32_t iobase1; /* base address of port window */
219 uint32_t iolimit1; /* topmost address of port window */
220 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
221 uint16_t secstat; /* secondary bus status register */
222 uint16_t bridgectl; /* bridge control register */
223 uint8_t seclat; /* CardBus latency timer */
226 extern uint32_t pci_numdevs;
228 /* Only if the prerequisites are present */
229 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
231 STAILQ_ENTRY(pci_devinfo) pci_links;
232 struct resource_list resources;
234 struct pci_conf conf;
242 enum pci_device_ivars {
267 * Simplified accessors for pci devices
269 #define PCI_ACCESSOR(var, ivar, type) \
270 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
272 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
273 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
274 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
275 PCI_ACCESSOR(device, DEVICE, uint16_t)
276 PCI_ACCESSOR(devid, DEVID, uint32_t)
277 PCI_ACCESSOR(class, CLASS, uint8_t)
278 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
279 PCI_ACCESSOR(progif, PROGIF, uint8_t)
280 PCI_ACCESSOR(revid, REVID, uint8_t)
281 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
282 PCI_ACCESSOR(irq, IRQ, uint8_t)
283 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
284 PCI_ACCESSOR(bus, BUS, uint8_t)
285 PCI_ACCESSOR(slot, SLOT, uint8_t)
286 PCI_ACCESSOR(function, FUNCTION, uint8_t)
287 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
288 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
289 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
290 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
291 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
292 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
297 * Operations on configuration space.
299 static __inline uint32_t
300 pci_read_config(device_t dev, int reg, int width)
302 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
306 pci_write_config(device_t dev, int reg, uint32_t val, int width)
308 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
312 * Ivars for pci bridges.
315 /*typedef enum pci_device_ivars pcib_device_ivars;*/
316 enum pcib_device_ivars {
321 #define PCIB_ACCESSOR(var, ivar, type) \
322 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
324 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
325 PCIB_ACCESSOR(bus, BUS, uint32_t)
330 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
331 * on i386 or other platforms should be mapped out in the MD pcireadconf
332 * code and not here, since the only MI invalid IRQ is 255.
334 #define PCI_INVALID_IRQ 255
335 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
338 * Convenience functions.
340 * These should be used in preference to manually manipulating
341 * configuration space.
344 pci_enable_busmaster(device_t dev)
346 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
350 pci_disable_busmaster(device_t dev)
352 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
356 pci_enable_io(device_t dev, int space)
358 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
362 pci_disable_io(device_t dev, int space)
364 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
368 pci_get_vpd_ident(device_t dev, const char **identptr)
370 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
374 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
376 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
380 * Check if the address range falls within the VGA defined address range(s)
383 pci_is_vga_ioport_range(u_long start, u_long end)
386 return (((start >= 0x3b0 && end <= 0x3bb) ||
387 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
391 pci_is_vga_memory_range(u_long start, u_long end)
394 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
398 * PCI power states are as defined by ACPI:
400 * D0 State in which device is on and running. It is receiving full
401 * power from the system and delivering full functionality to the user.
402 * D1 Class-specific low-power state in which device context may or may not
403 * be lost. Buses in D1 cannot do anything to the bus that would force
404 * devices on that bus to lose context.
405 * D2 Class-specific low-power state in which device context may or may
406 * not be lost. Attains greater power savings than D1. Buses in D2
407 * can cause devices on that bus to lose some context. Devices in D2
408 * must be prepared for the bus to be in D2 or higher.
409 * D3 State in which the device is off and not running. Device context is
410 * lost. Power can be removed from the device.
412 #define PCI_POWERSTATE_D0 0
413 #define PCI_POWERSTATE_D1 1
414 #define PCI_POWERSTATE_D2 2
415 #define PCI_POWERSTATE_D3 3
416 #define PCI_POWERSTATE_UNKNOWN -1
419 pci_set_powerstate(device_t dev, int state)
421 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
425 pci_get_powerstate(device_t dev)
427 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
431 pci_find_cap(device_t dev, int capability, int *capreg)
433 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
437 pci_find_extcap(device_t dev, int capability, int *capreg)
439 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
443 pci_find_htcap(device_t dev, int capability, int *capreg)
445 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
449 pci_alloc_msi(device_t dev, int *count)
451 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
455 pci_alloc_msix(device_t dev, int *count)
457 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
461 pci_remap_msix(device_t dev, int count, const u_int *vectors)
463 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
467 pci_release_msi(device_t dev)
469 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
473 pci_msi_count(device_t dev)
475 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
479 pci_msix_count(device_t dev)
481 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
484 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
485 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
486 device_t pci_find_device(uint16_t, uint16_t);
487 device_t pci_find_class(uint8_t class, uint8_t subclass);
489 /* Can be used by drivers to manage the MSI-X table. */
490 int pci_pending_msix(device_t dev, u_int index);
492 int pci_msi_device_blacklisted(device_t dev);
494 void pci_ht_map_msi(device_t dev, uint64_t addr);
496 int pci_get_max_read_req(device_t dev);
497 void pci_restore_state(device_t dev);
498 void pci_save_state(device_t dev);
499 int pci_set_max_read_req(device_t dev, int size);
501 #endif /* _SYS_BUS_H_ */
504 * cdev switch for control device, initialised in generic PCI code
506 extern struct cdevsw pcicdev;
509 * List of all PCI devices, generation count for the list.
511 STAILQ_HEAD(devlist, pci_devinfo);
513 extern struct devlist pci_devq;
514 extern uint32_t pci_generation;
516 struct pci_map *pci_find_bar(device_t dev, int reg);
517 int pci_bar_enabled(device_t dev, struct pci_map *pm);
519 #endif /* _PCIVAR_H_ */