2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
86 #define PCN_USEIOSPACE
88 #include <dev/pcn/if_pcnreg.h>
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
94 /* "device miibus" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
98 * Various supported device vendors/types and their names.
100 static const struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
106 static const struct pcn_chipid {
110 { Am79C971, "Am79C971" },
111 { Am79C972, "Am79C972" },
112 { Am79C973, "Am79C973" },
113 { Am79C978, "Am79C978" },
114 { Am79C975, "Am79C975" },
115 { Am79C976, "Am79C976" },
119 static const char *pcn_chipid_name(u_int32_t);
120 static u_int32_t pcn_chip_id(device_t);
121 static const struct pcn_type *pcn_match(u_int16_t, u_int16_t);
123 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
124 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
125 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
126 static void pcn_csr_write(struct pcn_softc *, int, int);
127 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
128 static void pcn_bcr_write(struct pcn_softc *, int, int);
130 static int pcn_probe(device_t);
131 static int pcn_attach(device_t);
132 static int pcn_detach(device_t);
134 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
135 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
136 static void pcn_rxeof(struct pcn_softc *);
137 static void pcn_txeof(struct pcn_softc *);
138 static void pcn_intr(void *);
139 static void pcn_tick(void *);
140 static void pcn_start(struct ifnet *);
141 static void pcn_start_locked(struct ifnet *);
142 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
143 static void pcn_init(void *);
144 static void pcn_init_locked(struct pcn_softc *);
145 static void pcn_stop(struct pcn_softc *);
146 static void pcn_watchdog(struct ifnet *);
147 static int pcn_shutdown(device_t);
148 static int pcn_ifmedia_upd(struct ifnet *);
149 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
151 static int pcn_miibus_readreg(device_t, int, int);
152 static int pcn_miibus_writereg(device_t, int, int, int);
153 static void pcn_miibus_statchg(device_t);
155 static void pcn_setfilt(struct ifnet *);
156 static void pcn_setmulti(struct pcn_softc *);
157 static void pcn_reset(struct pcn_softc *);
158 static int pcn_list_rx_init(struct pcn_softc *);
159 static int pcn_list_tx_init(struct pcn_softc *);
161 #ifdef PCN_USEIOSPACE
162 #define PCN_RES SYS_RES_IOPORT
163 #define PCN_RID PCN_PCI_LOIO
165 #define PCN_RES SYS_RES_MEMORY
166 #define PCN_RID PCN_PCI_LOMEM
169 static device_method_t pcn_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, pcn_probe),
172 DEVMETHOD(device_attach, pcn_attach),
173 DEVMETHOD(device_detach, pcn_detach),
174 DEVMETHOD(device_shutdown, pcn_shutdown),
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
188 static driver_t pcn_driver = {
191 sizeof(struct pcn_softc)
194 static devclass_t pcn_devclass;
196 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
197 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
199 #define PCN_CSR_SETBIT(sc, reg, x) \
200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
202 #define PCN_CSR_CLRBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
205 #define PCN_BCR_SETBIT(sc, reg, x) \
206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
208 #define PCN_BCR_CLRBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
212 pcn_csr_read(sc, reg)
213 struct pcn_softc *sc;
216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
217 return(CSR_READ_4(sc, PCN_IO32_RDP));
221 pcn_csr_read16(sc, reg)
222 struct pcn_softc *sc;
225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
226 return(CSR_READ_2(sc, PCN_IO16_RDP));
230 pcn_csr_write(sc, reg, val)
231 struct pcn_softc *sc;
235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
236 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
241 pcn_bcr_read(sc, reg)
242 struct pcn_softc *sc;
245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
246 return(CSR_READ_4(sc, PCN_IO32_BDP));
250 pcn_bcr_read16(sc, reg)
251 struct pcn_softc *sc;
254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
255 return(CSR_READ_2(sc, PCN_IO16_BDP));
259 pcn_bcr_write(sc, reg, val)
260 struct pcn_softc *sc;
264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
265 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
270 pcn_miibus_readreg(dev, phy, reg)
274 struct pcn_softc *sc;
277 sc = device_get_softc(dev);
280 * At least Am79C971 with DP83840A wedge when isolating the
281 * external PHY so we can't allow multiple external PHYs.
282 * There are cards that use Am79C971 with both the internal
283 * and an external PHY though.
284 * For internal PHYs it doesn't really matter whether we can
285 * isolate the remaining internal and the external ones in
286 * the PHY drivers as the internal PHYs have to be enabled
287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc.
288 * With Am79C97{3,5,8} we don't support switching beetween
289 * the internal and external PHYs, yet, so we can't allow
290 * multiple PHYs with these either.
291 * Am79C97{2,6} actually only support external PHYs (not
292 * connectable internal ones respond at the usual addresses,
293 * which don't hurt if we let them show up on the bus) and
294 * isolating them works.
296 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
297 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
298 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 &&
299 phy != sc->pcn_extphyaddr)
302 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
303 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
307 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
308 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
309 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1)
310 sc->pcn_extphyaddr = phy;
316 pcn_miibus_writereg(dev, phy, reg, data)
320 struct pcn_softc *sc;
322 sc = device_get_softc(dev);
324 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
325 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
331 pcn_miibus_statchg(dev)
334 struct pcn_softc *sc;
335 struct mii_data *mii;
337 sc = device_get_softc(dev);
338 mii = device_get_softc(sc->pcn_miibus);
340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
341 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
343 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
351 struct pcn_softc *sc;
354 struct ifmultiaddr *ifma;
356 u_int16_t hashes[4] = { 0, 0, 0, 0 };
360 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 for (i = 0; i < 4; i++)
364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
369 /* first, zot all the existing hash bits */
370 for (i = 0; i < 4; i++)
371 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
373 /* now program new ones */
375 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
376 if (ifma->ifma_addr->sa_family != AF_LINK)
378 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
379 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
380 hashes[h >> 4] |= 1 << (h & 0xF);
382 if_maddr_runlock(ifp);
384 for (i = 0; i < 4; i++)
385 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
394 struct pcn_softc *sc;
397 * Issue a reset by reading from the RESET register.
398 * Note that we don't know if the chip is operating in
399 * 16-bit or 32-bit mode at this point, so we attempt
400 * to reset the chip both ways. If one fails, the other
403 CSR_READ_2(sc, PCN_IO16_RESET);
404 CSR_READ_4(sc, PCN_IO32_RESET);
406 /* Wait a little while for the chip to get its brains in order. */
409 /* Select 32-bit (DWIO) mode */
410 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
412 /* Select software style 3. */
413 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
419 pcn_chipid_name(u_int32_t id)
421 const struct pcn_chipid *p;
433 pcn_chip_id(device_t dev)
435 struct pcn_softc *sc;
438 sc = device_get_softc(dev);
440 * Note: we can *NOT* put the chip into
441 * 32-bit mode yet. The le(4) driver will only
442 * work in 16-bit mode, and once the chip
443 * goes into 32-bit mode, the only way to
444 * get it out again is with a hardware reset.
445 * So if pcn_probe() is called before the
446 * le(4) driver's probe routine, the chip will
447 * be locked into 32-bit operation and the
448 * le(4) driver will be unable to attach to it.
449 * Note II: if the chip happens to already
450 * be in 32-bit mode, we still need to check
451 * the chip ID, but first we have to detect
452 * 32-bit mode using only 16-bit operations.
453 * The safest way to do this is to read the
454 * PCI subsystem ID from BCR23/24 and compare
455 * that with the value read from PCI config
458 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
460 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
462 * Note III: the test for 0x10001000 is a hack to
463 * pacify VMware, who's pseudo-PCnet interface is
464 * broken. Reading the subsystem register from PCI
465 * config space yields 0x00000000 while reading the
466 * same value from I/O space yields 0x10001000. It's
467 * not supposed to be that way.
469 if (chip_id == pci_read_config(dev,
470 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
471 /* We're in 16-bit mode. */
472 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
474 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
476 /* We're in 32-bit mode. */
477 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
479 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
485 static const struct pcn_type *
486 pcn_match(u_int16_t vid, u_int16_t did)
488 const struct pcn_type *t;
491 while (t->pcn_name != NULL) {
492 if ((vid == t->pcn_vid) && (did == t->pcn_did))
500 * Probe for an AMD chip. Check the PCI vendor and device
501 * IDs against our list and return a device name if we find a match.
507 const struct pcn_type *t;
508 struct pcn_softc *sc;
512 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
515 sc = device_get_softc(dev);
518 * Temporarily map the I/O space so we can read the chip ID register.
521 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
522 if (sc->pcn_res == NULL) {
523 device_printf(dev, "couldn't map ports/memory\n");
526 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
527 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
529 chip_id = pcn_chip_id(dev);
531 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
533 switch((chip_id >> 12) & PART_MASK) {
544 device_set_desc(dev, t->pcn_name);
545 return(BUS_PROBE_DEFAULT);
549 * Attach the interface. Allocate softc structures, do ifmedia
550 * setup and ethernet/BPF attach.
557 struct pcn_softc *sc;
558 struct mii_data *mii;
559 struct mii_softc *miisc;
563 sc = device_get_softc(dev);
565 /* Initialize our mutex. */
566 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
569 * Map control/status registers.
571 pci_enable_busmaster(dev);
573 /* Retrieve the chip ID */
574 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
575 device_printf(dev, "Chip ID %04x (%s)\n",
576 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
579 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
581 if (sc->pcn_res == NULL) {
582 device_printf(dev, "couldn't map ports/memory\n");
587 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
588 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
590 /* Allocate interrupt */
592 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
593 RF_SHAREABLE | RF_ACTIVE);
595 if (sc->pcn_irq == NULL) {
596 device_printf(dev, "couldn't map interrupt\n");
601 /* Reset the adapter. */
605 * Get station address from the EEPROM.
607 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
608 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
610 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
612 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
615 if (sc->pcn_ldata == NULL) {
616 device_printf(dev, "no memory for list buffers!\n");
620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
622 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
624 device_printf(dev, "can not if_alloc()\n");
629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
631 ifp->if_ioctl = pcn_ioctl;
632 ifp->if_start = pcn_start;
633 ifp->if_watchdog = pcn_watchdog;
634 ifp->if_init = pcn_init;
635 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
638 * Do MII setup. Note that loopback support isn't implemented.
639 * See the comment in pcn_miibus_readreg() for why we can't
640 * universally pass MIIF_NOISOLATE here.
642 sc->pcn_extphyaddr = -1;
643 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd,
644 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
647 device_printf(dev, "attaching PHYs failed\n");
651 * Record the media instances of internal PHYs, which map the
652 * built-in interfaces to the MII, so we can set the active
653 * PHY/port based on the currently selected media.
655 sc->pcn_inst_10bt = -1;
656 mii = device_get_softc(sc->pcn_miibus);
657 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
658 switch (miisc->mii_phy) {
660 sc->pcn_inst_10bt = miisc->mii_inst;
663 * XXX deal with the Am79C97{3,5} internal 100baseT
664 * and the Am79C978 internal HomePNA PHYs.
670 * Call MI attach routine.
672 ether_ifattach(ifp, (u_int8_t *) eaddr);
674 /* Hook interrupt last to avoid having to lock softc */
675 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
676 NULL, pcn_intr, sc, &sc->pcn_intrhand);
679 device_printf(dev, "couldn't set up irq\n");
692 * Shutdown hardware and free up resources. This can be called any
693 * time after the mutex has been initialized. It is called in both
694 * the error case in attach and the normal detach case so it needs
695 * to be careful about only freeing resources that have actually been
702 struct pcn_softc *sc;
705 sc = device_get_softc(dev);
708 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
710 /* These should only be active if attach succeeded */
711 if (device_is_attached(dev)) {
716 callout_drain(&sc->pcn_stat_callout);
720 device_delete_child(dev, sc->pcn_miibus);
721 bus_generic_detach(dev);
723 if (sc->pcn_intrhand)
724 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
726 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
728 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
734 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
738 mtx_destroy(&sc->pcn_mtx);
744 * Initialize the transmit descriptors.
748 struct pcn_softc *sc;
750 struct pcn_list_data *ld;
751 struct pcn_ring_data *cd;
757 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
758 cd->pcn_tx_chain[i] = NULL;
759 ld->pcn_tx_list[i].pcn_tbaddr = 0;
760 ld->pcn_tx_list[i].pcn_txctl = 0;
761 ld->pcn_tx_list[i].pcn_txstat = 0;
764 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
771 * Initialize the RX descriptors and allocate mbufs for them.
775 struct pcn_softc *sc;
777 struct pcn_ring_data *cd;
782 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
783 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
793 * Initialize an RX descriptor and attach an MBUF cluster.
796 pcn_newbuf(sc, idx, m)
797 struct pcn_softc *sc;
801 struct mbuf *m_new = NULL;
802 struct pcn_rx_desc *c;
804 c = &sc->pcn_ldata->pcn_rx_list[idx];
807 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
811 MCLGET(m_new, M_DONTWAIT);
812 if (!(m_new->m_flags & M_EXT)) {
816 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
819 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
820 m_new->m_data = m_new->m_ext.ext_buf;
823 m_adj(m_new, ETHER_ALIGN);
825 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
826 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
827 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
828 c->pcn_bufsz |= PCN_RXLEN_MBO;
829 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
835 * A frame has been uploaded: pass the resulting mbuf chain up to
836 * the higher level protocols.
840 struct pcn_softc *sc;
844 struct pcn_rx_desc *cur_rx;
850 i = sc->pcn_cdata.pcn_rx_prod;
852 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
853 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
854 m = sc->pcn_cdata.pcn_rx_chain[i];
855 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
858 * If an error occurs, update stats, clear the
859 * status word and leave the mbuf cluster in place:
860 * it should simply get re-used next time this descriptor
861 * comes up in the ring.
863 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
865 pcn_newbuf(sc, i, m);
866 PCN_INC(i, PCN_RX_LIST_CNT);
870 if (pcn_newbuf(sc, i, NULL)) {
871 /* Ran out of mbufs; recycle this one. */
872 pcn_newbuf(sc, i, m);
874 PCN_INC(i, PCN_RX_LIST_CNT);
878 PCN_INC(i, PCN_RX_LIST_CNT);
880 /* No errors; receive the packet. */
882 m->m_len = m->m_pkthdr.len =
883 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
884 m->m_pkthdr.rcvif = ifp;
887 (*ifp->if_input)(ifp, m);
891 sc->pcn_cdata.pcn_rx_prod = i;
897 * A frame was downloaded to the chip. It's safe for us to clean up
903 struct pcn_softc *sc;
905 struct pcn_tx_desc *cur_tx = NULL;
912 * Go through our tx list and free mbufs for those
913 * frames that have been transmitted.
915 idx = sc->pcn_cdata.pcn_tx_cons;
916 while (idx != sc->pcn_cdata.pcn_tx_prod) {
917 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
919 if (!PCN_OWN_TXDESC(cur_tx))
922 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
923 sc->pcn_cdata.pcn_tx_cnt--;
924 PCN_INC(idx, PCN_TX_LIST_CNT);
928 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
930 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
931 ifp->if_collisions++;
932 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
933 ifp->if_collisions++;
936 ifp->if_collisions +=
937 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
940 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
941 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
942 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
945 sc->pcn_cdata.pcn_tx_cnt--;
946 PCN_INC(idx, PCN_TX_LIST_CNT);
949 if (idx != sc->pcn_cdata.pcn_tx_cons) {
950 /* Some buffers have been freed. */
951 sc->pcn_cdata.pcn_tx_cons = idx;
952 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
954 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
963 struct pcn_softc *sc;
964 struct mii_data *mii;
971 mii = device_get_softc(sc->pcn_miibus);
975 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
978 /* link just came up, restart */
979 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
980 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
982 if (ifp->if_snd.ifq_head != NULL)
983 pcn_start_locked(ifp);
986 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
995 struct pcn_softc *sc;
1004 /* Suppress unwanted interrupts */
1005 if (!(ifp->if_flags & IFF_UP)) {
1011 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
1013 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
1014 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
1016 if (status & PCN_CSR_RINT)
1019 if (status & PCN_CSR_TINT)
1022 if (status & PCN_CSR_ERR) {
1023 pcn_init_locked(sc);
1028 if (ifp->if_snd.ifq_head != NULL)
1029 pcn_start_locked(ifp);
1036 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1037 * pointers to the fragment pointers.
1040 pcn_encap(sc, m_head, txidx)
1041 struct pcn_softc *sc;
1042 struct mbuf *m_head;
1045 struct pcn_tx_desc *f = NULL;
1047 int frag, cur, cnt = 0;
1050 * Start packing the mbufs in this chain into
1051 * the fragment pointers. Stop when we run out
1052 * of fragments or hit the end of the mbuf chain.
1055 cur = frag = *txidx;
1057 for (m = m_head; m != NULL; m = m->m_next) {
1061 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1063 f = &sc->pcn_ldata->pcn_tx_list[frag];
1064 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1065 f->pcn_txctl |= PCN_TXCTL_MBO;
1066 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1068 f->pcn_txctl |= PCN_TXCTL_STP;
1070 f->pcn_txctl |= PCN_TXCTL_OWN;
1072 PCN_INC(frag, PCN_TX_LIST_CNT);
1079 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1080 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1081 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1082 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1083 sc->pcn_cdata.pcn_tx_cnt += cnt;
1090 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1091 * to the mbuf data regions directly in the transmit lists. We also save a
1092 * copy of the pointers since the transmit list fragment pointers are
1093 * physical addresses.
1099 struct pcn_softc *sc;
1103 pcn_start_locked(ifp);
1108 pcn_start_locked(ifp)
1111 struct pcn_softc *sc;
1112 struct mbuf *m_head = NULL;
1117 PCN_LOCK_ASSERT(sc);
1122 idx = sc->pcn_cdata.pcn_tx_prod;
1124 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1127 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1128 IF_DEQUEUE(&ifp->if_snd, m_head);
1132 if (pcn_encap(sc, m_head, &idx)) {
1133 IF_PREPEND(&ifp->if_snd, m_head);
1134 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1139 * If there's a BPF listener, bounce a copy of this frame
1142 BPF_MTAP(ifp, m_head);
1147 sc->pcn_cdata.pcn_tx_prod = idx;
1148 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1151 * Set a timeout in case the chip goes out to lunch.
1162 struct pcn_softc *sc;
1166 /* If we want promiscuous mode, set the allframes bit. */
1167 if (ifp->if_flags & IFF_PROMISC) {
1168 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1170 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1173 /* Set the capture broadcast bit to capture broadcast frames. */
1174 if (ifp->if_flags & IFF_BROADCAST) {
1175 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1177 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1187 struct pcn_softc *sc = xsc;
1190 pcn_init_locked(sc);
1196 struct pcn_softc *sc;
1198 struct ifnet *ifp = sc->pcn_ifp;
1199 struct mii_data *mii = NULL;
1200 struct ifmedia_entry *ife;
1202 PCN_LOCK_ASSERT(sc);
1205 * Cancel pending I/O and free all RX/TX buffers.
1210 mii = device_get_softc(sc->pcn_miibus);
1211 ife = mii->mii_media.ifm_cur;
1213 /* Set MAC address */
1214 pcn_csr_write(sc, PCN_CSR_PAR0,
1215 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]);
1216 pcn_csr_write(sc, PCN_CSR_PAR1,
1217 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]);
1218 pcn_csr_write(sc, PCN_CSR_PAR2,
1219 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]);
1221 /* Init circular RX list. */
1222 if (pcn_list_rx_init(sc) == ENOBUFS) {
1223 if_printf(ifp, "initialization failed: no "
1224 "memory for rx buffers\n");
1230 * Init tx descriptors.
1232 pcn_list_tx_init(sc);
1234 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */
1235 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1238 * Set up the port based on the currently selected media.
1239 * For Am79C978 we've to unconditionally set PCN_PORT_MII and
1240 * set the PHY in PCN_BCR_PHYSEL instead.
1242 if (sc->pcn_type != Am79C978 &&
1243 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt)
1244 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET);
1246 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1248 /* Set up RX filter. */
1252 * Load the multicast filter.
1257 * Load the addresses of the RX and TX lists.
1259 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1260 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1261 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1262 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1263 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1264 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1265 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1266 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1268 /* Set the RX and TX ring sizes. */
1269 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1270 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1272 /* We're not using the initialization block. */
1273 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1275 /* Enable fast suspend mode. */
1276 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1279 * Enable burst read and write. Also set the no underflow
1280 * bit. This will avoid transmit underruns in certain
1281 * conditions while still providing decent performance.
1283 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1284 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1286 /* Enable graceful recovery from underflow. */
1287 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1289 /* Enable auto-padding of short TX frames. */
1290 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1292 /* Disable MII autoneg (we handle this ourselves). */
1293 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1295 if (sc->pcn_type == Am79C978)
1296 /* XXX support other PHYs? */
1297 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1298 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1300 /* Enable interrupts and start the controller running. */
1301 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1305 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1308 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1314 * Set media options.
1317 pcn_ifmedia_upd(ifp)
1320 struct pcn_softc *sc;
1327 * At least Am79C971 with DP83840A can wedge when switching
1328 * from the internal 10baseT PHY to the external PHY without
1329 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE
1330 * the PCnet chip has to be powered down or stopped anyway
1331 * and although documented otherwise it doesn't take effect
1332 * until the next initialization.
1337 pcn_init_locked(sc);
1338 if (ifp->if_snd.ifq_head != NULL)
1339 pcn_start_locked(ifp);
1347 * Report current media status.
1350 pcn_ifmedia_sts(ifp, ifmr)
1352 struct ifmediareq *ifmr;
1354 struct pcn_softc *sc;
1355 struct mii_data *mii;
1359 mii = device_get_softc(sc->pcn_miibus);
1362 ifmr->ifm_active = mii->mii_media_active;
1363 ifmr->ifm_status = mii->mii_media_status;
1370 pcn_ioctl(ifp, command, data)
1375 struct pcn_softc *sc = ifp->if_softc;
1376 struct ifreq *ifr = (struct ifreq *) data;
1377 struct mii_data *mii = NULL;
1383 if (ifp->if_flags & IFF_UP) {
1384 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1385 ifp->if_flags & IFF_PROMISC &&
1386 !(sc->pcn_if_flags & IFF_PROMISC)) {
1387 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1390 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1392 pcn_csr_write(sc, PCN_CSR_CSR,
1393 PCN_CSR_INTEN|PCN_CSR_START);
1394 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1395 !(ifp->if_flags & IFF_PROMISC) &&
1396 sc->pcn_if_flags & IFF_PROMISC) {
1397 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1400 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1402 pcn_csr_write(sc, PCN_CSR_CSR,
1403 PCN_CSR_INTEN|PCN_CSR_START);
1404 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1405 pcn_init_locked(sc);
1407 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1410 sc->pcn_if_flags = ifp->if_flags;
1423 mii = device_get_softc(sc->pcn_miibus);
1424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1427 error = ether_ioctl(ifp, command, data);
1438 struct pcn_softc *sc;
1445 if_printf(ifp, "watchdog timeout\n");
1449 pcn_init_locked(sc);
1451 if (ifp->if_snd.ifq_head != NULL)
1452 pcn_start_locked(ifp);
1460 * Stop the adapter and free any mbufs allocated to the
1464 pcn_stop(struct pcn_softc *sc)
1469 PCN_LOCK_ASSERT(sc);
1473 callout_stop(&sc->pcn_stat_callout);
1475 /* Turn off interrupts */
1476 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1478 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1482 * Free data in the RX lists.
1484 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1485 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1486 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1487 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1490 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1491 sizeof(sc->pcn_ldata->pcn_rx_list));
1494 * Free the TX list buffers.
1496 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1497 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1498 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1499 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1503 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1504 sizeof(sc->pcn_ldata->pcn_tx_list));
1506 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1512 * Stop all chip I/O so that the kernel's probe routines don't
1513 * get confused by errant DMAs when rebooting.
1516 pcn_shutdown(device_t dev)
1518 struct pcn_softc *sc;
1520 sc = device_get_softc(dev);