2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * DEC PDQ FDDI Controller; code for BSD derived operating systems
31 * This module supports the DEC DEFPA PCI FDDI Controller
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/socket.h>
39 #include <sys/module.h>
42 #include <machine/bus_memio.h>
43 #include <machine/bus_pio.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
49 #include <net/if_arp.h>
50 #include <net/if_media.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
56 #include <dev/pdq/pdq_freebsd.h>
57 #include <dev/pdq/pdqreg.h>
59 #define DEC_VENDORID 0x1011
60 #define DEFPA_CHIPID 0x000F
62 #define DEFPA_LATENCY 0x88
64 #define PCI_CFLT 0x0C /* Configuration Latency */
65 #define PCI_CBMA 0x10 /* Configuration Base Memory Address */
66 #define PCI_CBIO 0x14 /* Configuration Base I/O Address */
68 static int pdq_pci_probe (device_t);
69 static int pdq_pci_attach (device_t);
70 static int pdq_pci_detach (device_t);
71 static void pdq_pci_shutdown (device_t);
72 static void pdq_pci_ifintr (void *);
75 pdq_pci_ifintr(void *arg)
81 sc = device_get_softc(dev);
84 (void) pdq_interrupt(sc->sc_pdq);
91 * This is the PCI configuration support.
94 pdq_pci_probe(device_t dev)
96 if (pci_get_vendor(dev) == DEC_VENDORID &&
97 pci_get_device(dev) == DEFPA_CHIPID) {
98 device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
106 pdq_pci_attach(device_t dev)
113 sc = device_get_softc(dev);
114 ifp = &sc->arpcom.ac_if;
119 * Map control/status registers.
121 pci_enable_busmaster(dev);
122 pci_enable_io(dev, SYS_RES_IOPORT);
123 pci_enable_io(dev, SYS_RES_MEMORY);
124 command = pci_read_config(dev, PCIR_COMMAND, 4);
126 if (!(command & PCIM_CMD_PORTEN)) {
127 device_printf(dev, "Failed to enable PCI I/O ports.\n");
132 if (!(command & PCIM_CMD_MEMEN)) {
133 device_printf(dev, "Failed to enable PCI memory mapping.\n");
138 command = pci_read_config(dev, PCIR_LATTIMER, 1);
139 if (command < DEFPA_LATENCY) {
140 command = DEFPA_LATENCY;
141 pci_write_config(dev, PCIR_LATTIMER, command, 1);
144 sc->mem_rid = PCI_CBMA;
145 sc->mem_type = SYS_RES_MEMORY;
146 sc->mem = bus_alloc_resource(dev, sc->mem_type, &sc->mem_rid,
147 0, ~0, 1, RF_ACTIVE);
149 device_printf(dev, "Unable to allocate I/O space resource.\n");
153 sc->mem_bsh = rman_get_bushandle(sc->mem);
154 sc->mem_bst = rman_get_bustag(sc->mem);
157 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
158 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
160 device_printf(dev, "Unable to allocate interrupt resource.\n");
165 ifp->if_name = "fpa";
166 ifp->if_unit = device_get_unit(dev);
168 sc->sc_pdq = pdq_initialize(sc->mem_bst, sc->mem_bsh,
169 ifp->if_name, ifp->if_unit,
170 (void *)sc, PDQ_DEFPA);
171 if (sc->sc_pdq == NULL) {
172 device_printf(dev, "Initialization failed.\n");
177 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
178 pdq_pci_ifintr, dev, &sc->irq_ih);
180 device_printf(dev, "Failed to setup interrupt handler.\n");
185 bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes,
186 (caddr_t) sc->arpcom.ac_enaddr, FDDI_ADDR_LEN);
201 sc = device_get_softc(dev);
208 pdq_pci_shutdown(device_t dev)
212 sc = device_get_softc(dev);
213 pdq_hwreset(sc->sc_pdq);
218 static device_method_t pdq_pci_methods[] = {
219 /* Device interface */
220 DEVMETHOD(device_probe, pdq_pci_probe),
221 DEVMETHOD(device_attach, pdq_pci_attach),
222 DEVMETHOD(device_detach, pdq_pci_detach),
223 DEVMETHOD(device_shutdown, pdq_pci_shutdown),
228 static driver_t pdq_pci_driver = {
234 DRIVER_MODULE(if_fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
235 /* MODULE_DEPEND(if_fpa, pci, 1, 1, 1); */
236 MODULE_DEPEND(if_fpa, fddi, 1, 1, 1);