sys/dev/pdq/pdqreg.h

   1 /*      $NetBSD: pdqreg.h,v 1.14 2001/06/13 10:46:03 wiz Exp $  */
   2
   3 /*-
   4  * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. The name of the author may not be used to endorse or promote products
  13  *    derived from this software without specific prior written permission
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * Id: pdqreg.h,v 1.11 1997/03/21 21:16:04 thomas Exp
  27  * $FreeBSD$
  28  *
  29  */
  30
  31 /*
  32  * DEC PDQ FDDI Controller; PDQ port driver definitions
  33  *
  34  */
  35
  36 #ifndef _PDQREG_H
  37 #define _PDQREG_H
  38
  39 #if !defined(KERNEL) && !defined(_KERNEL)
  40 #include <stddef.h>
  41 #elif !defined(offsetof)
  42 #define offsetof(t, m)  ((char *) (&((t *)0L)->m) - (char *) 0L)
  43 #endif
  44 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
  45 #include <assert.h>
  46 #define PDQ_ASSERT      assert
  47 #else
  48 #define PDQ_ASSERT(x)   do { } while(0)
  49 #endif
  50
  51 #define PDQ_RING_SIZE(array)    ((sizeof(array) / sizeof(array[0])))
  52 #define PDQ_ARRAY_SIZE(array)   ((sizeof(array) / sizeof(array[0])))
  53 #define PDQ_RING_MASK(array)    (PDQ_RING_SIZE(array) - 1)
  54 #define PDQ_BITMASK(n)          (1L << (pdq_uint32_t) (n))
  55
  56 #define PDQ_FDDI_MAX            4495
  57 #define PDQ_FDDI_LLC_MIN        20
  58 #define PDQ_FDDI_SMT_MIN        37
  59
  60 #define PDQ_FDDI_SMT            0x40
  61 #define PDQ_FDDI_LLC_ASYNC      0x50
  62 #define PDQ_FDDI_LLC_SYNC       0xD0
  63 #define PDQ_FDDI_IMP_ASYNC      0x60
  64 #define PDQ_FDDI_IMP_SYNC       0xE0
  65
  66 #define PDQ_FDDIFC_C            0x80
  67 #define PDQ_FDDIFC_L            0x40
  68 #define PDQ_FDDIFC_F            0x30
  69 #define PDQ_FDDIFC_Z            0x0F
  70
  71 #define PDQ_FDDI_PH0            0x20
  72 #define PDQ_FDDI_PH1            0x38
  73 #define PDQ_FDDI_PH2            0x00
  74
  75 typedef pdq_uint32_t pdq_physaddr_t;
  76
  77 struct _pdq_lanaddr_t {
  78     pdq_uint8_t lanaddr_bytes[8];
  79 };
  80
  81 typedef struct {
  82     pdq_uint8_t fwrev_bytes[4];
  83 } pdq_fwrev_t;
  84
  85 enum _pdq_state_t {
  86     PDQS_RESET=0,
  87     PDQS_UPGRADE=1,
  88     PDQS_DMA_UNAVAILABLE=2,
  89     PDQS_DMA_AVAILABLE=3,
  90     PDQS_LINK_AVAILABLE=4,
  91     PDQS_LINK_UNAVAILABLE=5,
  92     PDQS_HALTED=6,
  93     PDQS_RING_MEMBER=7
  94 };
  95
  96 struct _pdq_csrs_t {
  97     pdq_bus_memoffset_t csr_port_reset;                 /* 0x00 [RW] */
  98     pdq_bus_memoffset_t csr_host_data;                  /* 0x04 [R]  */
  99     pdq_bus_memoffset_t csr_port_control;               /* 0x08 [RW] */
 100     pdq_bus_memoffset_t csr_port_data_a;                /* 0x0C [RW] */
 101     pdq_bus_memoffset_t csr_port_data_b;                /* 0x10 [RW] */
 102     pdq_bus_memoffset_t csr_port_status;                /* 0x14 [R]  */
 103     pdq_bus_memoffset_t csr_host_int_type_0;            /* 0x18 [RW] */
 104     pdq_bus_memoffset_t csr_host_int_enable;            /* 0x1C [RW] */
 105     pdq_bus_memoffset_t csr_type_2_producer;            /* 0x20 [RW] */
 106     pdq_bus_memoffset_t csr_cmd_response_producer;      /* 0x28 [RW] */
 107     pdq_bus_memoffset_t csr_cmd_request_producer;       /* 0x2C [RW] */
 108     pdq_bus_memoffset_t csr_host_smt_producer;          /* 0x30 [RW] */
 109     pdq_bus_memoffset_t csr_unsolicited_producer;       /* 0x34 [RW] */
 110     pdq_bus_t csr_bus;
 111     pdq_bus_memaddr_t csr_base;
 112 };
 113
 114 struct _pdq_pci_csrs_t {
 115     pdq_bus_memoffset_t csr_pfi_mode_control;           /* 0x40 [RW] */
 116     pdq_bus_memoffset_t csr_pfi_status;                 /* 0x44 [RW] */
 117     pdq_bus_memoffset_t csr_fifo_write;                 /* 0x48 [RW] */
 118     pdq_bus_memoffset_t csr_fifo_read;                  /* 0x4C [RW] */
 119     pdq_bus_t csr_bus;
 120     pdq_bus_memaddr_t csr_base;
 121 };
 122
 123 #define PDQ_PFI_MODE_DMA_ENABLE         0x01    /* DMA Enable */
 124 #define PDQ_PFI_MODE_PFI_PCI_INTR       0x02    /* PFI-to-PCI Int Enable */
 125 #define PDQ_PFI_MODE_PDQ_PCI_INTR       0x04    /* PDQ-to-PCI Int Enable */
 126
 127 #define PDQ_PFI_STATUS_PDQ_INTR         0x10    /* PDQ Int received */
 128 #define PDQ_PFI_STATUS_DMA_ABORT        0x08    /* PDQ DMA Abort asserted */
 129
 130 #define PDQ_TC_CSR_OFFSET                       0x00100000
 131 #define PDQ_TC_CSR_SPACE                        0x0040
 132 #define PDQ_FBUS_CSR_OFFSET                     0x00200000
 133 #define PDQ_FBUS_CSR_SPACE                      0x0080
 134
 135 /*
 136  * Port Reset Data A Definitions
 137  */
 138 #define PDQ_PRESET_SKIP_SELFTEST        0x0004
 139 #define PDQ_PRESET_SOFT_RESET           0x0002
 140 #define PDQ_PRESET_UPGRADE              0x0001
 141 /*
 142  * Port Control Register Definitions
 143  */
 144 #define PDQ_PCTL_CMD_ERROR              0x8000
 145 #define PDQ_PCTL_FLASH_BLAST            0x4000
 146 #define PDQ_PCTL_HALT                   0x2000
 147 #define PDQ_PCTL_COPY_DATA              0x1000
 148 #define PDQ_PCTL_ERROR_LOG_START        0x0800
 149 #define PDQ_PCTL_ERROR_LOG_READ         0x0400
 150 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE    0x0200
 151 #define PDQ_PCTL_DMA_INIT               0x0100
 152 #define PDQ_DMA_INIT_LW_BSWAP_DATA      0x02
 153 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL   0x01
 154 #define PDQ_PCTL_INIT_START             0x0080
 155 #define PDQ_PCTL_CONSUMER_BLOCK         0x0040
 156 #define PDQ_PCTL_DMA_UNINIT             0x0020
 157 #define PDQ_PCTL_RING_MEMBER            0x0010
 158 #define PDQ_PCTL_MLA_READ               0x0008
 159 #define PDQ_PCTL_FW_REV_READ            0x0004
 160 #define PDQ_PCTL_DEVICE_SPECIFIC        0x0002
 161 #define PDQ_PCTL_SUB_CMD                0x0001
 162
 163 typedef enum {
 164     PDQ_SUB_CMD_LINK_UNINIT=1,
 165     PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
 166     PDQ_SUB_CMD_PDQ_REV_GET=4
 167 } pdq_sub_cmd_t;
 168
 169 typedef enum {
 170     PDQ_DMA_BURST_4LW=0,
 171     PDQ_DMA_BURST_8LW=1,
 172     PDQ_DMA_BURST_16LW=2,
 173     PDQ_DMA_BURST_32LW=3
 174 } pdq_dma_burst_size_t;
 175
 176 typedef enum {
 177     PDQ_CHIP_REV_A_B_OR_C=0,
 178     PDQ_CHIP_REV_D=2,
 179     PDQ_CHIP_REV_E=4
 180 } pdq_chip_rev_t;
 181 /*
 182  * Port Status Register Definitions
 183  */
 184 #define PDQ_PSTS_RCV_DATA_PENDING       0x80000000ul
 185 #define PDQ_PSTS_XMT_DATA_PENDING       0x40000000ul
 186 #define PDQ_PSTS_HOST_SMT_PENDING       0x20000000ul
 187 #define PDQ_PSTS_UNSOL_PENDING          0x10000000ul
 188 #define PDQ_PSTS_CMD_RSP_PENDING        0x08000000ul
 189 #define PDQ_PSTS_CMD_REQ_PENDING        0x04000000ul
 190 #define PDQ_PSTS_TYPE_0_PENDING         0x02000000ul
 191 #define PDQ_PSTS_INTR_PENDING           0xFE000000ul
 192 #define PDQ_PSTS_ADAPTER_STATE(sts)     ((pdq_state_t) (((sts) >> 8) & 0x07))
 193 #define PDQ_PSTS_HALT_ID(sts)           ((pdq_halt_code_t) ((sts) & 0xFF))
 194 /*
 195  * Host Interrupt Register Definitions
 196  */
 197 #define PDQ_HOST_INT_TX_ENABLE                  0x80000000ul
 198 #define PDQ_HOST_INT_RX_ENABLE                  0x40000000ul
 199 #define PDQ_HOST_INT_UNSOL_ENABLE               0x20000000ul
 200 #define PDQ_HOST_INT_HOST_SMT_ENABLE            0x10000000ul
 201 #define PDQ_HOST_INT_CMD_RSP_ENABLE             0x08000000ul
 202 #define PDQ_HOST_INT_CMD_RQST_ENABLE            0x04000000ul
 203
 204 #define PDQ_HOST_INT_1MS                        0x80
 205 #define PDQ_HOST_INT_20MS                       0x40
 206 #define PDQ_HOST_INT_CSR_CMD_DONE               0x20
 207 #define PDQ_HOST_INT_STATE_CHANGE               0x10
 208 #define PDQ_HOST_INT_XMT_DATA_FLUSH             0x08
 209 #define PDQ_HOST_INT_NXM                        0x04
 210 #define PDQ_HOST_INT_PM_PARITY_ERROR            0x02
 211 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR      0x01
 212 #define PDQ_HOST_INT_FATAL_ERROR                0x07
 213
 214 typedef enum {
 215     PDQH_SELFTEST_TIMEOUT=0,
 216     PDQH_HOST_BUS_PARITY_ERROR=1,
 217     PDQH_HOST_DIRECTED_HALT=2,
 218     PDQH_SOFTWARE_FAULT=3,
 219     PDQH_HARDWARE_FAULT=4,
 220     PDQH_PC_TRACE_PATH_TEST=5,
 221     PDQH_DMA_ERROR=6,
 222     PDQH_IMAGE_CRC_ERROR=7,
 223     PDQH_ADAPTER_PROCESSOR_ERROR=8,
 224     PDQH_MAX=9
 225 } pdq_halt_code_t;
 226
 227 typedef struct {
 228     pdq_uint16_t pdqcb_receives;
 229     pdq_uint16_t pdqcb_transmits;
 230     pdq_uint32_t pdqcb__filler1;
 231     pdq_uint32_t pdqcb_host_smt;
 232     pdq_uint32_t pdqcb__filler2;
 233     pdq_uint32_t pdqcb_unsolicited_event;
 234     pdq_uint32_t pdqcb__filler3;
 235     pdq_uint32_t pdqcb_command_response;
 236     pdq_uint32_t pdqcb__filler4;
 237     pdq_uint32_t pdqcb_command_request;
 238     pdq_uint32_t pdqcb__filler5[7];
 239 } pdq_consumer_block_t;
 240
 241 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
 242 #define PDQ_BITFIELD2(a, b)                      b, a
 243 #define PDQ_BITFIELD3(a, b, c)                c, b, a
 244 #define PDQ_BITFIELD4(a, b, c, d)          d, c, b, a
 245 #define PDQ_BITFIELD5(a, b, c, d, e)    e, d, c, b, a
 246 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
 247                                         l, k, j, i, h, g, f, e, d, c, b, a
 248 #else
 249 #define PDQ_BITFIELD2(a, b)             a, b
 250 #define PDQ_BITFIELD3(a, b, c)          a, b, c
 251 #define PDQ_BITFIELD4(a, b, c, d)       a, b, c, d
 252 #define PDQ_BITFIELD5(a, b, c, d, e)    a, b, c, d, e
 253 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
 254                                         a, b, c, d, e, f, g, h, i, j, k, l
 255 #endif
 256
 257 typedef struct {
 258     pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
 259                                rxd_seg_cnt : 4,
 260                                rxd_seg_len_hi : 9,
 261                                rxd_seg_len_lo : 2,
 262                                rxd_sop : 1);
 263     pdq_uint32_t rxd_pa_lo;
 264 } pdq_rxdesc_t;
 265
 266 typedef union {
 267     pdq_uint32_t rxs_status;
 268     struct {
 269         pdq_uint32_t PDQ_BITFIELD12(st_len : 13,
 270                                     st_rcc_ss : 2,
 271                                     st_rcc_dd : 2,
 272                                     st_rcc_reason : 3,
 273                                     st_rcc_badcrc : 1,
 274                                     st_rcc_badpdu : 1,
 275                                     st_fsb__reserved : 2,
 276                                     st_fsb_c : 1,
 277                                     st_fsb_a : 1,
 278                                     st_fsb_e : 1,
 279                                     st_fsc : 3,
 280                                     st__reserved : 2);
 281     } rxs_st;
 282 } pdq_rxstatus_t;
 283 #define rxs_len                 rxs_st.st_len
 284 #define rxs_rcc_ss              rxs_st.st_rcc_ss
 285 #define rxs_rcc_dd              rxs_st.st_rcc_dd
 286 #define rxs_rcc_reason          rxs_st.st_rcc_reason
 287 #define rxs_rcc_badcrc          rxs_st.st_rcc_badcrc
 288 #define rxs_rcc_badpdu          rxs_st.st_rcc_badpdu
 289 #define rxs_fsb_c               rxs_st.st_fsb_c
 290 #define rxs_fsb_a               rxs_st.st_fsb_a
 291 #define rxs_fsb_e               rxs_st.st_fsb_e
 292 #define rxs_fsc                 rxs_st.st_fsc
 293
 294 #define PDQ_RXS_RCC_DD_NO_MATCH         0x00
 295 #define PDQ_RXS_RCC_DD_PROMISC_MATCH    0x01
 296 #define PDQ_RXS_RCC_DD_CAM_MATCH        0x02
 297 #define PDQ_RXS_RCC_DD_MLA_MATCH        0x03
 298
 299 typedef struct {
 300     pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
 301                                txd_seg_len : 13,
 302                                txd_mbz : 1,
 303                                txd_eop : 1,
 304                                txd_sop : 1);
 305     pdq_uint32_t txd_pa_lo;
 306 } pdq_txdesc_t;
 307
 308 typedef struct {
 309     pdq_rxdesc_t pdqdb_receives[256];           /* 2048;        0x0000..0x07FF */
 310     pdq_txdesc_t pdqdb_transmits[256];          /* 2048;        0x0800..0x0FFF */
 311     pdq_rxdesc_t pdqdb_host_smt[64];            /*  512;        0x1000..0x11FF */
 312     pdq_rxdesc_t pdqdb_unsolicited_events[16];  /*  128;        0x1200..0x127F */
 313     pdq_rxdesc_t pdqdb_command_responses[16];   /*  128;        0x1280..0x12FF */
 314     pdq_txdesc_t pdqdb_command_requests[16];    /*  128;        0x1300..0x137F */
 315     /*
 316      * The rest of the descriptor block is unused.
 317      * As such we could use it for other things.
 318      */
 319     pdq_uint32_t pdqdb__filler1[16];            /*   64;        0x1380..0x13BF */
 320     pdq_consumer_block_t pdqdb_consumer;        /*   64;        0x13C0..0x13FF */
 321     /*
 322      * The maximum command size is 512 so as long as thes
 323      * command is at least that long all will be fine.
 324      */
 325     pdq_uint32_t pdqdb__filler2[64];            /*  256;        0x1400..0x14FF */
 326     pdq_uint8_t pdqdb_cmd_request_buf[1024];    /* 1024;        0x1500..0x18FF */
 327     pdq_uint8_t pdqdb_cmd_response_buf[1024];   /* 1024;        0x1900..0x1CFF */
 328     pdq_uint32_t pdqdb__filler3[128];           /*  512;        0x1D00..0x1EFF */
 329     pdq_uint8_t pdqdb_tx_hdr[4];                /*    4;        0x1F00..0x1F03 */
 330     pdq_uint32_t pdqdb__filler4[63];            /*  252;        0x1F04..0x1FFF */
 331 } pdq_descriptor_block_t;
 332
 333 #define PDQ_SIZE_COMMAND_RESPONSE       512
 334
 335 typedef enum {
 336     PDQC_START=0,
 337     PDQC_FILTER_SET=1,
 338     PDQC_FILTER_GET=2,
 339     PDQC_CHARS_SET=3,
 340     PDQC_STATUS_CHARS_GET=4,
 341     PDQC_COUNTERS_GET=5,
 342     PDQC_COUNTERS_SET=6,
 343     PDQC_ADDR_FILTER_SET=7,
 344     PDQC_ADDR_FILTER_GET=8,
 345     PDQC_ERROR_LOG_CLEAR=9,
 346     PDQC_ERROR_LOG_GET=10,
 347     PDQC_FDDI_MIB_GET=11,
 348     PDQC_DEC_EXT_MIB_GET=12,
 349     PDQC_DEV_SPECIFIC_GET=13,
 350     PDQC_SNMP_SET=14,
 351     PDQC_SMT_MIB_GET=16,
 352     PDQC_SMT_MIB_SET=17,
 353     PDQC_BOGUS_CMD=18
 354 } pdq_cmd_code_t;
 355
 356 typedef struct {
 357     /*
 358      * These value manage the available space in command/response
 359      * buffer area.
 360      */
 361     pdq_physaddr_t ci_pa_request_bufstart;
 362     pdq_uint8_t *ci_request_bufstart;
 363     pdq_physaddr_t ci_pa_response_bufstart;
 364     pdq_uint8_t *ci_response_bufstart;
 365     /*
 366      * Bitmask of commands to sent to the PDQ
 367      */
 368     pdq_uint32_t ci_pending_commands;
 369     /*
 370      * Variables to maintain the PDQ queues.
 371      */
 372     pdq_uint32_t ci_command_active;
 373     pdq_uint32_t ci_request_producer;
 374     pdq_uint32_t ci_response_producer;
 375     pdq_uint32_t ci_request_completion;
 376     pdq_uint32_t ci_response_completion;
 377     /*
 378      *
 379      */
 380     pdq_physaddr_t ci_pa_request_descriptors;
 381     pdq_physaddr_t ci_pa_response_descriptors;
 382
 383     pdq_cmd_code_t ci_queued_commands[16];
 384 } pdq_command_info_t;
 385
 386 #define PDQ_SIZE_UNSOLICITED_EVENT      512
 387 #define PDQ_NUM_UNSOLICITED_EVENTS      (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
 388
 389 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
 390
 391 typedef struct {
 392     pdq_physaddr_t ui_pa_bufstart;
 393     pdq_physaddr_t ui_pa_descriptors;
 394     pdq_unsolicited_event_t *ui_events;
 395
 396     pdq_uint32_t ui_free;
 397     pdq_uint32_t ui_producer;
 398     pdq_uint32_t ui_completion;
 399 } pdq_unsolicited_info_t;
 400
 401 #define PDQ_RX_FC_OFFSET        (sizeof(pdq_rxstatus_t) + 3)
 402 #define PDQ_RX_SEGCNT           ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
 403 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
 404     PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
 405           ((pdq)->pdq_rx_info.rx_producer << 0) \
 406         | ((pdq)->pdq_tx_info.tx_producer << 8) \
 407         | ((pdq)->pdq_rx_info.rx_completion << 16) \
 408         | ((pdq)->pdq_tx_info.tx_completion << 24))
 409
 410 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
 411     PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
 412           ((pdq)->pdq_host_smt_info.rx_producer   << 0) \
 413         | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
 414
 415 #define PDQ_ADVANCE(n, a, m)    ((n) = ((n) + (a)) & (m))
 416
 417 typedef struct {
 418     void *q_head;
 419     void *q_tail;
 420 } pdq_databuf_queue_t;
 421
 422 typedef struct {
 423     void *rx_buffers;
 424     pdq_physaddr_t rx_pa_descriptors;
 425
 426     pdq_uint32_t rx_target;
 427     pdq_uint32_t rx_free;
 428     pdq_uint32_t rx_producer;
 429     pdq_uint32_t rx_completion;
 430 } pdq_rx_info_t;
 431
 432 typedef struct {
 433     pdq_databuf_queue_t tx_txq;
 434     pdq_txdesc_t tx_hdrdesc;
 435     pdq_uint8_t tx_descriptor_count[256];
 436     pdq_physaddr_t tx_pa_descriptors;
 437
 438     pdq_uint32_t tx_free;
 439     pdq_uint32_t tx_producer;
 440     pdq_uint32_t tx_completion;
 441 } pdq_tx_info_t;
 442
 443 typedef struct _pdq_os_ctx_t pdq_os_ctx_t;
 444 struct _pdq_t {
 445     pdq_csrs_t pdq_csrs;
 446     pdq_pci_csrs_t pdq_pci_csrs;
 447     pdq_type_t pdq_type;
 448     pdq_chip_rev_t pdq_chip_rev;
 449     pdq_lanaddr_t pdq_hwaddr;
 450     pdq_fwrev_t pdq_fwrev;
 451     pdq_descriptor_block_t *pdq_dbp;
 452     volatile pdq_consumer_block_t *pdq_cbp;
 453     pdq_uint32_t pdq_intrmask;
 454     pdq_uint32_t pdq_flags;
 455 #define PDQ_PROMISC     0x0001
 456 #define PDQ_ALLMULTI    0x0002
 457 #define PDQ_PASS_SMT    0x0004
 458 #define PDQ_RUNNING     0x0008
 459 #define PDQ_PRINTCHARS  0x0010
 460 #define PDQ_TXOK        0x0020
 461 #define PDQ_WANT_FDX    0x0040
 462 #define PDQ_IS_FDX      0x0080
 463 #define PDQ_IS_ONRING   0x0100
 464     const char *pdq_os_name;
 465     pdq_os_ctx_t *pdq_os_ctx;
 466     pdq_uint32_t pdq_unit;
 467     pdq_command_info_t pdq_command_info;
 468     pdq_unsolicited_info_t pdq_unsolicited_info;
 469     pdq_tx_info_t pdq_tx_info;
 470     pdq_rx_info_t pdq_rx_info;
 471     pdq_rx_info_t pdq_host_smt_info;
 472     void *pdq_receive_buffers[256];
 473     void *pdq_host_smt_buffers[64];
 474     pdq_physaddr_t pdq_pa_consumer_block;
 475     pdq_physaddr_t pdq_pa_descriptor_block;
 476 };
 477
 478 #define PDQ_DB_BUSPA(pdq, m) \
 479         ((pdq)->pdq_pa_descriptor_block + \
 480                 ((volatile u_int8_t *) (m) - (u_int8_t *) (pdq)->pdq_dbp))
 481
 482
 483 typedef enum {
 484     PDQR_SUCCESS=0,
 485     PDQR_FAILURE=1,
 486     PDQR_WARNING=2,
 487     PDQR_LOOP_MODE_BAD=3,
 488     PDQR_ITEM_CODE_BAD=4,
 489     PDQR_TVX_BAD=5,
 490     PDQR_TREQ_BAD=6,
 491     PDQR_RESTRICTED_TOKEN_BAD=7,
 492     PDQR_NO_EOL=12,
 493     PDQR_FILTER_STATE_BAD=13,
 494     PDQR_CMD_TYPE_BAD=14,
 495     PDQR_ADAPTER_STATE_BAD=15,
 496     PDQR_RING_PURGER_BAD=16,
 497     PDQR_LEM_THRESHOLD_BAD=17,
 498     PDQR_LOOP_NOT_SUPPORTED=18,
 499     PDQR_FLUSH_TIME_BAD=19,
 500     PDQR_NOT_YET_IMPLEMENTED=20,
 501     PDQR_CONFIG_POLICY_BAD=21,
 502     PDQR_STATION_ACTION_BAD=22,
 503     PDQR_MAC_ACTION_BAD=23,
 504     PDQR_CON_POLICIES_BAD=24,
 505     PDQR_MAC_LOOP_TIME_BAD=25,
 506     PDQR_TB_MAX_BAD=26,
 507     PDQR_LER_CUTOFF_BAD=27,
 508     PDQR_LER_ALARM_BAD=28,
 509     PDQR_MAC_PATHS_REQ_BAD=29,
 510     PDQR_MAC_T_REQ_BAD=30,
 511     PDQR_EMAC_RING_PURGER_BAD=31,
 512     PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
 513     PDQR_NO_SUCH_ENTRY=33,
 514     PDQR_T_NOTIFY_BAD=34,
 515     PDQR_TR_MAX_EXP_BAD=35,
 516     PDQR_FRAME_ERR_THRESHOLD_BAD=36,
 517     PDQR_MAX_TREQ_BAD=37,
 518     PDQR_FULL_DUPLEX_ENABLE_BAD=38,
 519     PDQR_ITEM_INDEX_BAD=39
 520 } pdq_response_code_t;
 521
 522 typedef enum {
 523     PDQI_EOL=0,
 524     PDQI_T_REQ=1,
 525     PDQI_TVX=2,
 526     PDQI_RESTRICTED_TOKEN=3,
 527     PDQI_LEM_THRESHOLD=4,
 528     PDQI_RING_PURGER=5,
 529     PDQI_COUNTER_INTERVAL=6,
 530     PDQI_IND_GROUP_PROM=7,
 531     PDQI_GROUP_PROM=8,
 532     PDQI_BROADCAST=9,
 533     PDQI_SMT_PROM=10,
 534     PDQI_SMT_USER=11,
 535     PDQI_RESERVED=12,
 536     PDQI_IMPLEMENTOR=13,
 537     PDQI_LOOPBACK_MODE=14,
 538     PDQI_SMT_CONFIG_POLICY=16,
 539     PDQI_SMT_CONNECTION_POLICY=17,
 540     PDQI_SMT_T_NOTIFY=18,
 541     PDQI_SMT_STATION_ACTION=19,
 542     PDQI_MAC_PATHS_REQUESTED=21,
 543     PDQI_MAC_ACTION=23,
 544     PDQI_PORT_CONNECTION_POLICIES=24,
 545     PDQI_PORT_PATHS_REQUESTED=25,
 546     PDQI_PORT_MAC_LOOP_TIME=26,
 547     PDQI_PORT_TB_MAX=27,
 548     PDQI_PORT_LER_CUTOFF=28,
 549     PDQI_PORT_LER_ALARM=29,
 550     PDQI_PORT_ACTION=30,
 551     PDQI_FLUSH_TIME=32,
 552     PDQI_SMT_USER_DATA=33,
 553     PDQI_SMT_STATUS_REPORT_POLICY=34,
 554     PDQI_SMT_TRACE_MAX_EXPIRATION=35,
 555     PDQI_MAC_FRAME_ERR_THRESHOLD=36,
 556     PDQI_MAC_UNIT_DATA_ENABLE=37,
 557     PDQI_PATH_TVX_LOWER_BOUND=38,
 558     PDQI_PATH_TMAX_LOWER_BOUND=39,
 559     PDQI_PATH_MAX_TREQ=40,
 560     PDQI_MAC_TREQ=41,
 561     PDQI_EMAC_RING_PURGER=42,
 562     PDQI_EMAC_RTOKEN_TIMEOUT=43,
 563     PDQI_FULL_DUPLEX_ENABLE=44
 564 } pdq_item_code_t;
 565
 566 typedef enum {
 567     PDQSNMP_EOL=0,
 568     PDQSNMP_FULL_DUPLEX_ENABLE=0x2F11
 569 } pdq_snmp_item_code_t;
 570
 571 enum _pdq_boolean_t {
 572     PDQ_FALSE=0,
 573     PDQ_TRUE=1
 574 };
 575
 576 typedef enum {
 577     PDQ_FILTER_BLOCK=0,
 578     PDQ_FILTER_PASS=1
 579 } pdq_filter_state_t;
 580
 581 typedef enum {
 582     PDQ_STATION_TYPE_SAS=0,
 583     PDQ_STATION_TYPE_DAC=1,
 584     PDQ_STATION_TYPE_SAC=2,
 585     PDQ_STATION_TYPE_NAC=3,
 586     PDQ_STATION_TYPE_DAS=4
 587 } pdq_station_type_t;
 588
 589 typedef enum {
 590     PDQ_STATION_STATE_OFF=0,
 591     PDQ_STATION_STATE_ON=1,
 592     PDQ_STATION_STATE_LOOPBACK=2
 593 } pdq_station_state_t;
 594
 595 typedef enum {
 596     PDQ_LINK_STATE_OFF_READY=1,
 597     PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
 598     PDQ_LINK_STATE_ON_RING_INIT=3,
 599     PDQ_LINK_STATE_ON_RING_RUN=4,
 600     PDQ_LINK_STATE_BROKEN=5
 601 } pdq_link_state_t;
 602
 603 typedef enum {
 604     PDQ_DA_TEST_STATE_UNKNOWN=0,
 605     PDQ_DA_TEST_STATE_SUCCESS=1,
 606     PDQ_DA_TEST_STATE_DUPLICATE=2
 607 } pdq_da_test_state_t;
 608
 609 typedef enum {
 610     PDQ_RING_PURGER_STATE_OFF=0,
 611     PDQ_RING_PURGER_STATE_CANDIDATE=1,
 612     PDQ_RING_PURGER_STATE_NON_PURGER=2,
 613     PDQ_RING_PURGER_STATE_PURGER=3
 614 } pdq_ring_purger_state_t;
 615
 616 typedef enum {
 617     PDQ_FRAME_STRING_MODE_SA_MATCH=0,
 618     PDQ_FRAME_STRING_MODE_FCI_STRIP=1
 619 } pdq_frame_strip_mode_t;
 620
 621 typedef enum {
 622     PDQ_RING_ERROR_REASON_NO_ERROR=0,
 623     PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
 624     PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
 625     PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
 626     PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
 627     PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
 628     PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
 629     PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
 630     PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
 631     PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
 632     PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
 633     PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
 634 } pdq_ring_error_reason_t;
 635
 636 typedef enum {
 637     PDQ_STATION_MODE_NORMAL=0,
 638     PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
 639 } pdq_station_mode_t;
 640
 641 typedef enum {
 642     PDQ_PHY_TYPE_A=0,
 643     PDQ_PHY_TYPE_B=1,
 644     PDQ_PHY_TYPE_S=2,
 645     PDQ_PHY_TYPE_M=3,
 646     PDQ_PHY_TYPE_UNKNOWN=4
 647 } pdq_phy_type_t;
 648
 649 typedef enum {
 650     PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
 651     PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
 652     PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
 653     PDQ_PMD_TYPE_ANSI_SONET=3,
 654     PDQ_PMD_TYPE_LOW_POWER=100,
 655     PDQ_PMD_TYPE_THINWIRE=101,
 656     PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
 657     PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
 658 } pdq_pmd_type_t;
 659
 660 typedef enum {
 661     PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
 662     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
 663     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
 664     PDQ_PMD_CLASS_SONET=3,
 665     PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
 666     PDQ_PMD_CLASS_TWISTED_PAIR=5,
 667     PDQ_PMD_CLASS_UNKNOWN=6,
 668     PDQ_PMD_CLASS_UNSPECIFIED=7
 669 } pdq_pmd_class_t;
 670
 671 typedef enum {
 672     PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
 673     PDQ_PHY_STATE_BROKEN=1,
 674     PDQ_PHY_STATE_OFF_READY=2,
 675     PDQ_PHY_STATE_WAITING=3,
 676     PDQ_PHY_STATE_STARTING=4,
 677     PDQ_PHY_STATE_FAILED=5,
 678     PDQ_PHY_STATE_WATCH=6,
 679     PDQ_PHY_STATE_INUSE=7
 680 } pdq_phy_state_t;
 681
 682 typedef enum {
 683     PDQ_REJECT_REASON_NONE=0,
 684     PDQ_REJECT_REASON_LOCAL_LCT=1,
 685     PDQ_REJECT_REASON_REMOTE_LCT=2,
 686     PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
 687     PDQ_REJECT_REASON_LEM_REJECT=4,
 688     PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
 689     PDQ_REJECT_REASON_NOISE_REJECT=6,
 690     PDQ_REJECT_REASON_REMOTE_REJECT=7,
 691     PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
 692     PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
 693     PDQ_REJECT_REASON_STANDBY=10,
 694     PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
 695 } pdq_reject_reason_t;
 696
 697 typedef enum {
 698     PDQ_BROKEN_REASON_NONE=0
 699 } pdq_broken_reason_t;
 700
 701 typedef enum {
 702     PDQ_RI_REASON_TVX_EXPIRED=0,
 703     PDQ_RI_REASON_TRT_EXPIRED=1,
 704     PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
 705     PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
 706     PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
 707 } pdq_ri_reason_t;
 708
 709 typedef enum {
 710     PDQ_LCT_DIRECTION_LOCAL_LCT=0,
 711     PDQ_LCT_DIRECTION_REMOTE_LCT=1,
 712     PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
 713 } pdq_lct_direction_t;
 714
 715 typedef enum {
 716     PDQ_PORT_A=0,
 717     PDQ_PORT_B=1
 718 } pdq_port_type_t;
 719
 720 typedef struct {
 721     pdq_uint8_t station_id_bytes[8];
 722 } pdq_station_id_t;
 723
 724 typedef pdq_uint32_t pdq_fdditimer_t;
 725 /*
 726  * Command format for Start, Filter_Get, ... commands
 727  */
 728 typedef struct {
 729     pdq_cmd_code_t generic_op;
 730 } pdq_cmd_generic_t;
 731
 732 /*
 733  * Response format for Start, Filter_Set, ... commands
 734  */
 735 typedef struct {
 736     pdq_uint32_t generic_reserved;
 737     pdq_cmd_code_t generic_op;
 738     pdq_response_code_t generic_status;
 739 } pdq_response_generic_t;
 740
 741 /*
 742  * Command format for Filter_Set command
 743  */
 744 typedef struct {
 745     pdq_cmd_code_t filter_set_op;
 746     struct {
 747         pdq_item_code_t item_code;
 748         pdq_filter_state_t filter_state;
 749     } filter_set_items[7];
 750     pdq_item_code_t filter_set_eol_item_code;
 751 } pdq_cmd_filter_set_t;
 752
 753 /*
 754  * Response format for Filter_Get command.
 755  */
 756 typedef struct {
 757     pdq_uint32_t filter_get_reserved;
 758     pdq_cmd_code_t filter_get_op;
 759     pdq_response_code_t filter_get_status;
 760     pdq_filter_state_t filter_get_ind_group_prom;
 761     pdq_filter_state_t filter_get_group_prom;
 762     pdq_filter_state_t filter_get_broadcast_all;
 763     pdq_filter_state_t filter_get_smt_prom;
 764     pdq_filter_state_t filter_get_smt_user;
 765     pdq_filter_state_t filter_get_reserved_all;
 766     pdq_filter_state_t filter_get_implementor_all;
 767 } pdq_response_filter_get_t;
 768
 769 #define PDQ_SIZE_RESPONSE_FILTER_GET    0x28
 770
 771 typedef struct {
 772     pdq_cmd_code_t chars_set_op;
 773     struct {
 774         pdq_item_code_t item_code;
 775         pdq_uint32_t item_value;
 776         pdq_port_type_t item_port;
 777     } chars_set_items[1];
 778     pdq_item_code_t chars_set_eol_item_code;
 779 } pdq_cmd_chars_set_t;
 780
 781 typedef struct {
 782     pdq_cmd_code_t addr_filter_set_op;
 783     pdq_lanaddr_t addr_filter_set_addresses[62];
 784 } pdq_cmd_addr_filter_set_t;
 785
 786 #define PDQ_SIZE_CMD_ADDR_FILTER_SET    0x1F4
 787
 788 typedef struct {
 789     pdq_uint32_t addr_filter_get_reserved;
 790     pdq_cmd_code_t addr_filter_get_op;
 791     pdq_response_code_t addr_filter_get_status;
 792     pdq_lanaddr_t addr_filter_get_addresses[62];
 793 } pdq_response_addr_filter_get_t;
 794
 795 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET       0x1FC
 796
 797 typedef struct {
 798     pdq_uint32_t status_chars_get_reserved;
 799     pdq_cmd_code_t status_chars_get_op;
 800     pdq_response_code_t status_chars_get_status;
 801     struct {
 802         /* Station Characteristic Attributes */
 803         pdq_station_id_t station_id;
 804         pdq_station_type_t station_type;
 805         pdq_uint32_t smt_version_id;
 806         pdq_uint32_t smt_max_version_id;
 807         pdq_uint32_t smt_min_version_id;
 808         /* Station Status Attributes */
 809         pdq_station_state_t station_state;
 810         /* Link Characteristic Attributes */
 811         pdq_lanaddr_t link_address;
 812         pdq_fdditimer_t t_req;
 813         pdq_fdditimer_t tvx;
 814         pdq_fdditimer_t restricted_token_timeout;
 815         pdq_boolean_t ring_purger_enable;
 816         pdq_link_state_t link_state;
 817         pdq_fdditimer_t negotiated_trt;
 818         pdq_da_test_state_t dup_addr_flag;
 819         /* Link Status Attributes */
 820         pdq_lanaddr_t upstream_neighbor;
 821         pdq_lanaddr_t old_upstream_neighbor;
 822         pdq_boolean_t upstream_neighbor_dup_addr_flag;
 823         pdq_lanaddr_t downstream_neighbor;
 824         pdq_lanaddr_t old_downstream_neighbor;
 825         pdq_ring_purger_state_t ring_purger_state;
 826         pdq_frame_strip_mode_t frame_strip_mode;
 827         pdq_ring_error_reason_t ring_error_reason;
 828         pdq_boolean_t loopback;
 829         pdq_fdditimer_t ring_latency;
 830         pdq_lanaddr_t last_dir_beacon_sa;
 831         pdq_lanaddr_t last_dir_beacon_una;
 832         /* Phy Characteristic Attributes */
 833         pdq_phy_type_t phy_type[2];
 834         pdq_pmd_type_t pmd_type[2];
 835         pdq_uint32_t lem_threshold[2];
 836         /* Phy Status Attributes */
 837         pdq_phy_state_t phy_state[2];
 838         pdq_phy_type_t neighbor_phy_type[2];
 839         pdq_uint32_t link_error_estimate[2];
 840         pdq_broken_reason_t broken_reason[2];
 841         pdq_reject_reason_t reject_reason[2];
 842         /* Miscellaneous */
 843         pdq_uint32_t counter_interval;
 844         pdq_fwrev_t module_rev;
 845         pdq_fwrev_t firmware_rev;
 846         pdq_uint32_t mop_device_type;
 847         pdq_uint32_t fddi_led[2];
 848         pdq_uint32_t flush;
 849     } status_chars_get;
 850 } pdq_response_status_chars_get_t;
 851
 852 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET      0xF0
 853
 854 typedef struct {
 855     pdq_uint32_t fddi_mib_get_reserved;
 856     pdq_cmd_code_t fddi_mib_get_op;
 857     pdq_response_code_t fddi_mib_get_status;
 858     struct {
 859         /* SMT Objects */
 860         pdq_station_id_t smt_station_id;
 861         pdq_uint32_t smt_op_version_id;
 862         pdq_uint32_t smt_hi_version_id;
 863         pdq_uint32_t smt_lo_version_id;
 864         pdq_uint32_t smt_mac_ct;
 865         pdq_uint32_t smt_non_master_ct;
 866         pdq_uint32_t smt_master_ct;
 867         pdq_uint32_t smt_paths_available;
 868         pdq_uint32_t smt_config_capabilities;
 869         pdq_uint32_t smt_config_policy;
 870         pdq_uint32_t smt_connection_policy;
 871         pdq_uint32_t smt_t_notify;
 872         pdq_uint32_t smt_status_reporting;
 873         pdq_uint32_t smt_ecm_state;
 874         pdq_uint32_t smt_cf_state;
 875         pdq_uint32_t smt_hold_state;
 876         pdq_uint32_t smt_remote_disconnect_flag;
 877         pdq_uint32_t smt_station_action;
 878         /* MAC Objects */
 879         pdq_uint32_t mac_frame_status_capabilities;
 880         pdq_uint32_t mac_t_max_greatest_lower_bound;
 881         pdq_uint32_t mac_tvx_greatest_lower_bound;
 882         pdq_uint32_t mac_paths_available;
 883         pdq_uint32_t mac_current_path;
 884         pdq_lanaddr_t mac_upstream_neighbor;
 885         pdq_lanaddr_t mac_old_upstream_neighbor;
 886         pdq_uint32_t mac_dup_addr_test;
 887         pdq_uint32_t mac_paths_requested;
 888         pdq_uint32_t mac_downstream_port_type;
 889         pdq_lanaddr_t mac_smt_address;
 890         pdq_uint32_t mac_t_req;
 891         pdq_uint32_t mac_t_neg;
 892         pdq_uint32_t mac_t_max;
 893         pdq_uint32_t mac_tvx_value;
 894         pdq_uint32_t mac_t_min;
 895         pdq_uint32_t mac_current_frame_status;
 896         pdq_uint32_t mac_frame_error_threshold;
 897         pdq_uint32_t mac_frame_error_ratio;
 898         pdq_uint32_t mac_rmt_state;
 899         pdq_uint32_t mac_da_flag;
 900         pdq_uint32_t mac_una_da_flag;
 901         pdq_uint32_t mac_frame_condition;
 902         pdq_uint32_t mac_chip_set;
 903         pdq_uint32_t mac_action;
 904         /* Port Objects */
 905         pdq_uint32_t port_pc_type[2];
 906         pdq_uint32_t port_pc_neighbor[2];
 907         pdq_uint32_t port_connection_policies[2];
 908         pdq_uint32_t port_remote_mac_indicated[2];
 909         pdq_uint32_t port_ce_state[2];
 910         pdq_uint32_t port_paths_requested[2];
 911         pdq_uint32_t port_mac_placement[2];
 912         pdq_uint32_t port_available_paths[2];
 913         pdq_uint32_t port_mac_loop_time[2];
 914         pdq_uint32_t port_tb_max[2];
 915         pdq_uint32_t port_bs_flag[2];
 916         pdq_uint32_t port_ler_estimate[2];
 917         pdq_uint32_t port_ler_cutoff[2];
 918         pdq_uint32_t port_ler_alarm[2];
 919         pdq_uint32_t port_connect_state[2];
 920         pdq_uint32_t port_pcm_state[2];
 921         pdq_uint32_t port_pc_withhold[2];
 922         pdq_uint32_t port_ler_condition[2];
 923         pdq_uint32_t port_chip_set[2];
 924         pdq_uint32_t port_action[2];
 925         /* Attachment Objects */
 926         pdq_uint32_t attachment_class;
 927         pdq_uint32_t attachment_optical_bypass_present;
 928         pdq_uint32_t attachment_imax_expiration;
 929         pdq_uint32_t attachment_inserted_status;
 930         pdq_uint32_t attachment_insert_policy;
 931     } fddi_mib_get;
 932 } pdq_response_fddi_mib_get_t;
 933
 934 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET  0x17C
 935
 936 typedef enum {
 937     PDQ_FDX_STATE_IDLE=0,
 938     PDQ_FDX_STATE_REQUEST=1,
 939     PDQ_FDX_STATE_CONFIRM=2,
 940     PDQ_FDX_STATE_OPERATION=3
 941 } pdq_fdx_state_t;
 942
 943 typedef struct {
 944     pdq_uint32_t dec_ext_mib_get_reserved;
 945     pdq_cmd_code_t dec_ext_mib_get_op;
 946     pdq_response_code_t dec_ext_mib_get_response;
 947     struct {
 948         /* SMT Objects */
 949         pdq_uint32_t esmt_station_type;
 950         /* MAC Objects */
 951         pdq_uint32_t emac_link_state;
 952         pdq_uint32_t emac_ring_purger_state;
 953         pdq_uint32_t emac_ring_purger_enable;
 954         pdq_uint32_t emac_frame_strip_mode;
 955         pdq_uint32_t emac_ring_error_reason;
 956         pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
 957         pdq_uint32_t emac_restricted_token_timeout;
 958         /* Port Objects */
 959         pdq_uint32_t eport_pmd_type[2];
 960         pdq_uint32_t eport_phy_state[2];
 961         pdq_uint32_t eport_reject_reason[2];
 962         /* Full Duplex Objects */
 963         pdq_boolean_t fdx_enable;
 964         pdq_boolean_t fdx_operational;
 965         pdq_fdx_state_t fdx_state;
 966     } dec_ext_mib_get;
 967 } pdq_response_dec_ext_mib_get_t;
 968
 969 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET       0x50
 970
 971 typedef struct {
 972     pdq_cmd_code_t snmp_set_op;
 973     struct {
 974         pdq_item_code_t item_code;
 975         pdq_uint32_t item_value;
 976         pdq_port_type_t item_port;
 977     } snmp_set_items[7];
 978     pdq_item_code_t snmp_set_eol_item_code;
 979 } pdq_cmd_snmp_set_t;
 980
 981 typedef enum {
 982     PDQ_CALLER_ID_NONE=0,
 983     PDQ_CALLER_ID_SELFTEST=1,
 984     PDQ_CALLER_ID_MFG=2,
 985     PDQ_CALLER_ID_FIRMWARE=5,
 986     PDQ_CALLER_ID_CONSOLE=8
 987 } pdq_caller_id_t;
 988
 989 typedef struct {
 990     pdq_uint32_t error_log_get__reserved;
 991     pdq_cmd_code_t error_log_get_op;
 992     pdq_response_code_t error_log_get_status;
 993     /* Error Header */
 994     pdq_uint32_t error_log_get_event_status;
 995     /* Event Information Block */
 996     pdq_caller_id_t error_log_get_caller_id;
 997     pdq_uint32_t error_log_get_timestamp[2];
 998     pdq_uint32_t error_log_get_write_count;
 999     /* Diagnostic Information */
1000     pdq_uint32_t error_log_get_fru_implication_mask;
1001     pdq_uint32_t error_log_get_test_id;
1002     pdq_uint32_t error_log_get_diag_reserved[6];
1003     /* Firmware Information */
1004     pdq_uint32_t error_log_get_fw_reserved[112];
1005 } pdq_response_error_log_get_t;
1006
1007 \f
1008 /*
1009  * Definitions for the Unsolicited Event Queue.
1010  */
1011 typedef enum {
1012     PDQ_UNSOLICITED_EVENT=0,
1013     PDQ_UNSOLICITED_COUNTERS=1
1014 } pdq_event_t;
1015
1016 typedef enum {
1017     PDQ_ENTITY_STATION=0,
1018     PDQ_ENTITY_LINK=1,
1019     PDQ_ENTITY_PHY_PORT=2,
1020     PDQ_ENTITY_MAX=3
1021 } pdq_entity_t;
1022
1023 typedef enum {
1024     PDQ_STATION_EVENT_TRACE_RECEIVED=1,
1025     PDQ_STATION_EVENT_MAX=2
1026 } pdq_station_event_t;
1027
1028 typedef enum {
1029     PDQ_STATION_EVENT_ARGUMENT_REASON=0,        /* pdq_uint32_t */
1030     PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1031 } pdq_station_event_argument_t;
1032
1033 typedef enum {
1034     PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
1035     PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
1036     PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
1037     PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
1038     PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
1039     PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
1040     PDQ_LINK_EVENT_NO_USER_BUFFER=9,
1041     PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1042     PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1043     PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1044     PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1045     PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1046     PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1047     PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1048     PDQ_LINK_EVENT_TRACE_INITIATED=17,
1049     PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18,
1050     PDQ_LINK_EVENT_MAX=19
1051 } pdq_link_event_t;
1052
1053 typedef enum {
1054     PDQ_LINK_EVENT_ARGUMENT_REASON=0,           /* pdq_rireason_t */
1055     PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1056     PDQ_LINK_EVENT_ARGUMENT_SOURCE=2,           /* pdq_lanaddr_t */
1057     PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1058     PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1059 } pdq_link_event_argument_t;
1060
1061 typedef enum {
1062     PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1063     PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1064     PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2,
1065     PDQ_PHY_EVENT_MAX=3
1066 } pdq_phy_event_t;
1067
1068 typedef enum {
1069     PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0,         /* pdq_lct_direction_t */
1070     PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1071 } pdq_phy_event_arguments;
1072
1073 struct _pdq_unsolicited_event_t {
1074     pdq_uint32_t rvent_reserved;
1075     pdq_event_t event_type;
1076     pdq_entity_t event_entity;
1077     pdq_uint32_t event_index;
1078     union {
1079         pdq_station_event_t station_event;
1080         pdq_link_event_t link_event;
1081         pdq_phy_event_t phy_event;
1082         pdq_uint32_t value;
1083     } event_code;
1084     /*
1085      * The remainder of this event is an argument list.
1086      */
1087     pdq_uint32_t event__filler[123];
1088 };
1089
1090 #endif /* _PDQREG_H */