1 /*******************************************************************************
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided
5 *that the following conditions are met:
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
8 *2. Redistributions in binary form must reproduce the above copyright notice,
9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided
10 *with the distribution.
12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
23 ********************************************************************************/
24 /*******************************************************************************/
26 * \brief The file defines the constants used by SAS/SATA LL layer
30 /*******************************************************************************/
32 #ifndef __SAMPIDEFS_H__
34 #define __SAMPIDEFS_H__
36 /* for Request Opcode of IOMB */
37 #define OPC_INB_ECHO 0x001 /* */
39 #define OPC_INB_PHYSTART 0x004 /* */
40 #define OPC_INB_PHYSTOP 0x005 /* */
41 #define OPC_INB_SSPINIIOSTART 0x006 /* */
42 #define OPC_INB_SSPINITMSTART 0x007 /* */
43 #define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */
44 #define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */
45 #define OPC_INB_SSPTGTIOSTART 0x00a /* */
46 #define OPC_INB_SSPTGTRSPSTART 0x00b /* */
47 #define OPC_INB_SSP_ABORT 0x00f /* */
48 #define OPC_INB_DEREG_DEV_HANDLE 0x010 /* 16 */
49 #define OPC_INB_GET_DEV_HANDLE 0x011 /* 17 */
50 #define OPC_INB_SMP_REQUEST 0x012 /* 18 */
52 #define OPC_INB_SMP_ABORT 0x014 /* 20 */
54 #define OPC_INB_SPC_REG_DEV 0x016 /* 22 V reserved */
55 #define OPC_INB_SATA_HOST_OPSTART 0x017 /* 23 */
56 #define OPC_INB_SATA_ABORT 0x018 /* 24 */
57 #define OPC_INB_LOCAL_PHY_CONTROL 0x019 /* 25 */
58 #define OPC_INB_SPC_GET_DEV_INFO 0x01a /* 26 V reserved */
60 #define OPC_INB_FW_FLASH_UPDATE 0x020 /* 32 */
62 #define OPC_INB_GPIO 0x022 /* 34 */
63 #define OPC_INB_SAS_DIAG_MODE_START_END 0x023 /* 35 */
64 #define OPC_INB_SAS_DIAG_EXECUTE 0x024 /* 36 */
65 #define OPC_INB_SPC_SAS_HW_EVENT_ACK 0x025 /* 37 V reserved */
66 #define OPC_INB_GET_TIME_STAMP 0x026 /* 38 */
67 #define OPC_INB_PORT_CONTROL 0x027 /* 39 */
68 #define OPC_INB_GET_NVMD_DATA 0x028 /* 40 */
69 #define OPC_INB_SET_NVMD_DATA 0x029 /* 41 */
70 #define OPC_INB_SET_DEVICE_STATE 0x02a /* 42 */
71 #define OPC_INB_GET_DEVICE_STATE 0x02b /* 43 */
72 #define OPC_INB_SET_DEV_INFO 0x02c /* 44 */
73 #define OPC_INB_SAS_RE_INITIALIZE 0x02d /* 45 V reserved */
74 #define OPC_INB_SGPIO 0x02e /* 46 */
75 #define OPC_INB_PCIE_DIAG_EXECUTE 0x02f /* 47 */
77 #define OPC_INB_SET_CONTROLLER_CONFIG 0x030 /* 48 */
78 #define OPC_INB_GET_CONTROLLER_CONFIG 0x031 /* 49 */
80 #define OPC_INB_REG_DEV 0x032 /* 50 SPCV */
81 #define OPC_INB_SAS_HW_EVENT_ACK 0x033 /* 51 SPCV */
82 #define OPC_INB_GET_DEV_INFO 0x034 /* 52 SPCV */
83 #define OPC_INB_GET_PHY_PROFILE 0x035 /* 53 SPCV */
84 #define OPC_INB_FLASH_OP_EXT 0x036 /* 54 SPCV */
85 #define OPC_INB_SET_PHY_PROFILE 0x037 /* 55 SPCV */
86 #define OPC_INB_GET_DFE_DATA 0x038 /* 56 SPCV */
87 #define OPC_INB_GET_VHIST_CAP 0x039 /* 57 SPCV12g */
90 #define OPC_INB_KEK_MANAGEMENT 0x100 /* 256 SPCV */
91 #define OPC_INB_DEK_MANAGEMENT 0x101 /* 257 SPCV */
92 #define OPC_INB_SSP_DIF_ENC_OPSTART 0x102 /* 258 SPCV */
93 #define OPC_INB_SATA_DIF_ENC_OPSTART 0x103 /* 259 SPCV */
94 #define OPC_INB_OPR_MGMT 0x104 /* 260 SPCV */
95 #define OPC_INB_ENC_TEST_EXECUTE 0x105 /* 261 SPCV */
96 #define OPC_INB_SET_OPERATOR 0x106 /* 262 SPCV */
97 #define OPC_INB_GET_OPERATOR 0x107 /* 263 SPCV */
98 #define OPC_INB_DIF_ENC_OFFLOAD_CMD 0x110 /* 272 SPCV */
100 #define OPC_INB_FW_PROFILE 0x888 /* 2184 SPCV */
102 /* for Response Opcode of IOMB */
103 #define OPC_OUB_ECHO 0x001 /* 1 */
105 #define OPC_OUB_SPC_HW_EVENT 0x004 /* 4 V reserved Now OPC_OUB_HW_EVENT */
106 #define OPC_OUB_SSP_COMP 0x005 /* 5 */
107 #define OPC_OUB_SMP_COMP 0x006 /* 6 */
108 #define OPC_OUB_LOCAL_PHY_CNTRL 0x007 /* 7 */
110 #define OPC_OUB_SPC_DEV_REGIST 0x00a /* 10 V reserved Now OPC_OUB_DEV_REGIST */
111 #define OPC_OUB_DEREG_DEV 0x00b /* 11 */
112 #define OPC_OUB_GET_DEV_HANDLE 0x00c /* 12 */
113 #define OPC_OUB_SATA_COMP 0x00d /* 13 */
114 #define OPC_OUB_SATA_EVENT 0x00e /* 14 */
115 #define OPC_OUB_SSP_EVENT 0x00f /* 15 */
117 #define OPC_OUB_SPC_DEV_HANDLE_ARRIV 0x010 /* 16 V reserved Now OPC_OUB_DEV_HANDLE_ARRIV */
119 #define OPC_OUB_SSP_RECV_EVENT 0x012 /* 18 */
120 #define OPC_OUB_SPC_DEV_INFO 0x013 /* 19 V reserved Now OPC_OUB_DEV_INFO*/
121 #define OPC_OUB_FW_FLASH_UPDATE 0x014 /* 20 */
123 #define OPC_OUB_GPIO_RESPONSE 0x016 /* 22 */
124 #define OPC_OUB_GPIO_EVENT 0x017 /* 23 */
125 #define OPC_OUB_GENERAL_EVENT 0x018 /* 24 */
127 #define OPC_OUB_SSP_ABORT_RSP 0x01a /* 26 */
128 #define OPC_OUB_SATA_ABORT_RSP 0x01b /* 27 */
129 #define OPC_OUB_SAS_DIAG_MODE_START_END 0x01c /* 28 */
130 #define OPC_OUB_SAS_DIAG_EXECUTE 0x01d /* 29 */
131 #define OPC_OUB_GET_TIME_STAMP 0x01e /* 30 */
132 #define OPC_OUB_SPC_SAS_HW_EVENT_ACK 0x01f /* 31 V reserved Now OPC_OUB_SAS_HW_EVENT_ACK*/
133 #define OPC_OUB_PORT_CONTROL 0x020 /* 32 */
134 #define OPC_OUB_SKIP_ENTRY 0x021 /* 33 */
135 #define OPC_OUB_SMP_ABORT_RSP 0x022 /* 34 */
136 #define OPC_OUB_GET_NVMD_DATA 0x023 /* 35 */
137 #define OPC_OUB_SET_NVMD_DATA 0x024 /* 36 */
138 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 0x025 /* 37 */
139 #define OPC_OUB_SET_DEVICE_STATE 0x026 /* 38 */
140 #define OPC_OUB_GET_DEVICE_STATE 0x027 /* 39 */
141 #define OPC_OUB_SET_DEV_INFO 0x028 /* 40 */
142 #define OPC_OUB_SAS_RE_INITIALIZE 0x029 /* 41 V reserved not replaced */
144 #define OPC_OUB_HW_EVENT 0x700 /* 1792 SPCV Was OPC_OUB_SPC_HW_EVENT*/
145 #define OPC_OUB_DEV_HANDLE_ARRIV 0x720 /* 1824 SPCV Was OPC_OUB_SPC_DEV_HANDLE_ARRIV*/
147 #define OPC_OUB_PHY_START_RESPONSE 0x804 /* 2052 SPCV */
148 #define OPC_OUB_PHY_STOP_RESPONSE 0x805 /* 2053 SPCV */
149 #define OPC_OUB_SGPIO_RESPONSE 0x82E /* 2094 SPCV */
150 #define OPC_OUB_PCIE_DIAG_EXECUTE 0x82F /* 2095 SPCV */
152 #define OPC_OUB_SET_CONTROLLER_CONFIG 0x830 /* 2096 SPCV */
153 #define OPC_OUB_GET_CONTROLLER_CONFIG 0x831 /* 2097 SPCV */
154 #define OPC_OUB_DEV_REGIST 0x832 /* 2098 SPCV */
155 #define OPC_OUB_SAS_HW_EVENT_ACK 0x833 /* 2099 SPCV */
156 #define OPC_OUB_DEV_INFO 0x834 /* 2100 SPCV */
157 #define OPC_OUB_GET_PHY_PROFILE_RSP 0x835 /* 2101 SPCV */
158 #define OPC_OUB_FLASH_OP_EXT_RSP 0x836 /* 2102 SPCV */
159 #define OPC_OUB_SET_PHY_PROFILE_RSP 0x837 /* 2103 SPCV */
160 #define OPC_OUB_GET_DFE_DATA_RSP 0x838 /* 2104 SPCV */
161 #define OPC_OUB_GET_VIST_CAP_RSP 0x839 /* Can be 2104 for SPCV12g */
163 #define OPC_OUB_FW_PROFILE 0x888 /* 2184 */
165 #define OPC_OUB_KEK_MANAGEMENT 0x900 /* 2304 SPCV */
166 #define OPC_OUB_DEK_MANAGEMENT 0x901 /* 2305 SPCV */
167 #define OPC_OUB_COMBINED_SSP_COMP 0x902 /* 2306 SPCV */
168 #define OPC_OUB_COMBINED_SATA_COMP 0x903 /* 2307 SPCV */
169 #define OPC_OUB_OPR_MGMT 0x904 /* 2308 SPCV */
170 #define OPC_OUB_ENC_TEST_EXECUTE 0x905 /* 2309 SPCV */
171 #define OPC_OUB_SET_OPERATOR 0x906 /* 2310 SPCV */
172 #define OPC_OUB_GET_OPERATOR 0x907 /* 2311 SPCV */
173 #define OPC_OUB_DIF_ENC_OFFLOAD_RSP 0x910 /* 2320 SPCV */
175 /* Definitions for encryption key management */
176 #define KEK_MGMT_SUBOP_INVALIDATE 0x1
177 #define KEK_MGMT_SUBOP_UPDATE 0x2
178 #define KEK_MGMT_SUBOP_KEYCARDINVALIDATE 0x3
179 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
181 #define DEK_MGMT_SUBOP_INVALIDATE 0x1
182 #define DEK_MGMT_SUBOP_UPDATE 0x2
184 /***************************************************
185 * typedef for IOMB structure
186 ***************************************************/
187 /** \brief the data structure of Echo Command
189 * use to describe MPI Echo Command (64 bytes)
192 typedef struct agsaEchoCmd_s {
197 /** \brief the data structure of PHY Start Command
199 * use to describe MPI PHY Start Command (64 bytes)
202 typedef struct agsaPhyStartCmd_s {
204 bit32 SscdAseSHLmMlrPhyId;
205 agsaSASIdentify_t sasIdentify;
206 bit32 analogSetupIdx;
211 #define SPINHOLD_DISABLE (0x00 << 14)
212 #define SPINHOLD_ENABLE (0x01 << 14)
213 #define LINKMODE_SAS (0x01 << 12)
214 #define LINKMODE_DSATA (0x02 << 12)
215 #define LINKMODE_AUTO (0x03 << 12)
216 #define LINKRATE_15 (0x01 << 8)
217 #define LINKRATE_30 (0x02 << 8)
218 #define LINKRATE_60 (0x04 << 8)
219 #define LINKRATE_12 (0x08 << 8)
221 /** \brief the data structure of PHY Stop Command
223 * use to describe MPI PHY Start Command (64 bytes)
226 typedef struct agsaPhyStopCmd_s {
232 /** \brief the data structure of SSP INI IO Start Command
234 * use to describe MPI SSP INI IO Start Command (64 bytes)
237 typedef struct agsaSSPIniIOStartCmd_s {
242 agsaSSPCmdInfoUnit_t SSPInfoUnit;
247 } agsaSSPIniIOStartCmd_t;
249 /** \brief the data structure of SSP INI TM Start Command
251 * use to describe MPI SSP INI TM Start Command (64 bytes)
254 typedef struct agsaSSPIniTMStartCmd_s {
262 } agsaSSPIniTMStartCmd_t;
264 /** \brief the data structure of SSP INI Extended IO Start Command
266 * use to describe MPI SSP INI Extended CDB Start Command (96 bytes to support 32 CDB)
269 typedef struct agsaSSPIniExtIOStartCmd_s {
273 bit32 SSPIuLendirMTlr;
276 /* bit32 AddrLow0; */
280 } agsaSSPIniExtIOStartCmd_t;
282 typedef struct agsaSSPIniEncryptIOStartCmd_s
285 bit32 deviceId; /* 2 */
286 bit32 dataLen; /* 3 */
287 bit32 dirMTlr; /* 4 */
288 bit32 sspiu_0_3_indcdbalL; /* 5 */
289 bit32 sspiu_4_7_indcdbalH; /* 6 */
290 bit32 sspiu_8_11; /* 7 */
291 bit32 sspiu_12_15; /* 8 */
292 bit32 sspiu_16_19; /* 9 */
293 bit32 sspiu_19_23; /* 10 */
294 bit32 sspiu_24_27; /* 11 */
295 bit32 epl_descL; /* 12 */
296 bit32 dpl_descL; /* 13 */
297 bit32 edpl_descH; /* 14 */
298 bit32 DIF_flags; /* 15 */
299 bit32 udt; /* 16 0x10 */
300 bit32 udtReplacementLo; /* 17 */
301 bit32 udtReplacementHi; /* 18 */
302 bit32 DIF_seed; /* 19 */
303 bit32 encryptFlagsLo; /* 20 0x14 */
304 bit32 encryptFlagsHi; /* 21 */
305 bit32 keyTag_W0; /* 22 */
306 bit32 keyTag_W1; /* 23 */
307 bit32 tweakVal_W0; /* 24 0x18 */
308 bit32 tweakVal_W1; /* 25 */
309 bit32 tweakVal_W2; /* 26 */
310 bit32 tweakVal_W3; /* 27 */
311 bit32 AddrLow0; /* 28 0x1C */
312 bit32 AddrHi0; /* 29 */
315 } agsaSSPIniEncryptIOStartCmd_t;
317 /** \brief the data structure of SSP Abort Command
319 * use to describe MPI SSP Abort Command (64 bytes)
322 typedef struct agsaSSPAbortCmd_s {
330 /** \brief the data structure of Register Device Command
332 * use to describe MPI DEVICE REGISTER Command (64 bytes)
335 typedef struct agsaRegDevCmd_s {
338 bit32 dTypeLRateAwtHa;
339 bit32 ITNexusTimeOut;
346 /** \brief the data structure of Deregister Device Handle Command
348 * use to describe MPI DEREGISTER DEVIDE HANDLE Command (64 bytes)
351 typedef struct agsaDeregDevHandleCmd_s {
356 } agsaDeregDevHandleCmd_t;
358 /** \brief the data structure of Get Device Handle Command
360 * use to describe MPI GET DEVIDE HANDLE Command (64 bytes)
363 typedef struct agsaGetDevHandleCmd_s {
365 bit32 DevADevTMaxDIDportId;
368 } agsaGetDevHandleCmd_t;
370 /** \brief the data structure of SMP Request Command
372 * use to describe MPI SMP REQUEST Command (64 bytes)
376 typedef struct agsaSMPCmd_s {
379 bit32 IR_IP_OV_res_phyId_DPdLen_res;
382 /* Bits [15:2] - Reserved */
383 /* Bits [23:16] - Len */
384 /* Bits [31:24] - Reserved */
389 typedef struct agsaSMPCmd_V_s {
391 bit32 deviceId; /* 2 */
392 bit32 IR_IP_OV_res_phyId_DPdLen_res;/* 3 */
395 /* Bits [15:2] - Reserved */
396 /* Bits [23:16] - Len */
397 /* Bits [31:24] - Reserved */
398 bit32 SMPHDR; /* 4 */
399 bit32 SMP3_0; /* 5 */
400 bit32 SMP7_4; /* 6 */
401 bit32 SMP11_8; /* 7 */
402 bit32 IndirL_SMPRF15_12; /* 8 */
403 bit32 IndirH_or_SMPRF19_16; /* 9 */
404 bit32 IndirLen_or_SMPRF23_20; /* 10 */
405 bit32 R_or_SMPRF27_24; /* 11 */
406 bit32 ISRAL_or_SMPRF31_28; /* 12 */
407 bit32 ISRAH_or_SMPRF35_32; /* 13 */
408 bit32 ISRL_or_SMPRF39_36; /* 14 */
409 bit32 R_or_SMPRF43_40; /* 15 */
412 /** \brief the data structure of SMP Abort Command
414 * use to describe MPI SMP Abort Command (64 bytes)
417 typedef struct agsaSMPAbortCmd_s {
425 /** \brief the data structure of SATA Start Command
427 * use to describe MPI SATA Start Command (64 bytes)
430 typedef struct agsaSATAStartCmd_s {
432 bit32 deviceId; /* 2 */
433 bit32 dataLen; /* 3 */
434 bit32 optNCQTagataProt; /* 4 */
435 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */
436 bit32 reserved1; /* 10 */
437 bit32 reserved2; /* 11 */
438 bit32 AddrLow0; /* 12 */
439 bit32 AddrHi0; /* 13 */
442 bit32 ATAPICDB[4]; /* 16-19 */
443 } agsaSATAStartCmd_t;
445 typedef struct agsaSATAEncryptStartCmd_s
448 bit32 IniDeviceId; /* 2 */
449 bit32 dataLen; /* 3 */
450 bit32 optNCQTagataProt; /* 4 */
451 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */
452 bit32 reserved1; /* 10 */
453 bit32 Res_EPL_DESCL; /* 11 */
454 bit32 resSKIPBYTES; /* 12 */
455 bit32 Res_DPL_DESCL_NDPLR; /* 13 DIF per LA Address lo if DPLE is 1 */
456 bit32 Res_EDPL_DESCH; /* 14 DIF per LA Address hi if DPLE is 1 */
457 bit32 DIF_flags; /* 15 */
459 bit32 udtReplacementLo; /* 17 */
460 bit32 udtReplacementHi; /* 18 */
461 bit32 DIF_seed; /* 19 */
462 bit32 encryptFlagsLo; /* 20 */
463 bit32 encryptFlagsHi; /* 21 */
464 bit32 keyTagLo; /* 22 */
465 bit32 keyTagHi; /* 23 */
466 bit32 tweakVal_W0; /* 24 */
467 bit32 tweakVal_W1; /* 25 */
468 bit32 tweakVal_W2; /* 26 */
469 bit32 tweakVal_W3; /* 27 */
470 bit32 AddrLow0; /* 28 */
471 bit32 AddrHi0; /* 29 */
474 } agsaSATAEncryptStartCmd_t;
476 /** \brief the data structure of SATA Abort Command
478 * use to describe MPI SATA Abort Command (64 bytes)
481 typedef struct agsaSATAAbortCmd_s {
487 } agsaSATAAbortCmd_t;
489 /** \brief the data structure of Local PHY Control Command
491 * use to describe MPI LOCAL PHY CONTROL Command (64 bytes)
494 typedef struct agsaLocalPhyCntrlCmd_s {
498 } agsaLocalPhyCntrlCmd_t;
500 /** \brief the data structure of Get Device Info Command
502 * use to describe MPI GET DEVIDE INFO Command (64 bytes)
505 typedef struct agsaGetDevInfoCmd_s {
509 } agsaGetDevInfoCmd_t;
511 /** \brief the data structure of HW Reset Command
513 * use to describe MPI HW Reset Command (64 bytes)
516 typedef struct agsaHWResetCmd_s {
521 /** \brief the data structure of Firmware download
523 * use to describe MPI FW DOWNLOAD Command (64 bytes)
525 typedef struct agsaFwFlashUpdate_s {
527 bit32 curImageOffset;
535 } agsaFwFlashUpdate_t;
538 /** \brief the data structure EXT Flash Op
540 * use to describe Extented Flash Operation Command (128 bytes)
542 typedef struct agsaFwFlashOpExt_s {
553 } agsaFwFlashOpExt_t;
555 /** \brief the data structure EXT Flash Op
557 * use to describe Extented Flash Operation Command (64 bytes)
559 typedef struct agsaFwFlashOpExtRsp_s {
566 } agsaFwFlashOpExtRsp_t;
569 #define FWFLASH_IOMB_RESERVED_LEN 0x07
571 #ifdef SPC_ENABLE_PROFILE
572 typedef struct agsaFwProfileIOMB_s {
574 bit32 tcid_processor_cmd;
582 } agsaFwProfileIOMB_t;
583 #define FWPROFILE_IOMB_RESERVED_LEN 0x07
585 /** \brief the data structure of GPIO Commannd
587 * use to describe MPI GPIO Command (64 bytes)
589 typedef struct agsaGPIOCmd_s {
596 bit32 OT19_12; /* reserved for SPCv controller */
604 #define GPIO_GW_BIT 0x1
605 #define GPIO_GR_BIT 0x2
606 #define GPIO_GS_BIT 0x4
607 #define GPIO_GE_BIT 0x8
609 /** \brief the data structure of SAS Diagnostic Start/End Command
611 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
613 typedef struct agsaSASDiagStartEndCmd_s {
615 bit32 OperationPhyId;
617 } agsaSASDiagStartEndCmd_t;
619 /** \brief the data structure of SAS Diagnostic Execute Command
621 * use to describe MPI SAS Diagnostic Execute Command for SPCv (128 bytes)
623 typedef struct agsaSASDiagExecuteCmd_s {
625 bit32 CmdTypeDescPhyId;/* 2 */
626 bit32 Pat1Pat2; /* 3 */
627 bit32 Threshold; /* 4 */
628 bit32 CodePatErrMsk; /* 5 */
630 bit32 PERF1CTL; /* 7 */
631 bit32 THRSHLD1; /* 8 */
632 bit32 reserved[23]; /* 9 31 */
633 } agsaSASDiagExecuteCmd_t;
636 /** \brief the data structure of SAS Diagnostic Execute Command
638 * use to describe MPI SAS Diagnostic Execute Command for SPC (64 bytes)
640 typedef struct agsa_SPC_SASDiagExecuteCmd_s {
642 bit32 CmdTypeDescPhyId;/* 2 */
643 bit32 Pat1Pat2; /* 3 */
644 bit32 Threshold; /* 4 */
645 bit32 CodePatErrMsk; /* 5 */
647 bit32 PERF1CTL; /* 7 */
648 bit32 reserved[8]; /* 8 15 */
649 } agsa_SPC_SASDiagExecuteCmd_t;
650 #define SAS_DIAG_PARAM_BYTES 24
653 /** \brief the data structure of SSP TGT IO Start Command
655 * use to describe MPI SSP TGT IO Start Command (64 bytes)
658 typedef struct agsaSSPTgtIOStartCmd_s {
660 bit32 deviceId; /* 2 */
661 bit32 dataLen; /* 3 */
662 bit32 dataOffset; /* 4 */
663 bit32 INITagAgrDir; /* 5 */
664 bit32 reserved; /* 6 */
665 bit32 DIF_flags; /* 7 */
667 bit32 udtReplacementLo; /* 9 */
668 bit32 udtReplacementHi; /* 10 */
669 bit32 DIF_seed; /* 11 */
670 bit32 AddrLow0; /* 12 */
671 bit32 AddrHi0; /* 13 */
674 } agsaSSPTgtIOStartCmd_t;
676 /** \brief the data structure of SSP TGT Response Start Command
678 * use to describe MPI SSP TGT Response Start Command (64 bytes)
681 typedef struct agsaSSPTgtRspStartCmd_s {
691 } agsaSSPTgtRspStartCmd_t;
693 /** \brief the data structure of Device Handle Accept Command
695 * use to describe MPI Device Handle Accept Command (64 bytes)
698 typedef struct agsaDevHandleAcceptCmd_s {
702 bit32 DevA_MCN_R_R_HA_ITNT;
704 } agsaDevHandleAcceptCmd_t;
706 /** \brief the data structure of SAS HW Event Ack Command
708 * use to describe MPI SAS HW Event Ack Command (64 bytes)
711 typedef struct agsaSASHwEventAckCmd_s {
713 bit32 sEaPhyIdPortId;
717 } agsaSASHwEventAckCmd_t;
719 /** \brief the data structure of Get Time Stamp Command
721 * use to describe MPI Get Time Stamp Command (64 bytes)
724 typedef struct agsaGetTimeStampCmd_s {
727 } agsaGetTimeStampCmd_t;
729 /** \brief the data structure of Port Control Command
731 * use to describe MPI Port Control Command (64 bytes)
734 typedef struct agsaPortControlCmd_s {
740 } agsaPortControlCmd_t;
742 /** \brief the data structure of Set NVM Data Command
744 * use to describe MPI Set NVM Data Command (64 bytes)
747 typedef struct agNVMIndirect_s {
756 typedef union agsaSetNVMData_s {
758 agNVMIndirect_t indirectData;
761 typedef struct agsaSetNVMDataCmd_s {
765 agsaSetNVMData_t Data;
766 } agsaSetNVMDataCmd_t;
768 /** \brief the data structure of Get NVM Data Command
770 * use to describe MPI Get NVM Data Command (64 bytes)
773 typedef struct agsaGetNVMDataCmd_s {
782 } agsaGetNVMDataCmd_t;
784 #define TWI_DEVICE 0x0
785 #define C_SEEPROM 0x1
786 #define VPD_FLASH 0x4
787 #define AAP1_RDUMP 0x5
788 #define IOP_RDUMP 0x6
789 #define EXPAN_ROM 0x7
791 #define DIRECT_MODE 0x0
792 #define INDIRECT_MODE 0x1
794 #define IRMode 0x80000000
795 #define IPMode 0x80000000
796 #define NVMD_TYPE 0x0000000F
797 #define NVMD_STAT 0x0000FFFF
798 #define NVMD_LEN 0xFF000000
800 #define TWI_DEVICE 0x0
803 /** \brief the data structure of Set Device State Command
805 * use to describe MPI Set Device State Command (64 bytes)
808 typedef struct agsaSetDeviceStateCmd_s {
813 } agsaSetDeviceStateCmd_t;
815 #define DS_OPERATIONAL 0x01
816 #define DS_IN_RECOVERY 0x03
817 #define DS_IN_ERROR 0x04
818 #define DS_NON_OPERATIONAL 0x07
820 /** \brief the data structure of Get Device State Command
822 * use to describe MPI Get Device State Command (64 bytes)
825 typedef struct agsaGetDeviceStateCmd_s {
829 } agsaGetDeviceStateCmd_t;
831 /** \brief the data structure of Set Device Info Command
833 * use to describe MPI OPC_INB_SET_DEV_INFO (0x02c) Command (64 bytes)
836 typedef struct agsaSetDevInfoCmd_s {
840 bit32 DEVA_MCN_R_ITNT;
842 } agsaSetDevInfoCmd_t;
844 #define SET_DEV_INFO_V_DW3_MASK 0x0000003F
845 #define SET_DEV_INFO_V_DW4_MASK 0xFF07FFFF
846 #define SET_DEV_INFO_SPC_DW3_MASK 0x7
847 #define SET_DEV_INFO_SPC_DW4_MASK 0x003FFFF
849 #define SET_DEV_INFO_V_DW3_SM_SHIFT 3
850 #define SET_DEV_INFO_V_DW3_SA_SHIFT 2
851 #define SET_DEV_INFO_V_DW3_SR_SHIFT 1
852 #define SET_DEV_INFO_V_DW3_SI_SHIFT 0
854 #define SET_DEV_INFO_V_DW4_MCN_SHIFT 24
855 #define SET_DEV_INFO_V_DW4_AWT_SHIFT 17
856 #define SET_DEV_INFO_V_DW4_RETRY_SHIFT 16
857 #define SET_DEV_INFO_V_DW4_ITNEXUS_SHIFT 0
859 /** \brief the data structure of SAS Re_Initialize Command
861 * use to describe MPI SAS RE_INITIALIZE Command (64 bytes)
864 typedef struct agsaSasReInitializeCmd_s {
868 bit32 openRejReCmdData;
871 } agsaSasReInitializeCmd_t;
874 /** \brief the data structure of SGPIO Command
876 * use to describe MPI serial GPIO Command (64 bytes)
879 typedef struct agsaSGpioCmd_s {
881 bit32 regIndexRegTypeFunctionFrameType;
883 bit32 writeData[OSSA_SGPIO_MAX_WRITE_DATA_COUNT];
886 /** \brief the data structure of PCIE Diagnostic Command
888 * use to describe MPI PCIE Diagnostic Command for SPCv (128 bytes)
891 typedef struct agsaPCIeDiagExecuteCmd_s {
893 bit32 CmdTypeDesc; /* 2 */
894 bit32 UUM_EDA; /* 3 */
895 bit32 UDTR1_UDT0; /* 4 */
896 bit32 UDT5_UDT2; /* 5 */
897 bit32 UDTR5_UDTR2; /* 6 */
898 bit32 Res_IOS; /* 7 */
899 bit32 rdAddrLower; /* 8 */
900 bit32 rdAddrUpper; /* 9 */
901 bit32 wrAddrLower; /* 10 */
902 bit32 wrAddrUpper; /* 11 */
904 bit32 pattern; /* 13 */
905 bit32 reserved2[2]; /* 14 15 */
906 bit32 reserved3[16]; /* 15 31 */
907 } agsaPCIeDiagExecuteCmd_t;
910 /** \brief the data structure of PCI Diagnostic Command for SPC
912 * use to describe MPI PCI Diagnostic Command for SPC (64 bytes)
915 typedef struct agsa_SPC_PCIDiagExecuteCmd_s {
926 } agsa_SPC_PCIDiagExecuteCmd_t;
928 /** \brief the data structure of GET DFE Data Command
930 * use to describe GET DFE Data Command for SPCv (128 bytes)
933 typedef struct agsaGetDDEFDataCmd_s {
935 bit32 reserved_In_Ln;/* 2 */
937 bit32 reserved1[3]; /* 4 - 6 */
938 bit32 Buf_AddrL; /* 7 */
939 bit32 Buf_AddrH; /* 8 */
940 bit32 Buf_Len; /* 9 */
941 bit32 E_reserved; /* 10 */
942 bit32 reserved2[21]; /* 11 - 31 */
943 } agsaGetDDEFDataCmd_t;
946 /***********************************************
948 ***********************************************/
949 /** \brief the data structure of Echo Response
951 * use to describe MPI Echo Response (64 bytes)
954 typedef struct agsaEchoRsp_s {
959 /** \brief the data structure of HW Event from Outbound
961 * use to describe MPI HW Event (64 bytes)
964 typedef struct agsaHWEvent_SPC_OUB_s {
965 bit32 LRStatusEventPhyIdPortId;
968 agsaSASIdentify_t sasIdentify;
969 agsaFisRegDeviceToHost_t sataFis;
970 } agsaHWEvent_SPC_OUB_t;
972 #define PHY_ID_BITS 0x000000F0
973 #define LINK_RATE_MASK 0xF0000000
974 #define STATUS_BITS 0x0F000000
975 #define HW_EVENT_BITS 0x00FFFF00
977 typedef struct agsaHWEvent_Phy_OUB_s {
981 } agsaHWEvent_Phy_OUB_t;
983 /** \brief the data structure of HW Event from Outbound
985 * use to describe MPI HW Event (64 bytes)
988 typedef struct agsaHWEvent_V_OUB_s {
989 bit32 LRStatEventPortId;
991 bit32 RsvPhyIdNpipRsvPortState;
992 agsaSASIdentify_t sasIdentify;
993 agsaFisRegDeviceToHost_t sataFis;
994 } agsaHWEvent_V_OUB_t;
996 #define PHY_ID_V_BITS 0x00FF0000
997 #define NIPP_V_BITS 0x0000FF00
1001 /** \brief the data structure of SSP Completion Response
1003 * use to describe MPI SSP Completion Response (1024 bytes)
1006 typedef struct agsaSSPCompletionRsp_s {
1011 agsaSSPResponseInfoUnit_t SSPrsp;
1014 bit32 respData1[239];
1015 } agsaSSPCompletionRsp_t;
1018 /** \brief the data structure of SSP Completion DIF Response
1020 * use to describe MPI SSP Completion DIF Response (1024 bytes)
1023 typedef struct agsaSSPCompletionDifRsp_s {
1033 bit32 ExpectedCRCUDT01;
1034 bit32 ExpectedUDT2345;
1035 bit32 ActualCRCUDT01;
1036 bit32 ActualUDT2345;
1038 bit32 ErrBoffsetEDataLen;
1041 } agsaSSPCompletionDifRsp_t;
1044 /* SSPTag bit fields Bits [31:16] */
1045 #define SSP_RESCV_BIT 0x00010000 /* Bits [16] */
1046 #define SSP_RESCV_PAD 0x00060000 /* Bits [18:17] */
1047 #define SSP_RESCV_PAD_SHIFT 17
1048 #define SSP_AGR_S_BIT (1 << 19) /* Bits [19] */
1050 /** \brief the data structure of SMP Completion Response
1052 * use to describe MPI SMP Completion Response (1024 bytes)
1055 typedef struct agsaSMPCompletionRsp_s {
1060 } agsaSMPCompletionRsp_t;
1062 /** \brief the data structure of Deregister Device Response
1064 * use to describe MPI Deregister Device Response (64 bytes)
1067 typedef struct agsaDeregDevHandleRsp_s {
1072 } agsaDeregDevHandleRsp_t;
1074 /** \brief the data structure of Get Device Handle Response
1076 * use to describe MPI Get Device Handle Response (64 bytes)
1079 typedef struct agsaGetDevHandleRsp_s {
1081 bit32 DeviceIdcPortId;
1083 } agsaGetDevHandleRsp_t;
1085 #define DEVICE_IDC_BITS 0x00FFFF00
1086 #define DEVICE_ID_BITS 0x00000FFF
1088 /** \brief the data structure of Local Phy Control Response
1090 * use to describe MPI Local Phy Control Response (64 bytes)
1093 typedef struct agsaLocalPhyCntrlRsp_s {
1098 } agsaLocalPhyCntrlRsp_t;
1100 #define LOCAL_PHY_OP_BITS 0x0000FF00
1101 #define LOCAL_PHY_PHYID 0x000000FF
1103 /** \brief the data structure of DEVICE_REGISTRATION Response
1105 * use to describe device registration response (64 bytes)
1108 typedef struct agsaDeviceRegistrationRsp_s {
1113 } agsaDeviceRegistrationRsp_t;
1116 #define FAILURE_OUT_OF_RESOURCE 0x01 /* The device registration failed because the SPC 8x6G is running out of device handle resources. The parameter DEVICE_ID is not used. */
1117 #define FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /* The device registration failed because the SPC 8x6G detected an existing device handle with a similar SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */
1118 #define FAILURE_INVALID_PHY_ID 0x03 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an invalid (out-of-range) PHY ID. */
1119 #define FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an already -registered PHY ID for a directly attached SATA drive. */
1120 #define FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /* PORT_ID specified in the REGISTER_DEVICE Command is out-of range (0-7). */
1121 #define FAILURE_PORT_NOT_VALID_STATE 0x06 /* The PORT_ID specified in the REGISTER_DEVICE Command is not in PORT_VALID state. */
1122 #define FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /* The device type, specified in the
\91S field in the REGISTER_DEVICE Command is not valid. */
1124 #define MPI_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 /* The device registration failed because the SPCv controller is running out of device handle resources. The parameter DEVICE_ID is not used. */
1125 #define MPI_ERR_DEVICE_ALREADY_REGISTERED 0x1021 /* The device registration failed because the SPCv controller detected an existing device handle with the same SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */
1126 #define MPI_ERR_DEVICE_TYPE_NOT_VALID 0x1022 /* The device type, specified in the
\91S field in the REGISTER_DEVICE_HANDLE Command (page 274) is not valid. */
1127 #define MPI_ERR_PORT_INVALID_PORT_ID 0x1041 /* specified in the REGISTER_DEVICE_HANDLE Command (page 274) is invalid. i.e Out of supported range */
1128 #define MPI_ERR_PORT_STATE_NOT_VALID 0x1042 /* The PORT_ID specified in the REGISTER_DEVICE_HANDLE Command (page 274) is not in PORT_VALID state. */
1129 #define MPI_ERR_PORT_STATE_NOT_IN_USE 0x1043
1130 #define MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044
1131 #define MPI_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1132 #define MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /*MPI_ERR_DEVICE_ACCEPT_PENDING*/
1135 #define MPI_ERR_PHY_ID_INVALID 0x1061 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an invalid (out-of-range) PHY ID. */
1136 #define MPI_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an alreadyregistered PHY ID for a directly-attached SATA drive. */
1141 /** \brief the data structure of SATA Completion Response
1143 * use to describe MPI SATA Completion Response (64 bytes)
1146 typedef struct agsaSATACompletionRsp_s {
1152 } agsaSATACompletionRsp_t;
1154 /** \brief the data structure of SATA Event Response
1156 * use to describe MPI SATA Event Response (64 bytes)
1159 typedef struct agsaSATAEventRsp_s {
1165 } agsaSATAEventRsp_t;
1167 /** \brief the data structure of SSP Event Response
1169 * use to describe MPI SSP Event Response (64 bytes)
1172 typedef struct agsaSSPEventRsp_s {
1178 bit32 EVT_PARAM0_or_LBAH;
1179 bit32 EVT_PARAM1_or_LBAL;
1182 bit32 UDT1_E_UDT0_E_CRC_E;
1183 bit32 UDT5_E_UDT4_E_UDT3_E_UDT2_E;
1184 bit32 UDT1_A_UDT0_A_CRC_A;
1185 bit32 UDT5_A_UDT4_A_UDT3_A_UDT2_A;
1186 bit32 HW_DEVID_Reserved_DIF_ERR;
1187 bit32 EDATA_LEN_ERR_BOFF;
1189 } agsaSSPEventRsp_t;
1191 #define SSPTAG_BITS 0x0000FFFF
1193 /** \brief the data structure of Get Device Info Response
1195 * use to describe MPI Get Device Info Response (64 bytes)
1198 typedef struct agsaGetDevInfoRspSpc_s {
1202 bit32 dTypeSrateSMPTOArPortID;
1203 bit32 FirstBurstSizeITNexusTimeOut;
1207 } agsaGetDevInfoRsp_t;
1209 #define SMPTO_BITS 0xFFFF
1210 #define NEXUSTO_BITS 0xFFFF
1211 #define FIRST_BURST 0xFFFF
1212 #define FLAG_BITS 0x3
1213 #define LINK_RATE_BITS 0xFF
1214 #define DEV_TYPE_BITS 0x30000000
1216 /** \brief the data structure of Get Device Info Response V
1218 * use to describe MPI Get Device Info Response (64 bytes)
1221 typedef struct agsaGetDevInfoRspV_s {
1225 bit32 ARSrateSMPTimeOutPortID;
1226 bit32 IRMcnITNexusTimeOut;
1230 } agsaGetDevInfoRspV_t;
1232 #define SMPTO_VBITS 0xFFFF
1233 #define NEXUSTO_VBITS 0xFFFF
1234 #define FIRST_BURST_MCN 0xF
1235 #define FLAG_VBITS 0x3
1236 #define LINK_RATE_VBITS 0xFF
1237 #define DEV_TYPE_VBITS 0x10000000
1240 /** \brief the data structure of Get Phy Profile Command IOMB V
1243 typedef struct agsaGetPhyProfileCmd_V_s {
1245 bit32 Reserved_Ppc_SOP_PHYID;
1247 } agsaGetPhyProfileCmd_V_t;
1250 /** \brief the data structure of Get Phy Profile Response IOMB V
1253 typedef struct agsaGetPhyProfileRspV_s {
1256 bit32 Reserved_Ppc_SOP_PHYID;
1257 bit32 PageSpecificArea[12];
1258 } agsaGetPhyProfileRspV_t;
1260 /** \brief the data structure of Set Phy Profile Command IOMB V
1263 typedef struct agsaSetPhyProfileCmd_V_s {
1265 bit32 Reserved_Ppc_SOP_PHYID;
1266 bit32 PageSpecificArea[29];
1267 } agsaSetPhyProfileCmd_V_t;
1269 /** \brief the data structure of GetVis Command IOMB V
1270 * OPC_OUB_GET_VIST_CAP_RSP
1272 typedef struct agsaGetVHistCap_V_s {
1282 bit32 reserved2[22];
1283 } agsaGetVHistCap_V_t;
1285 /** \brief the data structure of Set Phy Profile Response IOMB V
1288 typedef struct agsaSetPhyProfileRspV_s {
1291 bit32 Reserved_Ppc_PHYID;
1292 bit32 PageSpecificArea[12];
1293 } agsaSetPhyProfileRspV_t;
1295 typedef struct agsaGetPhyInfoV_s {
1297 bit32 Reserved_SOP_PHYID;
1299 } agsaGetPhyInfoV_t;
1302 #define SPC_GET_SAS_PHY_ERR_COUNTERS 1
1303 #define SPC_GET_SAS_PHY_ERR_COUNTERS_CLR 2
1304 #define SPC_GET_SAS_PHY_BW_COUNTERS 3
1307 /** \brief the data structure of FW_FLASH_UPDATE Response
1309 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
1312 typedef struct agsaFwFlashUpdateRsp_s {
1316 } agsaFwFlashUpdateRsp_t;
1318 #ifdef SPC_ENABLE_PROFILE
1319 typedef struct agsaFwProfileRsp_s {
1324 } agsaFwProfileRsp_t;
1326 /** \brief the data structure of GPIO Response
1328 * use to describe MPI GPIO Response (64 bytes)
1330 typedef struct agsaGPIORsp_s {
1343 /** \brief the data structure of GPIO Event
1345 * use to describe MPI GPIO Event Response (64 bytes)
1347 typedef struct agsaGPIOEvent_s {
1352 /** \brief the data structure of GENERAL_EVENT Response
1354 * use to describe MPI GENERNAL_EVENT Notification (64 bytes)
1357 typedef struct agsaGenernalEventRsp_s {
1359 bit32 inboundIOMB[14];
1360 } agsaGenernalEventRsp_t;
1362 /** \brief the data structure of SSP_ABORT Response
1364 * use to describe MPI SSP_ABORT (64 bytes)
1367 typedef struct agsaSSPAbortRsp_s {
1372 } agsaSSPAbortRsp_t;
1374 /** \brief the data structure of SATA_ABORT Response
1376 * use to describe MPI SATA_ABORT (64 bytes)
1379 typedef struct agsaSATAAbortRsp_s {
1384 } agsaSATAAbortRsp_t;
1386 /** \brief the data structure of SAS Diagnostic Start/End Response
1388 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
1391 typedef struct agsaSASDiagStartEndRsp_s {
1395 } agsaSASDiagStartEndRsp_t;
1397 /** \brief the data structure of SAS Diagnostic Execute Response
1399 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
1402 typedef struct agsaSASDiagExecuteRsp_s {
1404 bit32 CmdTypeDescPhyId;
1408 } agsaSASDiagExecuteRsp_t;
1410 /** \brief the data structure of General Event Notification Response
1412 * use to describe MPI General Event Notification Response (64 bytes)
1415 typedef struct agsaGeneralEventRsp_s {
1417 bit32 inbIOMBpayload[14];
1418 } agsaGeneralEventRsp_t;
1420 #define GENERAL_EVENT_PAYLOAD 14
1421 #define OPCODE_BITS 0x00000fff
1424 Table 171 GENERAL_EVENT Notification Status Field Codes
1425 Value Name Description
1427 #define GEN_EVENT_IOMB_V_BIT_NOT_SET 0x01 /* INBOUND_ Inbound IOMB is received with the V bit in the IOMB header not set. */
1428 #define GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED 0x02 /* Inbound IOMB is received with an unsupported OPC. */
1429 #define GEN_EVENT_IOMB_INVALID_OBID 0x03 /* INBOUND Inbound IOMB is received with an invalid OBID. */
1430 #define GEN_EVENT_DS_IN_NON_OPERATIONAL 0x39 /* DEVICE_HANDLE_ACCEPT command failed due to the device being in DS_NON_OPERATIONAL state. */
1431 #define GEN_EVENT_DS_IN_RECOVERY 0x3A /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_IN_RECOVERY state. */
1432 #define GEN_EVENT_DS_INVALID 0x49 /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_INVALID state. */
1434 #define GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x50 /* Indicates the PCIe Read Request to fetch one or more inbound IOMBs received
1435 a failed completion response. The first and second Dwords of the
1436 INBOUND IOMB field ( Dwords 2 and 3) contains information to identifying
1437 the location in the inbound queue where the error occurred.
1438 Dword 2 bits[15:0] contains the inbound queue number.
1439 Dword 2 bits[31:16] specifies how many consecutive IOMBs were affected
1441 Dword 3 specifies the Consumer Index [CI] of the inbound queue where
1442 the DMA operation failed.*/
1444 /** \brief the data structure of SSP Request Received Notification
1446 * use to describe MPI SSP Request Received Notification ( 1024 bytes)
1449 typedef struct agsaSSPReqReceivedNotify_s {
1452 bit32 frameTypeHssa;
1455 } agsaSSPReqReceivedNotify_t;
1457 #define SSPIUL_BITS 0x0000FFFF
1458 #define INITTAG_BITS 0x0000FFFF
1459 #define FRAME_TYPE 0x000000FF
1460 #define TLR_BITS 0x00000300
1462 /** \brief the data structure of Device Handle Arrived Notification
1464 * use to describe MPI Device Handle Arrived Notification ( 64 bytes)
1467 typedef struct agsaDeviceHandleArrivedNotify_s {
1469 bit32 HostAssignedIdFwdDeviceId;
1470 bit32 ProtConrPortId;
1475 } agsaDeviceHandleArrivedNotify_t;
1478 #define Conrate_V_MASK 0x0000F000
1479 #define Conrate_V_SHIFT 12
1480 #define Conrate_SPC_MASK 0x0000F000
1481 #define Conrate_SPC_SHIFT 4
1483 #define Protocol_SPC_MASK 0x00000700
1484 #define Protocol_SPC_SHIFT 8
1485 #define Protocol_SPC_MASK 0x00000700
1486 #define Protocol_SPC_SHIFT 8
1488 #define PortId_V_MASK 0xFF
1489 #define PortId_SPC_MASK 0x0F
1491 #define PROTOCOL_BITS 0x00000700
1492 #define PROTOCOL_SHIFT 8
1494 #define SHIFT_REG_64K_MASK 0xffff0000
1495 #define SHIFT_REG_BIT_SHIFT 8
1496 #define SPC_GSM_SM_OFFSET 0x400000
1497 #define SPCV_GSM_SM_OFFSET 0x0
1499 /** \brief the data structure of Get Time Stamp Response
1501 * use to describe MPI Get TIme Stamp Response ( 64 bytes)
1504 typedef struct agsaGetTimeStampRsp_s {
1506 bit32 timeStampLower;
1507 bit32 timeStampUpper;
1509 } agsaGetTimeStampRsp_t;
1511 /** \brief the data structure of SAS HW Event Ack Response
1513 * use to describe SAS HW Event Ack Response ( 64 bytes)
1516 typedef struct agsaSASHwEventAckRsp_s {
1520 } agsaSASHwEventAckRsp_t;
1522 /** \brief the data structure of Port Control Response
1524 * use to describe Port Control Response ( 64 bytes)
1527 typedef struct agsaPortControlRsp_s {
1531 bit32 rsvdPortState;
1533 } agsaPortControlRsp_t;
1535 /** \brief the data structure of SMP Abort Response
1537 * use to describe SMP Abort Response ( 64 bytes)
1540 typedef struct agsaSMPAbortRsp_s {
1545 } agsaSMPAbortRsp_t;
1547 /** \brief the data structure of Get NVMD Data Response
1549 * use to describe MPI Get NVMD Data Response (64 bytes)
1552 typedef struct agsaGetNVMDataRsp_s {
1554 bit32 iRTdaBnDpsAsNvm;
1557 } agsaGetNVMDataRsp_t;
1559 /** \brief the data structure of Set NVMD Data Response
1561 * use to describe MPI Set NVMD Data Response (64 bytes)
1564 typedef struct agsaSetNVMDataRsp_s {
1566 bit32 iPTdaBnDpsAsNvm;
1569 } agsaSetNVMDataRsp_t;
1571 /** \brief the data structure of Device Handle Removal
1573 * use to describe MPI Device Handle Removel Notification (64 bytes)
1576 typedef struct agsaDeviceHandleRemoval_s {
1580 } agsaDeviceHandleRemoval_t;
1582 /** \brief the data structure of Set Device State Response
1584 * use to describe MPI Set Device State Response (64 bytes)
1587 typedef struct agsaSetDeviceStateRsp_s {
1593 } agsaSetDeviceStateRsp_t;
1595 #define NDS_BITS 0x0F
1596 #define PDS_BITS 0xF0
1598 /** \brief the data structure of Get Device State Response
1600 * use to describe MPI Get Device State Response (64 bytes)
1603 typedef struct agsaGetDeviceStateRsp_s {
1609 } agsaGetDeviceStateRsp_t;
1611 /** \brief the data structure of Set Device Info Response
1613 * use to describe MPI Set Device Info Response (64 bytes)
1616 typedef struct agsaSetDeviceInfoRsp_s {
1623 } agsaSetDeviceInfoRsp_t;
1625 /** \brief the data structure of SAS Re_Initialize Response
1627 * use to describe MPI SAS RE_INITIALIZE Response (64 bytes)
1630 typedef struct agsaSasReInitializeRsp_s {
1635 bit32 openRejReCmdData;
1638 } agsaSasReInitializeRsp_t;
1640 /** \brief the data structure of SGPIO Response
1642 * use to describe MPI serial GPIO Response IOMB (64 bytes)
1645 typedef struct agsaSGpioRsp_s {
1647 bit32 resultFunctionFrameType;
1648 bit32 readData[OSSA_SGPIO_MAX_READ_DATA_COUNT];
1652 /** \brief the data structure of PCIe diag response
1654 * use to describe PCIe diag response IOMB (64 bytes)
1658 typedef struct agsaPCIeDiagExecuteRsp_s {
1660 bit32 CmdTypeDesc; /* 2 */
1661 bit32 Status; /* 3 */
1662 bit32 reservedDW4; /* 4 */
1663 bit32 reservedDW5; /* 5 */
1664 bit32 ERR_BLKH; /* 6 */
1665 bit32 ERR_BLKL; /* 7 */
1666 bit32 DWord8; /* 8 */
1667 bit32 DWord9; /* 9 */
1668 bit32 DWord10; /* 10 */
1669 bit32 DWord11; /* 11 */
1670 bit32 DIF_ERR; /* 12 */
1671 bit32 reservedDW13; /* 13 */
1672 bit32 reservedDW14; /* 14 */
1673 bit32 reservedDW15; /* 15 */
1674 } agsaPCIeDiagExecuteRsp_t;
1676 /** \brief the data structure of PCI diag response
1678 * use to describe PCI diag response IOMB for SPC (64 bytes)
1682 typedef struct agsa_SPC_PCIeDiagExecuteRsp_s {
1684 bit32 CmdTypeDesc; /* 2 */
1685 bit32 Status; /* 3 */
1686 bit32 reserved[12]; /* 4 15 */
1687 } agsa_SPC_PCIeDiagExecuteRsp_t;
1689 /** \brief the data structure of GET DFE Data Response
1691 * use to describe GET DFE Data Response for SPCv (64 bytes)
1694 typedef struct agsaGetDDEFDataRsp_s {
1696 bit32 status; /* 2 */
1697 bit32 reserved_In_Ln;/* 3 */
1700 bit32 reserved[10]; /* 6 - 15 */
1701 } agsaGetDDEFDataRsp_t;
1703 /** \brief the data structure of GET Vis Data Response
1705 * use to describe GET Vis Data Response for SPCv (64 bytes)
1708 typedef struct agsaGetVHistCapRsp_s {
1710 bit32 status; /* 2 */
1711 bit32 channel; /* 3 */
1712 bit32 BistLo; /* 4 */
1713 bit32 BistHi; /* 5 */
1714 bit32 BytesXfered; /* 6 */
1715 bit32 PciLo; /* 7 */
1716 bit32 PciHi; /* 8 */
1717 bit32 PciBytecount; /* 9 */
1718 bit32 reserved[5]; /* 10 - 15 */
1719 } agsaGetVHistCapRsp_t;
1721 typedef struct agsaSetControllerConfigCmd_s {
1724 bit32 configPage[13]; /* Page code specific fields */
1725 } agsaSetControllerConfigCmd_t;
1728 typedef struct agsaSetControllerConfigRsp_s {
1731 bit32 errorQualifierPage;
1733 } agsaSetControllerConfigRsp_t;
1735 typedef struct agsaGetControllerConfigCmd_s {
1741 } agsaGetControllerConfigCmd_t;
1743 typedef struct agsaGetControllerConfigRsp_s {
1746 bit32 errorQualifier;
1747 bit32 configPage[12]; /* Page code specific fields */
1748 } agsaGetControllerConfigRsp_t;
1750 typedef struct agsaDekManagementCmd_s {
1752 bit32 KEKIDX_Reserved_TBLS_DSOP;
1757 bit32 Reserved_DBF_TBL_SIZE;
1758 } agsaDekManagementCmd_t;
1760 typedef struct agsaDekManagementRsp_s {
1765 bit32 errorQualifier;
1767 } agsaDekManagementRsp_t;
1769 typedef struct agsaKekManagementCmd_s {
1771 bit32 NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP;
1774 } agsaKekManagementCmd_t;
1776 typedef struct agsaKekManagementRsp_s {
1780 bit32 errorQualifier;
1782 } agsaKekManagementRsp_t;
1785 typedef struct agsaCoalSspComplCxt_s {
1789 } agsaCoalSspComplCxt_t;
1791 /** \brief the data structure of SSP Completion Response
1793 * use to describe MPI SSP Completion Response (1024 bytes)
1796 typedef struct agsaSSPCoalescedCompletionRsp_s {
1797 bit32 coalescedCount;
1798 agsaCoalSspComplCxt_t sspComplCxt[1]; /* Open ended array */
1799 } agsaSSPCoalescedCompletionRsp_t;
1802 /** \brief the data structure of SATA Completion Response
1804 * use to describe MPI SATA Completion Response (1024 bytes)
1807 typedef struct agsaCoalStpComplCxt_s {
1810 } agsaCoalStpComplCxt_t;
1812 typedef struct agsaSATACoalescedCompletionRsp_s {
1813 bit32 coalescedCount;
1814 agsaCoalStpComplCxt_t stpComplCxt[1]; /* Open ended array */
1815 } agsaSATACoalescedCompletionRsp_t;
1818 /** \brief the data structure of Operator Mangement Command
1820 * use to describe OPR_MGMT Command (128 bytes)
1823 typedef struct agsaOperatorMangmentCmd_s{
1825 bit32 OPRIDX_AUTIDX_R_KBF_PKT_OMO;/* 2 */
1826 bit8 IDString_Role[32]; /* 3 10 */
1827 #ifndef HAILEAH_HOST_6G_COMPITIBILITY_FLAG
1828 agsaEncryptKekBlob_t Kblob; /* 11 22 */
1830 bit32 reserved[8]; /* 23 31 */
1831 } agsaOperatorMangmentCmd_t;
1836 * use to describe OPR_MGMT Response (64 bytes)
1839 typedef struct agsaOperatorMangmentRsp_s {
1841 bit32 status; /* 2 */
1842 bit32 OPRIDX_AUTIDX_R_OMO; /* 3 */
1843 bit32 errorQualifier; /* 4 */
1844 bit32 reserved[10]; /* 5 15 */
1845 } agsaOperatorMangmenRsp_t;
1847 /** \brief the data structure of Set Operator Command
1849 * use to describe Set Operator Command (64 bytes)
1852 typedef struct agsaSetOperatorCmd_s{
1854 bit32 OPRIDX_PIN_ACS; /* 2 */
1855 bit32 cert[10]; /* 3 12 */
1856 bit32 reserved[3]; /* 13 15 */
1857 } agsaSetOperatorCmd_t;
1861 * use to describe Set Operator Response (64 bytes)
1864 typedef struct agsaSetOperatorRsp_s {
1866 bit32 status; /* 2 */
1867 bit32 ERR_QLFR_OPRIDX_PIN_ACS;/* 3 */
1868 bit32 reserved[12]; /* 4 15 */
1869 } agsaSetOperatorRsp_t;
1871 /** \brief the data structure of Get Operator Command
1873 * use to describe Get Operator Command (64 bytes)
1876 typedef struct agsaGetOperatorCmd_s{
1878 bit32 option; /* 2 */
1879 bit32 OprBufAddrLo; /* 3 */
1880 bit32 OprBufAddrHi; /* 4*/
1881 bit32 reserved[11]; /*5 15*/
1882 } agsaGetOperatorCmd_t;
1886 * use to describe Get Operator Response (64 bytes)
1889 typedef struct agsaGetOperatorRsp_s {
1891 bit32 status; /* 2 */
1892 bit32 Num_Option; /* 3 */
1893 bit32 IDString[8]; /* 4 11*/
1894 bit32 reserved[4]; /* 12 15*/
1895 } agsaGetOperatorRsp_t;
1899 * use to start Encryption BIST (128 bytes)
1902 typedef struct agsaEncryptBist_s {
1904 bit32 r_subop; /* 2 */
1905 bit32 testDiscption[28]; /* 3 31 */
1906 } agsaEncryptBist_t;
1910 * use to describe Encryption BIST Response (64 bytes)
1914 typedef struct agsaEncryptBistRsp_s {
1916 bit32 status; /* 2 */
1917 bit32 subop; /* 3 */
1918 bit32 testResults[11]; /* 4 15 */
1919 } agsaEncryptBistRsp_t;
1921 /** \brief the data structure of DifEncOffload Command
1923 * use to describe Set DifEncOffload Command (128 bytes)
1926 typedef struct agsaDifEncOffloadCmd_s{
1928 bit32 option; /* 2 */
1929 bit32 reserved[2]; /* 3-4 */
1930 bit32 Src_Data_Len; /* 5 */
1931 bit32 Dst_Data_Len; /* 6 */
1932 bit32 flags; /* 7 */
1933 bit32 UDTR01UDT01; /* 8 */
1934 bit32 UDT2345; /* 9 */
1935 bit32 UDTR2345; /* 10 */
1936 bit32 DPLR0SecCnt_IOSeed; /* 11 */
1937 bit32 DPL_Addr_Lo; /* 12 */
1938 bit32 DPL_Addr_Hi; /* 13 */
1939 bit32 KeyIndex_CMode_KTS_ENT_R; /* 14 */
1940 bit32 EPLR0SecCnt_KS_ENSS; /* 15 */
1941 bit32 keyTag_W0; /* 16 */
1942 bit32 keyTag_W1; /* 17 */
1943 bit32 tweakVal_W0; /* 18 */
1944 bit32 tweakVal_W1; /* 19 */
1945 bit32 tweakVal_W2; /* 20 */
1946 bit32 tweakVal_W3; /* 21 */
1947 bit32 EPL_Addr_Lo; /* 22 */
1948 bit32 EPL_Addr_Hi; /* 23 */
1949 agsaSgl_t SrcSgl; /* 24-27 */
1950 agsaSgl_t DstSgl; /* 28-31 */
1951 } agsaDifEncOffloadCmd_t;
1955 * use to describe DIF/Encryption Offload Response (32 bytes)
1958 typedef struct agsaDifEncOffloadRspV_s {
1961 bit32 ExpectedCRCUDT01;
1962 bit32 ExpectedUDT2345;
1963 bit32 ActualCRCUDT01;
1964 bit32 ActualUDT2345;
1967 } agsaDifEncOffloadRspV_t;
1969 #endif /*__SAMPIDEFS_H__ */