2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/mutex.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
53 #include <machine/vmparam.h>
54 #include <machine/pc/bios.h>
57 #include <dev/ppbus/ppbconf.h>
58 #include <dev/ppbus/ppb_msq.h>
60 #include <dev/ppc/ppcvar.h>
61 #include <dev/ppc/ppcreg.h>
65 static void ppcintr(void *arg);
67 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
68 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
70 #define LOG_PPC(function, ppc, string) \
71 if (bootverbose) printf("%s: %s\n", function, string)
73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
76 * We use critical enter/exit for the simple config locking needed to
77 * detect the devices. We just want to make sure that both of our writes
78 * happen without someone else also writing to those config registers. Since
79 * we just do this at startup, Giant keeps multiple threads from executing,
80 * and critical_enter() then is all that's needed to keep us from being preempted
81 * during the critical sequences with the hardware.
83 * Note: this doesn't prevent multiple threads from putting the chips into
84 * config mode, but since we only do that to detect the type at startup the
85 * extra overhead isn't needed since Giant protects us from multiple entry
86 * and no other code changes these registers.
88 #define PPC_CONFIG_LOCK(ppc) critical_enter()
89 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
91 devclass_t ppc_devclass;
92 const char ppc_driver_name[] = "ppc";
94 static char *ppc_models[] = {
95 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
96 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
97 "SMC FDC37C935", "PC87303", 0
100 /* list of available modes */
101 static char *ppc_avms[] = {
102 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
103 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
104 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
105 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
108 /* list of current executing modes
109 * Note that few modes do not actually exist.
111 static char *ppc_modes[] = {
112 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
113 "EPP", "EPP", "EPP", "ECP",
114 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
115 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
118 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
122 * BIOS printer list - used by BIOS probe.
124 #define BIOS_PPC_PORTS 0x408
125 #define BIOS_PORTS ((short *)BIOS_PADDRTOVADDR(BIOS_PPC_PORTS))
126 #define BIOS_MAX_PPC 4
133 ppc_ecp_sync(device_t dev)
136 struct ppc_data *ppc = DEVTOSOFTC(dev);
138 PPC_ASSERT_LOCKED(ppc);
139 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
143 if ((r & 0xe0) != PPC_ECR_EPP)
146 for (i = 0; i < 100; i++) {
153 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
161 * Detect parallel port FIFO
164 ppc_detect_fifo(struct ppc_data *ppc)
167 char ctr_sav, ctr, cc;
171 ecr_sav = r_ecr(ppc);
172 ctr_sav = r_ctr(ppc);
174 /* enter ECP configuration mode, no interrupt, no DMA */
177 /* read PWord size - transfers in FIFO mode must be PWord aligned */
178 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
180 /* XXX 16 and 32 bits implementations not supported */
181 if (ppc->ppc_pword != PPC_PWORD_8) {
182 LOG_PPC(__func__, ppc, "PWord not supported");
186 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
188 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
190 /* enter ECP test mode, no interrupt, no DMA */
194 for (i=0; i<1024; i++) {
195 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
201 LOG_PPC(__func__, ppc, "can't flush FIFO");
205 /* enable interrupts, no DMA */
208 /* determine readIntrThreshold
209 * fill the FIFO until serviceIntr is set
211 for (i=0; i<1024; i++) {
212 w_fifo(ppc, (char)i);
213 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
214 /* readThreshold reached */
217 if (r_ecr(ppc) & PPC_FIFO_FULL) {
224 LOG_PPC(__func__, ppc, "can't fill FIFO");
228 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
229 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
230 w_ecr(ppc, 0xd0); /* enable interrupts */
232 /* determine writeIntrThreshold
233 * empty the FIFO until serviceIntr is set
235 for (i=ppc->ppc_fifo; i>0; i--) {
236 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
237 LOG_PPC(__func__, ppc, "invalid data in FIFO");
240 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
241 /* writeIntrThreshold reached */
242 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
244 /* if FIFO empty before the last byte, error */
245 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
246 LOG_PPC(__func__, ppc, "data lost in FIFO");
251 /* FIFO must be empty after the last byte */
252 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
253 LOG_PPC(__func__, ppc, "can't empty the FIFO");
270 ppc_detect_port(struct ppc_data *ppc)
273 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
275 if (r_dtr(ppc) != 0xaa)
282 * EPP timeout, according to the PC87332 manual
283 * Semantics of clearing EPP timeout bit.
284 * PC87332 - reading SPP_STR does it...
285 * SMC - write 1 to EPP timeout bit XXX
286 * Others - (?) write 0 to EPP timeout bit
289 ppc_reset_epp_timeout(struct ppc_data *ppc)
295 w_str(ppc, r & 0xfe);
301 ppc_check_epp_timeout(struct ppc_data *ppc)
303 ppc_reset_epp_timeout(ppc);
305 return (!(r_str(ppc) & TIMEOUT));
309 * Configure current operating mode
312 ppc_generic_setmode(struct ppc_data *ppc, int mode)
316 /* check if mode is available */
317 if (mode && !(ppc->ppc_avm & mode))
320 /* if ECP mode, configure ecr register */
321 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
322 /* return to byte mode (keeping direction bit),
323 * no interrupt, no DMA to be able to change to
326 w_ecr(ppc, PPC_ECR_RESET);
327 ecr = PPC_DISABLE_INTR;
331 else if (mode & PPB_ECP)
332 /* select ECP mode */
334 else if (mode & PPB_PS2)
335 /* select PS2 mode with ECP */
338 /* select COMPATIBLE/NIBBLE mode */
344 ppc->ppc_mode = mode;
350 * The ppc driver is free to choose options like FIFO or DMA
351 * if ECP mode is available.
353 * The 'RAW' option allows the upper drivers to force the ppc mode
354 * even with FIFO, DMA available.
357 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
361 /* check if mode is available */
362 if (mode && !(ppc->ppc_avm & mode))
365 /* if ECP mode, configure ecr register */
366 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
367 /* return to byte mode (keeping direction bit),
368 * no interrupt, no DMA to be able to change to
371 w_ecr(ppc, PPC_ECR_RESET);
372 ecr = PPC_DISABLE_INTR;
375 /* select EPP mode */
377 else if (mode & PPB_ECP)
378 /* select ECP mode */
380 else if (mode & PPB_PS2)
381 /* select PS2 mode with ECP */
384 /* select COMPATIBLE/NIBBLE mode */
390 ppc->ppc_mode = mode;
395 #ifdef PPC_PROBE_CHIPSET
399 * Probe for a Natsemi PC873xx-family part.
401 * References in this function are to the National Semiconductor
402 * PC87332 datasheet TL/C/11930, May 1995 revision.
404 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
405 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
406 static int pc873xx_irqtab[] = {5, 7, 5, 0};
408 static int pc873xx_regstab[] = {
409 PC873_FER, PC873_FAR, PC873_PTR,
410 PC873_FCR, PC873_PCR, PC873_PMC,
411 PC873_TUP, PC873_SID, PC873_PNP0,
412 PC873_PNP1, PC873_LPTBA, -1
415 static char *pc873xx_rnametab[] = {
416 "FER", "FAR", "PTR", "FCR", "PCR",
417 "PMC", "TUP", "SID", "PNP0", "PNP1",
422 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
424 static int index = 0;
426 int ptr, pcr, val, i;
428 while ((idport = pc873xx_basetab[index++])) {
429 /* XXX should check first to see if this location is already claimed */
432 * Pull the 873xx through the power-on ID cycle (2.2,1.).
433 * We can't use this to locate the chip as it may already have
434 * been used by the BIOS.
436 (void)inb(idport); (void)inb(idport);
437 (void)inb(idport); (void)inb(idport);
440 * Read the SID byte. Possible values are :
447 outb(idport, PC873_SID);
448 val = inb(idport + 1);
449 if ((val & 0xf0) == 0x10) {
450 ppc->ppc_model = NS_PC87332;
451 } else if ((val & 0xf8) == 0x70) {
452 ppc->ppc_model = NS_PC87306;
453 } else if ((val & 0xf8) == 0x50) {
454 ppc->ppc_model = NS_PC87334;
455 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
456 documentation, but probing
458 ppc->ppc_model = NS_PC87303;
460 if (bootverbose && (val != 0xff))
461 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
462 continue ; /* not recognised */
465 /* print registers */
468 for (i=0; pc873xx_regstab[i] != -1; i++) {
469 outb(idport, pc873xx_regstab[i]);
470 printf(" %s=0x%x", pc873xx_rnametab[i],
471 inb(idport + 1) & 0xff);
477 * We think we have one. Is it enabled and where we want it to be?
479 outb(idport, PC873_FER);
480 val = inb(idport + 1);
481 if (!(val & PC873_PPENABLE)) {
483 printf("PC873xx parallel port disabled\n");
486 outb(idport, PC873_FAR);
487 val = inb(idport + 1);
488 /* XXX we should create a driver instance for every port found */
489 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
490 /* First try to change the port address to that requested... */
492 switch (ppc->ppc_base) {
510 outb(idport, PC873_FAR);
511 outb(idport + 1, val);
512 outb(idport + 1, val);
514 /* Check for success by reading back the value we supposedly
515 wrote and comparing...*/
517 outb(idport, PC873_FAR);
518 val = inb(idport + 1) & 0x3;
520 /* If we fail, report the failure... */
522 if (pc873xx_porttab[val] != ppc->ppc_base) {
524 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
525 pc873xx_porttab[val], ppc->ppc_base);
530 outb(idport, PC873_PTR);
531 ptr = inb(idport + 1);
533 /* get irq settings */
534 if (ppc->ppc_base == 0x378)
535 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
537 irq = pc873xx_irqtab[val];
540 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
543 * Check if irq settings are correct
545 if (irq != ppc->ppc_irq) {
547 * If the chipset is not locked and base address is 0x378,
548 * we have another chance
550 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
551 if (ppc->ppc_irq == 7) {
552 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
553 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
555 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
556 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
559 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
562 printf("PC873xx sorry, can't change irq setting\n");
566 printf("PC873xx irq settings are correct\n");
569 outb(idport, PC873_PCR);
570 pcr = inb(idport + 1);
572 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
574 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
576 ppc->ppc_avm |= PPB_NIBBLE;
580 if (pcr & PC873_EPPEN) {
581 ppc->ppc_avm |= PPB_EPP;
586 if (pcr & PC873_EPP19)
587 ppc->ppc_epp = EPP_1_9;
589 ppc->ppc_epp = EPP_1_7;
591 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
592 outb(idport, PC873_PTR);
593 ptr = inb(idport + 1);
594 if (ptr & PC873_EPPRDIR)
595 printf(", Regular mode");
597 printf(", Automatic mode");
599 } else if (pcr & PC873_ECPEN) {
600 ppc->ppc_avm |= PPB_ECP;
604 if (pcr & PC873_ECPCLK) { /* XXX */
605 ppc->ppc_avm |= PPB_PS2;
610 outb(idport, PC873_PTR);
611 ptr = inb(idport + 1);
612 if (ptr & PC873_EXTENDED) {
613 ppc->ppc_avm |= PPB_SPP;
620 printf("PC873xx unlocked");
622 if (chipset_mode & PPB_ECP) {
623 if ((chipset_mode & PPB_EPP) && bootverbose)
624 printf(", ECP+EPP not supported");
627 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
628 outb(idport + 1, pcr);
629 outb(idport + 1, pcr);
634 } else if (chipset_mode & PPB_EPP) {
635 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
636 pcr |= (PC873_EPPEN | PC873_EPP19);
637 outb(idport + 1, pcr);
638 outb(idport + 1, pcr);
640 ppc->ppc_epp = EPP_1_9; /* XXX */
645 /* enable automatic direction turnover */
646 if (ppc->ppc_model == NS_PC87332) {
647 outb(idport, PC873_PTR);
648 ptr = inb(idport + 1);
649 ptr &= ~PC873_EPPRDIR;
650 outb(idport + 1, ptr);
651 outb(idport + 1, ptr);
654 printf(", Automatic mode");
657 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
658 outb(idport + 1, pcr);
659 outb(idport + 1, pcr);
661 /* configure extended bit in PTR */
662 outb(idport, PC873_PTR);
663 ptr = inb(idport + 1);
665 if (chipset_mode & PPB_PS2) {
666 ptr |= PC873_EXTENDED;
672 /* default to NIBBLE mode */
673 ptr &= ~PC873_EXTENDED;
678 outb(idport + 1, ptr);
679 outb(idport + 1, ptr);
682 ppc->ppc_avm = chipset_mode;
688 ppc->ppc_type = PPC_TYPE_GENERIC;
689 ppc_generic_setmode(ppc, chipset_mode);
691 return(chipset_mode);
697 * ppc_smc37c66xgt_detect
699 * SMC FDC37C66xGT configuration.
702 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
707 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
709 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
711 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
714 * Detection: enter configuration mode and read CRD register.
716 PPC_CONFIG_LOCK(ppc);
717 outb(csr, SMC665_iCODE);
718 outb(csr, SMC665_iCODE);
719 PPC_CONFIG_UNLOCK(ppc);
722 if (inb(cio) == 0x65) {
727 for (i = 0; i < 2; i++) {
728 PPC_CONFIG_LOCK(ppc);
729 outb(csr, SMC666_iCODE);
730 outb(csr, SMC666_iCODE);
731 PPC_CONFIG_UNLOCK(ppc);
734 if (inb(cio) == 0x66) {
739 /* Another chance, CSR may be hard-configured to be at 0x370 */
745 * If chipset not found, do not continue.
748 outb(csr, 0xaa); /* end config mode */
755 /* read the port's address: bits 0 and 1 of CR1 */
756 r = inb(cio) & SMC_CR1_ADDR;
757 if (port_address[(int)r] != ppc->ppc_base) {
758 outb(csr, 0xaa); /* end config mode */
762 ppc->ppc_model = type;
765 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
766 * If SPP mode is detected, try to set ECP+EPP mode
771 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
775 printf(" CR4=0x%x", inb(cio) & 0xff);
782 /* autodetect mode */
784 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
785 if (type == SMC_37C666GT) {
786 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
788 printf(" configuration hardwired, supposing " \
792 if ((inb(cio) & SMC_CR1_MODE) == 0) {
793 /* already in extended parallel port mode, read CR4 */
795 r = (inb(cio) & SMC_CR4_EMODE);
799 ppc->ppc_avm |= PPB_SPP;
805 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
811 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
817 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
819 printf(" ECP+EPP SPP");
823 /* not an extended port mode */
824 ppc->ppc_avm |= PPB_SPP;
831 ppc->ppc_avm = chipset_mode;
833 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
834 if (type == SMC_37C666GT)
838 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
839 /* do not use ECP when the mode is not forced to */
840 outb(cio, r | SMC_CR1_MODE);
844 /* an extended mode is selected */
845 outb(cio, r & ~SMC_CR1_MODE);
847 /* read CR4 register and reset mode field */
849 r = inb(cio) & ~SMC_CR4_EMODE;
851 if (chipset_mode & PPB_ECP) {
852 if (chipset_mode & PPB_EPP) {
853 outb(cio, r | SMC_ECPEPP);
857 outb(cio, r | SMC_ECP);
863 outb(cio, r | SMC_EPPSPP);
868 ppc->ppc_avm = chipset_mode;
871 /* set FIFO threshold to 16 */
872 if (ppc->ppc_avm & PPB_ECP) {
883 if (ppc->ppc_avm & PPB_EPP) {
889 * Set the EPP protocol...
890 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
892 if (ppc->ppc_epp == EPP_1_9)
893 outb(cio, (r & ~SMC_CR4_EPPTYPE));
895 outb(cio, (r | SMC_CR4_EPPTYPE));
898 outb(csr, 0xaa); /* end config mode */
900 ppc->ppc_type = PPC_TYPE_SMCLIKE;
901 ppc_smclike_setmode(ppc, chipset_mode);
903 return (chipset_mode);
907 * SMC FDC37C935 configuration
908 * Found on many Alpha machines
911 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
915 PPC_CONFIG_LOCK(ppc);
916 outb(SMC935_CFG, 0x55); /* enter config mode */
917 outb(SMC935_CFG, 0x55);
918 PPC_CONFIG_UNLOCK(ppc);
920 outb(SMC935_IND, SMC935_ID); /* check device id */
921 if (inb(SMC935_DAT) == 0x2)
925 outb(SMC935_CFG, 0xaa); /* exit config mode */
929 ppc->ppc_model = type;
931 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
932 outb(SMC935_DAT, 3); /* which is logical device 3 */
934 /* set io port base */
935 outb(SMC935_IND, SMC935_PORTHI);
936 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
937 outb(SMC935_IND, SMC935_PORTLO);
938 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
941 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
943 ppc->ppc_avm = chipset_mode;
944 outb(SMC935_IND, SMC935_PPMODE);
945 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
947 /* SPP + EPP or just plain SPP */
948 if (chipset_mode & (PPB_SPP)) {
949 if (chipset_mode & PPB_EPP) {
950 if (ppc->ppc_epp == EPP_1_9) {
951 outb(SMC935_IND, SMC935_PPMODE);
952 outb(SMC935_DAT, SMC935_EPP19SPP);
954 if (ppc->ppc_epp == EPP_1_7) {
955 outb(SMC935_IND, SMC935_PPMODE);
956 outb(SMC935_DAT, SMC935_EPP17SPP);
959 outb(SMC935_IND, SMC935_PPMODE);
960 outb(SMC935_DAT, SMC935_SPP);
964 /* ECP + EPP or just plain ECP */
965 if (chipset_mode & PPB_ECP) {
966 if (chipset_mode & PPB_EPP) {
967 if (ppc->ppc_epp == EPP_1_9) {
968 outb(SMC935_IND, SMC935_PPMODE);
969 outb(SMC935_DAT, SMC935_ECPEPP19);
971 if (ppc->ppc_epp == EPP_1_7) {
972 outb(SMC935_IND, SMC935_PPMODE);
973 outb(SMC935_DAT, SMC935_ECPEPP17);
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_ECP);
982 outb(SMC935_CFG, 0xaa); /* exit config mode */
984 ppc->ppc_type = PPC_TYPE_SMCLIKE;
985 ppc_smclike_setmode(ppc, chipset_mode);
987 return (chipset_mode);
991 * Winbond W83877F stuff
993 * EFER: extended function enable register
994 * EFIR: extended function index register
995 * EFDR: extended function data register
997 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
998 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1000 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1001 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1002 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1003 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1006 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1009 unsigned char r, hefere, hefras;
1011 for (i = 0; i < 4; i ++) {
1012 /* first try to enable configuration registers */
1013 efer = w83877f_efers[i];
1015 /* write the key to the EFER */
1016 for (j = 0; j < w83877f_keyiter[i]; j ++)
1017 outb (efer, w83877f_keys[i]);
1019 /* then check HEFERE and HEFRAS bits */
1021 hefere = inb(efdr) & WINB_HEFERE;
1024 hefras = inb(efdr) & WINB_HEFRAS;
1028 * 0 1 write 89h to 250h (power-on default)
1029 * 1 0 write 86h twice to 3f0h
1030 * 1 1 write 87h twice to 3f0h
1031 * 0 0 write 88h to 250h
1033 if ((hefere | hefras) == w83877f_hefs[i])
1037 return (-1); /* failed */
1040 /* check base port address - read from CR23 */
1042 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1045 /* read CHIP ID from CR9/bits0-3 */
1048 switch (inb(efdr) & WINB_CHIPID) {
1049 case WINB_W83877F_ID:
1050 ppc->ppc_model = WINB_W83877F;
1053 case WINB_W83877AF_ID:
1054 ppc->ppc_model = WINB_W83877AF;
1058 ppc->ppc_model = WINB_UNKNOWN;
1062 /* dump of registers */
1063 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1064 for (i = 0; i <= 0xd; i ++) {
1066 printf("0x%x ", inb(efdr));
1068 for (i = 0x10; i <= 0x17; i ++) {
1070 printf("0x%x ", inb(efdr));
1073 printf("0x%x ", inb(efdr));
1074 for (i = 0x20; i <= 0x29; i ++) {
1076 printf("0x%x ", inb(efdr));
1081 ppc->ppc_type = PPC_TYPE_GENERIC;
1083 if (!chipset_mode) {
1084 /* autodetect mode */
1088 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1092 r |= (inb(efdr) & WINB_PRTMODS2);
1097 device_printf(ppc->ppc_dev,
1098 "W83757 compatible mode\n");
1099 return (-1); /* generic or SMC-like */
1106 device_printf(ppc->ppc_dev,
1107 "not in parallel port mode\n");
1110 case (WINB_PARALLEL | WINB_EPP_SPP):
1111 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1113 device_printf(ppc->ppc_dev, "EPP SPP\n");
1116 case (WINB_PARALLEL | WINB_ECP):
1117 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1119 device_printf(ppc->ppc_dev, "ECP SPP\n");
1122 case (WINB_PARALLEL | WINB_ECP_EPP):
1123 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1124 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1127 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1130 printf("%s: unknown case (0x%x)!\n", __func__, r);
1136 /* select CR9 and set PRTMODS2 bit */
1138 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1140 /* select CR0 and reset PRTMODSx bits */
1142 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1144 if (chipset_mode & PPB_ECP) {
1145 if (chipset_mode & PPB_EPP) {
1146 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1148 device_printf(ppc->ppc_dev,
1151 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1154 outb(efdr, inb(efdr) | WINB_ECP);
1156 device_printf(ppc->ppc_dev, "ECP\n");
1159 /* select EPP_SPP otherwise */
1160 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1162 device_printf(ppc->ppc_dev, "EPP SPP\n");
1164 ppc->ppc_avm = chipset_mode;
1167 /* exit configuration mode */
1170 switch (ppc->ppc_type) {
1171 case PPC_TYPE_SMCLIKE:
1172 ppc_smclike_setmode(ppc, chipset_mode);
1175 ppc_generic_setmode(ppc, chipset_mode);
1179 return (chipset_mode);
1184 * ppc_generic_detect
1187 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1189 /* default to generic */
1190 ppc->ppc_type = PPC_TYPE_GENERIC;
1193 device_printf(ppc->ppc_dev, "SPP");
1195 /* first, check for ECP */
1196 w_ecr(ppc, PPC_ECR_PS2);
1197 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1198 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1202 /* search for SMC style ECP+EPP mode */
1203 w_ecr(ppc, PPC_ECR_EPP);
1206 /* try to reset EPP timeout bit */
1207 if (ppc_check_epp_timeout(ppc)) {
1208 ppc->ppc_dtm |= PPB_EPP;
1210 if (ppc->ppc_dtm & PPB_ECP) {
1211 /* SMC like chipset found */
1212 ppc->ppc_model = SMC_LIKE;
1213 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1222 /* restore to standard mode */
1223 w_ecr(ppc, PPC_ECR_STD);
1226 /* XXX try to detect NIBBLE and PS2 modes */
1227 ppc->ppc_dtm |= PPB_NIBBLE;
1230 ppc->ppc_avm = chipset_mode;
1232 ppc->ppc_avm = ppc->ppc_dtm;
1237 switch (ppc->ppc_type) {
1238 case PPC_TYPE_SMCLIKE:
1239 ppc_smclike_setmode(ppc, chipset_mode);
1242 ppc_generic_setmode(ppc, chipset_mode);
1246 return (chipset_mode);
1252 * mode is the mode suggested at boot
1255 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1256 #ifdef PPC_PROBE_CHIPSET
1259 /* list of supported chipsets */
1260 int (*chipset_detect[])(struct ppc_data *, int) = {
1262 ppc_smc37c66xgt_detect,
1264 ppc_smc37c935_detect,
1270 /* if can't find the port and mode not forced return error */
1271 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1272 return (EIO); /* failed, port not present */
1274 /* assume centronics compatible mode is supported */
1275 ppc->ppc_avm = PPB_COMPATIBLE;
1277 #ifdef PPC_PROBE_CHIPSET
1278 /* we have to differenciate available chipset modes,
1279 * chipset running modes and IEEE-1284 operating modes
1281 * after detection, the port must support running in compatible mode
1283 if (ppc->ppc_flags & 0x40) {
1285 printf("ppc: chipset forced to generic\n");
1288 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1290 #ifdef PPC_PROBE_CHIPSET
1292 for (i=0; chipset_detect[i] != NULL; i++) {
1293 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1294 ppc->ppc_mode = mode;
1301 /* configure/detect ECP FIFO */
1302 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1303 ppc_detect_fifo(ppc);
1309 * ppc_exec_microseq()
1311 * Execute a microsequence.
1312 * Microsequence mechanism is supposed to handle fast I/O operations.
1315 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1317 struct ppc_data *ppc = DEVTOSOFTC(dev);
1318 struct ppb_microseq *mi;
1328 struct ppb_microseq *stack = NULL;
1330 /* microsequence registers are equivalent to PC-like port registers */
1332 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1333 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1335 #define INCR_PC (mi ++) /* increment program counter */
1337 PPC_ASSERT_LOCKED(ppc);
1340 switch (mi->opcode) {
1342 cc = r_reg(mi->arg[0].i, ppc);
1343 cc &= (char)mi->arg[2].i; /* clear mask */
1344 cc |= (char)mi->arg[1].i; /* assert mask */
1345 w_reg(mi->arg[0].i, ppc, cc);
1349 case MS_OP_RASSERT_P:
1353 if ((len = mi->arg[0].i) == MS_ACCUM) {
1354 accum = ppc->ppc_accum;
1355 for (; accum; accum--)
1356 w_reg(reg, ppc, *ptr++);
1357 ppc->ppc_accum = accum;
1359 for (i=0; i<len; i++)
1360 w_reg(reg, ppc, *ptr++);
1366 case MS_OP_RFETCH_P:
1368 mask = (char)mi->arg[2].i;
1371 if ((len = mi->arg[0].i) == MS_ACCUM) {
1372 accum = ppc->ppc_accum;
1373 for (; accum; accum--)
1374 *ptr++ = r_reg(reg, ppc) & mask;
1375 ppc->ppc_accum = accum;
1377 for (i=0; i<len; i++)
1378 *ptr++ = r_reg(reg, ppc) & mask;
1385 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1393 /* let's suppose the next instr. is the same */
1395 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1396 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1398 if (mi->opcode == MS_OP_DELAY) {
1399 DELAY(mi->arg[0].i);
1408 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1416 iter = mi->arg[1].i;
1417 p = (char *)mi->arg[2].p;
1419 /* XXX delay limited to 255 us */
1420 for (i=0; i<iter; i++) {
1421 w_reg(reg, ppc, *p++);
1422 DELAY((unsigned char)*p++);
1428 ppc->ppc_accum = mi->arg[0].i;
1433 if (--ppc->ppc_accum > 0)
1440 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1447 if ((cc & (char)mi->arg[0].i) == 0)
1454 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1462 * If the C call returns !0 then end the microseq.
1463 * The current state of ptr is passed to the C function
1465 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1472 ppc->ppc_ptr = (char *)mi->arg[0].p;
1478 panic("%s: too much calls", __func__);
1481 /* store the state of the actual
1486 /* jump to the new microsequence */
1487 mi = (struct ppb_microseq *)mi->arg[0].p;
1494 /* retrieve microseq and pc state before the call */
1497 /* reset the stack */
1500 /* XXX return code */
1508 /* can't return to ppb level during the execution
1509 * of a submicrosequence */
1511 panic("%s: can't return to ppb level",
1514 /* update pc for ppb level of execution */
1517 /* return to ppb level of execution */
1521 panic("%s: unknown microsequence opcode 0x%x",
1522 __func__, mi->opcode);
1532 struct ppc_data *ppc = arg;
1533 u_char ctr, ecr, str;
1536 * If we have any child interrupt handlers registered, let
1537 * them handle this interrupt.
1539 * XXX: If DMA is in progress should we just complete that w/o
1543 if (ppc->ppc_intr_hook != NULL &&
1544 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1553 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1554 printf("![%x/%x/%x]", ctr, ecr, str);
1557 /* don't use ecp mode with IRQENABLE set */
1558 if (ctr & IRQENABLE) {
1563 /* interrupts are generated by nFault signal
1564 * only in ECP mode */
1565 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1566 /* check if ppc driver has programmed the
1567 * nFault interrupt */
1568 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1569 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1570 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1572 /* shall be handled by underlying layers XXX */
1578 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1579 /* disable interrupts (should be done by hardware though) */
1580 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1581 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1584 /* check if DMA completed */
1585 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1590 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1593 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1597 ppc->ppc_dmadone(ppc);
1598 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1600 /* wakeup the waiting process */
1604 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1605 /* classic interrupt I/O */
1606 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1614 ppc_read(device_t dev, char *buf, int len, int mode)
1620 ppc_write(device_t dev, char *buf, int len, int how)
1626 ppc_reset_epp(device_t dev)
1628 struct ppc_data *ppc = DEVTOSOFTC(dev);
1630 PPC_ASSERT_LOCKED(ppc);
1631 ppc_reset_epp_timeout(ppc);
1637 ppc_setmode(device_t dev, int mode)
1639 struct ppc_data *ppc = DEVTOSOFTC(dev);
1641 PPC_ASSERT_LOCKED(ppc);
1642 switch (ppc->ppc_type) {
1643 case PPC_TYPE_SMCLIKE:
1644 return (ppc_smclike_setmode(ppc, mode));
1647 case PPC_TYPE_GENERIC:
1649 return (ppc_generic_setmode(ppc, mode));
1658 ppc_probe(device_t dev, int rid)
1661 static short next_bios_ppc = 0;
1663 struct ppc_data *ppc;
1668 * Allocate the ppc_data structure.
1670 ppc = DEVTOSOFTC(dev);
1671 bzero(ppc, sizeof(struct ppc_data));
1673 ppc->rid_ioport = rid;
1675 /* retrieve ISA parameters */
1676 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1680 * If port not specified, use bios list.
1683 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1684 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1685 port = *(BIOS_PORTS + next_bios_ppc++);
1688 "parallel port found at 0x%jx\n", port);
1690 device_printf(dev, "parallel port not found.\n");
1693 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1694 IO_LPTSIZE_EXTENDED);
1698 /* IO port is mandatory */
1700 /* Try "extended" IO port range...*/
1701 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1703 IO_LPTSIZE_EXTENDED,
1706 if (ppc->res_ioport != 0) {
1708 device_printf(dev, "using extended I/O port range\n");
1710 /* Failed? If so, then try the "normal" IO port range... */
1711 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1716 if (ppc->res_ioport != 0) {
1718 device_printf(dev, "using normal I/O port range\n");
1721 device_printf(dev, "cannot reserve I/O port range\n");
1726 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1728 ppc->ppc_flags = device_get_flags(dev);
1730 if (!(ppc->ppc_flags & 0x20)) {
1731 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1734 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1740 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1742 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1745 ppc->ppc_model = GENERIC;
1747 ppc->ppc_mode = PPB_COMPATIBLE;
1748 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1750 ppc->ppc_type = PPC_TYPE_GENERIC;
1753 * Try to detect the chipset and its mode.
1755 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1761 if (ppc->res_irq != 0) {
1762 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1765 if (ppc->res_ioport != 0) {
1766 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1769 if (ppc->res_drq != 0) {
1770 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1777 ppc_attach(device_t dev)
1779 struct ppc_data *ppc = DEVTOSOFTC(dev);
1782 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1784 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1785 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1786 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1787 ppc_epp_protocol[ppc->ppc_epp] : "");
1790 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1791 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1794 /* default to the tty mask for registration */ /* XXX */
1795 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1796 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1799 "failed to register interrupt handler: %d\n",
1801 mtx_destroy(&ppc->ppc_lock);
1806 /* add ppbus as a child of this isa to parallel bridge */
1807 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1810 * Probe the ppbus and attach devices found.
1812 device_probe_and_attach(ppc->ppbus);
1818 ppc_detach(device_t dev)
1820 struct ppc_data *ppc = DEVTOSOFTC(dev);
1822 if (ppc->res_irq == 0) {
1826 /* detach & delete all children */
1827 device_delete_children(dev);
1829 if (ppc->res_irq != 0) {
1830 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1831 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1834 if (ppc->res_ioport != 0) {
1835 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1838 if (ppc->res_drq != 0) {
1839 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1843 mtx_destroy(&ppc->ppc_lock);
1849 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1851 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1853 PPC_ASSERT_LOCKED(ppc);
1856 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1859 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1862 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1865 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1868 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1871 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1874 return (r_dtr(ppc));
1876 return (r_str(ppc));
1878 return (r_ctr(ppc));
1880 return (r_epp_A(ppc));
1882 return (r_epp_D(ppc));
1884 return (r_ecr(ppc));
1886 return (r_fifo(ppc));
1909 panic("%s: unknown I/O operation", __func__);
1913 return (0); /* not significative */
1917 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1919 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1922 case PPC_IVAR_EPP_PROTO:
1923 PPC_ASSERT_LOCKED(ppc);
1924 *val = (u_long)ppc->ppc_epp;
1927 *val = (uintptr_t)&ppc->ppc_lock;
1937 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1939 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1942 case PPC_IVAR_INTR_HANDLER:
1943 PPC_ASSERT_LOCKED(ppc);
1944 if (dev != ppc->ppbus)
1947 ppc->ppc_intr_hook = NULL;
1950 if (ppc->ppc_intr_hook != NULL)
1952 ppc->ppc_intr_hook = (void *)val;
1953 ppc->ppc_intr_arg = device_get_softc(dev);
1963 * We allow child devices to allocate an IRQ resource at rid 0 for their
1964 * interrupt handlers.
1967 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1968 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1970 struct ppc_data *ppc = DEVTOSOFTC(bus);
1975 return (ppc->res_irq);
1982 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1986 struct ppc_data *ppc = DEVTOSOFTC(bus);
1992 KASSERT(r == ppc->res_irq,
1993 ("ppc child IRQ resource mismatch"));
2001 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);