2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
38 #include <sys/malloc.h>
42 #include <machine/clock.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/vmparam.h>
48 #include <isa/isareg.h>
49 #include <isa/isavar.h>
51 #include <dev/ppbus/ppbconf.h>
52 #include <dev/ppbus/ppb_msq.h>
54 #include <dev/ppc/ppcvar.h>
55 #include <dev/ppc/ppcreg.h>
59 static int ppc_isa_probe(device_t dev);
61 static void ppcintr(void *arg);
63 #define LOG_PPC(function, ppc, string) \
64 if (bootverbose) printf("%s: %s\n", function, string)
67 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
69 devclass_t ppc_devclass;
71 static device_method_t ppc_methods[] = {
72 /* device interface */
73 DEVMETHOD(device_probe, ppc_isa_probe),
74 DEVMETHOD(device_attach, ppc_attach),
77 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
78 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
79 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
80 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
83 DEVMETHOD(ppbus_io, ppc_io),
84 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
85 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
86 DEVMETHOD(ppbus_setmode, ppc_setmode),
87 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
88 DEVMETHOD(ppbus_read, ppc_read),
89 DEVMETHOD(ppbus_write, ppc_write),
94 static driver_t ppc_driver = {
97 sizeof(struct ppc_data),
100 static char *ppc_models[] = {
101 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
102 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
103 "SMC FDC37C935", "PC87303", 0
106 /* list of available modes */
107 static char *ppc_avms[] = {
108 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
109 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
110 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
111 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
114 /* list of current executing modes
115 * Note that few modes do not actually exist.
117 static char *ppc_modes[] = {
118 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
119 "EPP", "EPP", "EPP", "ECP",
120 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
121 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
124 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
128 * BIOS printer list - used by BIOS probe.
130 #define BIOS_PPC_PORTS 0x408
131 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
132 #define BIOS_MAX_PPC 4
139 ppc_ecp_sync(device_t dev) {
142 struct ppc_data *ppc = DEVTOSOFTC(dev);
144 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
148 if ((r & 0xe0) != PPC_ECR_EPP)
151 for (i = 0; i < 100; i++) {
158 printf("ppc%d: ECP sync failed as data still " \
159 "present in FIFO.\n", ppc->ppc_unit);
167 * Detect parallel port FIFO
170 ppc_detect_fifo(struct ppc_data *ppc)
173 char ctr_sav, ctr, cc;
177 ecr_sav = r_ecr(ppc);
178 ctr_sav = r_ctr(ppc);
180 /* enter ECP configuration mode, no interrupt, no DMA */
183 /* read PWord size - transfers in FIFO mode must be PWord aligned */
184 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
186 /* XXX 16 and 32 bits implementations not supported */
187 if (ppc->ppc_pword != PPC_PWORD_8) {
188 LOG_PPC(__func__, ppc, "PWord not supported");
192 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
194 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
196 /* enter ECP test mode, no interrupt, no DMA */
200 for (i=0; i<1024; i++) {
201 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
207 LOG_PPC(__func__, ppc, "can't flush FIFO");
211 /* enable interrupts, no DMA */
214 /* determine readIntrThreshold
215 * fill the FIFO until serviceIntr is set
217 for (i=0; i<1024; i++) {
218 w_fifo(ppc, (char)i);
219 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
220 /* readThreshold reached */
223 if (r_ecr(ppc) & PPC_FIFO_FULL) {
230 LOG_PPC(__func__, ppc, "can't fill FIFO");
234 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
235 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
236 w_ecr(ppc, 0xd0); /* enable interrupts */
238 /* determine writeIntrThreshold
239 * empty the FIFO until serviceIntr is set
241 for (i=ppc->ppc_fifo; i>0; i--) {
242 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
243 LOG_PPC(__func__, ppc, "invalid data in FIFO");
246 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
247 /* writeIntrThreshold reached */
248 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
250 /* if FIFO empty before the last byte, error */
251 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
252 LOG_PPC(__func__, ppc, "data lost in FIFO");
257 /* FIFO must be empty after the last byte */
258 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
259 LOG_PPC(__func__, ppc, "can't empty the FIFO");
276 ppc_detect_port(struct ppc_data *ppc)
279 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
281 if (r_dtr(ppc) != 0xaa)
288 * EPP timeout, according to the PC87332 manual
289 * Semantics of clearing EPP timeout bit.
290 * PC87332 - reading SPP_STR does it...
291 * SMC - write 1 to EPP timeout bit XXX
292 * Others - (?) write 0 to EPP timeout bit
295 ppc_reset_epp_timeout(struct ppc_data *ppc)
301 w_str(ppc, r & 0xfe);
307 ppc_check_epp_timeout(struct ppc_data *ppc)
309 ppc_reset_epp_timeout(ppc);
311 return (!(r_str(ppc) & TIMEOUT));
315 * Configure current operating mode
318 ppc_generic_setmode(struct ppc_data *ppc, int mode)
322 /* check if mode is available */
323 if (mode && !(ppc->ppc_avm & mode))
326 /* if ECP mode, configure ecr register */
327 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
328 /* return to byte mode (keeping direction bit),
329 * no interrupt, no DMA to be able to change to
332 w_ecr(ppc, PPC_ECR_RESET);
333 ecr = PPC_DISABLE_INTR;
337 else if (mode & PPB_ECP)
338 /* select ECP mode */
340 else if (mode & PPB_PS2)
341 /* select PS2 mode with ECP */
344 /* select COMPATIBLE/NIBBLE mode */
350 ppc->ppc_mode = mode;
356 * The ppc driver is free to choose options like FIFO or DMA
357 * if ECP mode is available.
359 * The 'RAW' option allows the upper drivers to force the ppc mode
360 * even with FIFO, DMA available.
363 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
367 /* check if mode is available */
368 if (mode && !(ppc->ppc_avm & mode))
371 /* if ECP mode, configure ecr register */
372 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
373 /* return to byte mode (keeping direction bit),
374 * no interrupt, no DMA to be able to change to
377 w_ecr(ppc, PPC_ECR_RESET);
378 ecr = PPC_DISABLE_INTR;
381 /* select EPP mode */
383 else if (mode & PPB_ECP)
384 /* select ECP mode */
386 else if (mode & PPB_PS2)
387 /* select PS2 mode with ECP */
390 /* select COMPATIBLE/NIBBLE mode */
396 ppc->ppc_mode = mode;
401 #ifdef PPC_PROBE_CHIPSET
405 * Probe for a Natsemi PC873xx-family part.
407 * References in this function are to the National Semiconductor
408 * PC87332 datasheet TL/C/11930, May 1995 revision.
410 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
411 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
412 static int pc873xx_irqtab[] = {5, 7, 5, 0};
414 static int pc873xx_regstab[] = {
415 PC873_FER, PC873_FAR, PC873_PTR,
416 PC873_FCR, PC873_PCR, PC873_PMC,
417 PC873_TUP, PC873_SID, PC873_PNP0,
418 PC873_PNP1, PC873_LPTBA, -1
421 static char *pc873xx_rnametab[] = {
422 "FER", "FAR", "PTR", "FCR", "PCR",
423 "PMC", "TUP", "SID", "PNP0", "PNP1",
428 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
430 static int index = 0;
432 int ptr, pcr, val, i;
434 while ((idport = pc873xx_basetab[index++])) {
436 /* XXX should check first to see if this location is already claimed */
439 * Pull the 873xx through the power-on ID cycle (2.2,1.).
440 * We can't use this to locate the chip as it may already have
441 * been used by the BIOS.
443 (void)inb(idport); (void)inb(idport);
444 (void)inb(idport); (void)inb(idport);
447 * Read the SID byte. Possible values are :
454 outb(idport, PC873_SID);
455 val = inb(idport + 1);
456 if ((val & 0xf0) == 0x10) {
457 ppc->ppc_model = NS_PC87332;
458 } else if ((val & 0xf8) == 0x70) {
459 ppc->ppc_model = NS_PC87306;
460 } else if ((val & 0xf8) == 0x50) {
461 ppc->ppc_model = NS_PC87334;
462 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
463 documentation, but probing
465 ppc->ppc_model = NS_PC87303;
467 if (bootverbose && (val != 0xff))
468 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
469 continue ; /* not recognised */
472 /* print registers */
475 for (i=0; pc873xx_regstab[i] != -1; i++) {
476 outb(idport, pc873xx_regstab[i]);
477 printf(" %s=0x%x", pc873xx_rnametab[i],
478 inb(idport + 1) & 0xff);
484 * We think we have one. Is it enabled and where we want it to be?
486 outb(idport, PC873_FER);
487 val = inb(idport + 1);
488 if (!(val & PC873_PPENABLE)) {
490 printf("PC873xx parallel port disabled\n");
493 outb(idport, PC873_FAR);
494 val = inb(idport + 1);
495 /* XXX we should create a driver instance for every port found */
496 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
498 /* First try to change the port address to that requested... */
500 switch(ppc->ppc_base) {
518 outb(idport, PC873_FAR);
519 outb(idport + 1, val);
520 outb(idport + 1, val);
522 /* Check for success by reading back the value we supposedly
523 wrote and comparing...*/
525 outb(idport, PC873_FAR);
526 val = inb(idport + 1) & 0x3;
528 /* If we fail, report the failure... */
530 if (pc873xx_porttab[val] != ppc->ppc_base) {
532 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
533 pc873xx_porttab[val], ppc->ppc_base);
538 outb(idport, PC873_PTR);
539 ptr = inb(idport + 1);
541 /* get irq settings */
542 if (ppc->ppc_base == 0x378)
543 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
545 irq = pc873xx_irqtab[val];
548 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
551 * Check if irq settings are correct
553 if (irq != ppc->ppc_irq) {
555 * If the chipset is not locked and base address is 0x378,
556 * we have another chance
558 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
559 if (ppc->ppc_irq == 7) {
560 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
561 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
563 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
564 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
567 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
570 printf("PC873xx sorry, can't change irq setting\n");
574 printf("PC873xx irq settings are correct\n");
577 outb(idport, PC873_PCR);
578 pcr = inb(idport + 1);
580 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
582 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
584 ppc->ppc_avm |= PPB_NIBBLE;
588 if (pcr & PC873_EPPEN) {
589 ppc->ppc_avm |= PPB_EPP;
594 if (pcr & PC873_EPP19)
595 ppc->ppc_epp = EPP_1_9;
597 ppc->ppc_epp = EPP_1_7;
599 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
600 outb(idport, PC873_PTR);
601 ptr = inb(idport + 1);
602 if (ptr & PC873_EPPRDIR)
603 printf(", Regular mode");
605 printf(", Automatic mode");
607 } else if (pcr & PC873_ECPEN) {
608 ppc->ppc_avm |= PPB_ECP;
612 if (pcr & PC873_ECPCLK) { /* XXX */
613 ppc->ppc_avm |= PPB_PS2;
618 outb(idport, PC873_PTR);
619 ptr = inb(idport + 1);
620 if (ptr & PC873_EXTENDED) {
621 ppc->ppc_avm |= PPB_SPP;
628 printf("PC873xx unlocked");
630 if (chipset_mode & PPB_ECP) {
631 if ((chipset_mode & PPB_EPP) && bootverbose)
632 printf(", ECP+EPP not supported");
635 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
636 outb(idport + 1, pcr);
637 outb(idport + 1, pcr);
642 } else if (chipset_mode & PPB_EPP) {
643 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
644 pcr |= (PC873_EPPEN | PC873_EPP19);
645 outb(idport + 1, pcr);
646 outb(idport + 1, pcr);
648 ppc->ppc_epp = EPP_1_9; /* XXX */
653 /* enable automatic direction turnover */
654 if (ppc->ppc_model == NS_PC87332) {
655 outb(idport, PC873_PTR);
656 ptr = inb(idport + 1);
657 ptr &= ~PC873_EPPRDIR;
658 outb(idport + 1, ptr);
659 outb(idport + 1, ptr);
662 printf(", Automatic mode");
665 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
666 outb(idport + 1, pcr);
667 outb(idport + 1, pcr);
669 /* configure extended bit in PTR */
670 outb(idport, PC873_PTR);
671 ptr = inb(idport + 1);
673 if (chipset_mode & PPB_PS2) {
674 ptr |= PC873_EXTENDED;
680 /* default to NIBBLE mode */
681 ptr &= ~PC873_EXTENDED;
686 outb(idport + 1, ptr);
687 outb(idport + 1, ptr);
690 ppc->ppc_avm = chipset_mode;
696 ppc->ppc_type = PPC_TYPE_GENERIC;
697 ppc_generic_setmode(ppc, chipset_mode);
699 return(chipset_mode);
705 * ppc_smc37c66xgt_detect
707 * SMC FDC37C66xGT configuration.
710 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
715 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
717 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
720 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
723 * Detection: enter configuration mode and read CRD register.
727 outb(csr, SMC665_iCODE);
728 outb(csr, SMC665_iCODE);
732 if (inb(cio) == 0x65) {
737 for (i = 0; i < 2; i++) {
739 outb(csr, SMC666_iCODE);
740 outb(csr, SMC666_iCODE);
744 if (inb(cio) == 0x66) {
749 /* Another chance, CSR may be hard-configured to be at 0x370 */
755 * If chipset not found, do not continue.
763 /* read the port's address: bits 0 and 1 of CR1 */
764 r = inb(cio) & SMC_CR1_ADDR;
765 if (port_address[(int)r] != ppc->ppc_base)
768 ppc->ppc_model = type;
771 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
772 * If SPP mode is detected, try to set ECP+EPP mode
777 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
781 printf(" CR4=0x%x", inb(cio) & 0xff);
788 /* autodetect mode */
790 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
791 if (type == SMC_37C666GT) {
792 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
794 printf(" configuration hardwired, supposing " \
798 if ((inb(cio) & SMC_CR1_MODE) == 0) {
799 /* already in extended parallel port mode, read CR4 */
801 r = (inb(cio) & SMC_CR4_EMODE);
805 ppc->ppc_avm |= PPB_SPP;
811 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
817 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
823 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
825 printf(" ECP+EPP SPP");
829 /* not an extended port mode */
830 ppc->ppc_avm |= PPB_SPP;
837 ppc->ppc_avm = chipset_mode;
839 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
840 if (type == SMC_37C666GT)
844 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
845 /* do not use ECP when the mode is not forced to */
846 outb(cio, r | SMC_CR1_MODE);
850 /* an extended mode is selected */
851 outb(cio, r & ~SMC_CR1_MODE);
853 /* read CR4 register and reset mode field */
855 r = inb(cio) & ~SMC_CR4_EMODE;
857 if (chipset_mode & PPB_ECP) {
858 if (chipset_mode & PPB_EPP) {
859 outb(cio, r | SMC_ECPEPP);
863 outb(cio, r | SMC_ECP);
869 outb(cio, r | SMC_EPPSPP);
874 ppc->ppc_avm = chipset_mode;
877 /* set FIFO threshold to 16 */
878 if (ppc->ppc_avm & PPB_ECP) {
889 if (ppc->ppc_avm & PPB_EPP) {
895 * Set the EPP protocol...
896 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
898 if (ppc->ppc_epp == EPP_1_9)
899 outb(cio, (r & ~SMC_CR4_EPPTYPE));
901 outb(cio, (r | SMC_CR4_EPPTYPE));
904 /* end config mode */
907 ppc->ppc_type = PPC_TYPE_SMCLIKE;
908 ppc_smclike_setmode(ppc, chipset_mode);
910 return (chipset_mode);
914 * SMC FDC37C935 configuration
915 * Found on many Alpha machines
918 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
924 outb(SMC935_CFG, 0x55); /* enter config mode */
925 outb(SMC935_CFG, 0x55);
928 outb(SMC935_IND, SMC935_ID); /* check device id */
929 if (inb(SMC935_DAT) == 0x2)
933 outb(SMC935_CFG, 0xaa); /* exit config mode */
937 ppc->ppc_model = type;
939 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
940 outb(SMC935_DAT, 3); /* which is logical device 3 */
942 /* set io port base */
943 outb(SMC935_IND, SMC935_PORTHI);
944 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
945 outb(SMC935_IND, SMC935_PORTLO);
946 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
949 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
951 ppc->ppc_avm = chipset_mode;
952 outb(SMC935_IND, SMC935_PPMODE);
953 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
955 /* SPP + EPP or just plain SPP */
956 if (chipset_mode & (PPB_SPP)) {
957 if (chipset_mode & PPB_EPP) {
958 if (ppc->ppc_epp == EPP_1_9) {
959 outb(SMC935_IND, SMC935_PPMODE);
960 outb(SMC935_DAT, SMC935_EPP19SPP);
962 if (ppc->ppc_epp == EPP_1_7) {
963 outb(SMC935_IND, SMC935_PPMODE);
964 outb(SMC935_DAT, SMC935_EPP17SPP);
967 outb(SMC935_IND, SMC935_PPMODE);
968 outb(SMC935_DAT, SMC935_SPP);
972 /* ECP + EPP or just plain ECP */
973 if (chipset_mode & PPB_ECP) {
974 if (chipset_mode & PPB_EPP) {
975 if (ppc->ppc_epp == EPP_1_9) {
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_ECPEPP19);
979 if (ppc->ppc_epp == EPP_1_7) {
980 outb(SMC935_IND, SMC935_PPMODE);
981 outb(SMC935_DAT, SMC935_ECPEPP17);
984 outb(SMC935_IND, SMC935_PPMODE);
985 outb(SMC935_DAT, SMC935_ECP);
990 outb(SMC935_CFG, 0xaa); /* exit config mode */
992 ppc->ppc_type = PPC_TYPE_SMCLIKE;
993 ppc_smclike_setmode(ppc, chipset_mode);
995 return (chipset_mode);
999 * Winbond W83877F stuff
1001 * EFER: extended function enable register
1002 * EFIR: extended function index register
1003 * EFDR: extended function data register
1005 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1006 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1008 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1009 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1010 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1011 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1014 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1017 unsigned char r, hefere, hefras;
1019 for (i = 0; i < 4; i ++) {
1020 /* first try to enable configuration registers */
1021 efer = w83877f_efers[i];
1023 /* write the key to the EFER */
1024 for (j = 0; j < w83877f_keyiter[i]; j ++)
1025 outb (efer, w83877f_keys[i]);
1027 /* then check HEFERE and HEFRAS bits */
1029 hefere = inb(efdr) & WINB_HEFERE;
1032 hefras = inb(efdr) & WINB_HEFRAS;
1036 * 0 1 write 89h to 250h (power-on default)
1037 * 1 0 write 86h twice to 3f0h
1038 * 1 1 write 87h twice to 3f0h
1039 * 0 0 write 88h to 250h
1041 if ((hefere | hefras) == w83877f_hefs[i])
1045 return (-1); /* failed */
1048 /* check base port address - read from CR23 */
1050 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1053 /* read CHIP ID from CR9/bits0-3 */
1056 switch (inb(efdr) & WINB_CHIPID) {
1057 case WINB_W83877F_ID:
1058 ppc->ppc_model = WINB_W83877F;
1061 case WINB_W83877AF_ID:
1062 ppc->ppc_model = WINB_W83877AF;
1066 ppc->ppc_model = WINB_UNKNOWN;
1070 /* dump of registers */
1071 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1072 for (i = 0; i <= 0xd; i ++) {
1074 printf("0x%x ", inb(efdr));
1076 for (i = 0x10; i <= 0x17; i ++) {
1078 printf("0x%x ", inb(efdr));
1081 printf("0x%x ", inb(efdr));
1082 for (i = 0x20; i <= 0x29; i ++) {
1084 printf("0x%x ", inb(efdr));
1087 printf("ppc%d:", ppc->ppc_unit);
1090 ppc->ppc_type = PPC_TYPE_GENERIC;
1092 if (!chipset_mode) {
1093 /* autodetect mode */
1097 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1101 r |= (inb(efdr) & WINB_PRTMODS2);
1106 printf("ppc%d: W83757 compatible mode\n",
1108 return (-1); /* generic or SMC-like */
1115 printf(" not in parallel port mode\n");
1118 case (WINB_PARALLEL | WINB_EPP_SPP):
1119 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1124 case (WINB_PARALLEL | WINB_ECP):
1125 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1130 case (WINB_PARALLEL | WINB_ECP_EPP):
1131 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1132 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1135 printf(" ECP+EPP SPP");
1138 printf("%s: unknown case (0x%x)!\n", __func__, r);
1144 /* select CR9 and set PRTMODS2 bit */
1146 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1148 /* select CR0 and reset PRTMODSx bits */
1150 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1152 if (chipset_mode & PPB_ECP) {
1153 if (chipset_mode & PPB_EPP) {
1154 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1158 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1161 outb(efdr, inb(efdr) | WINB_ECP);
1166 /* select EPP_SPP otherwise */
1167 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1171 ppc->ppc_avm = chipset_mode;
1177 /* exit configuration mode */
1180 switch (ppc->ppc_type) {
1181 case PPC_TYPE_SMCLIKE:
1182 ppc_smclike_setmode(ppc, chipset_mode);
1185 ppc_generic_setmode(ppc, chipset_mode);
1189 return (chipset_mode);
1194 * ppc_generic_detect
1197 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1199 /* default to generic */
1200 ppc->ppc_type = PPC_TYPE_GENERIC;
1203 printf("ppc%d:", ppc->ppc_unit);
1205 /* first, check for ECP */
1206 w_ecr(ppc, PPC_ECR_PS2);
1207 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1208 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1212 /* search for SMC style ECP+EPP mode */
1213 w_ecr(ppc, PPC_ECR_EPP);
1216 /* try to reset EPP timeout bit */
1217 if (ppc_check_epp_timeout(ppc)) {
1218 ppc->ppc_dtm |= PPB_EPP;
1220 if (ppc->ppc_dtm & PPB_ECP) {
1221 /* SMC like chipset found */
1222 ppc->ppc_model = SMC_LIKE;
1223 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1232 /* restore to standard mode */
1233 w_ecr(ppc, PPC_ECR_STD);
1236 /* XXX try to detect NIBBLE and PS2 modes */
1237 ppc->ppc_dtm |= PPB_NIBBLE;
1243 ppc->ppc_avm = chipset_mode;
1245 ppc->ppc_avm = ppc->ppc_dtm;
1250 switch (ppc->ppc_type) {
1251 case PPC_TYPE_SMCLIKE:
1252 ppc_smclike_setmode(ppc, chipset_mode);
1255 ppc_generic_setmode(ppc, chipset_mode);
1259 return (chipset_mode);
1265 * mode is the mode suggested at boot
1268 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1270 #ifdef PPC_PROBE_CHIPSET
1273 /* list of supported chipsets */
1274 int (*chipset_detect[])(struct ppc_data *, int) = {
1276 ppc_smc37c66xgt_detect,
1278 ppc_smc37c935_detect,
1284 /* if can't find the port and mode not forced return error */
1285 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1286 return (EIO); /* failed, port not present */
1288 /* assume centronics compatible mode is supported */
1289 ppc->ppc_avm = PPB_COMPATIBLE;
1291 #ifdef PPC_PROBE_CHIPSET
1292 /* we have to differenciate available chipset modes,
1293 * chipset running modes and IEEE-1284 operating modes
1295 * after detection, the port must support running in compatible mode
1297 if (ppc->ppc_flags & 0x40) {
1299 printf("ppc: chipset forced to generic\n");
1302 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1304 #ifdef PPC_PROBE_CHIPSET
1306 for (i=0; chipset_detect[i] != NULL; i++) {
1307 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1308 ppc->ppc_mode = mode;
1315 /* configure/detect ECP FIFO */
1316 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1317 ppc_detect_fifo(ppc);
1323 * ppc_exec_microseq()
1325 * Execute a microsequence.
1326 * Microsequence mechanism is supposed to handle fast I/O operations.
1329 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1331 struct ppc_data *ppc = DEVTOSOFTC(dev);
1332 struct ppb_microseq *mi;
1339 register int accum = 0;
1340 register char *ptr = 0;
1342 struct ppb_microseq *stack = 0;
1344 /* microsequence registers are equivalent to PC-like port registers */
1346 #define r_reg(reg,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, reg))
1347 #define w_reg(reg, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, reg, byte))
1349 #define INCR_PC (mi ++) /* increment program counter */
1353 switch (mi->opcode) {
1355 cc = r_reg(mi->arg[0].i, ppc);
1356 cc &= (char)mi->arg[2].i; /* clear mask */
1357 cc |= (char)mi->arg[1].i; /* assert mask */
1358 w_reg(mi->arg[0].i, ppc, cc);
1362 case MS_OP_RASSERT_P:
1366 if ((len = mi->arg[0].i) == MS_ACCUM) {
1367 accum = ppc->ppc_accum;
1368 for (; accum; accum--)
1369 w_reg(reg, ppc, *ptr++);
1370 ppc->ppc_accum = accum;
1372 for (i=0; i<len; i++)
1373 w_reg(reg, ppc, *ptr++);
1379 case MS_OP_RFETCH_P:
1381 mask = (char)mi->arg[2].i;
1384 if ((len = mi->arg[0].i) == MS_ACCUM) {
1385 accum = ppc->ppc_accum;
1386 for (; accum; accum--)
1387 *ptr++ = r_reg(reg, ppc) & mask;
1388 ppc->ppc_accum = accum;
1390 for (i=0; i<len; i++)
1391 *ptr++ = r_reg(reg, ppc) & mask;
1398 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1406 /* let's suppose the next instr. is the same */
1408 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1409 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1411 if (mi->opcode == MS_OP_DELAY) {
1412 DELAY(mi->arg[0].i);
1420 tsleep(NULL, PPBPRI, "ppbdelay",
1421 mi->arg[0].i * (hz/1000));
1427 iter = mi->arg[1].i;
1428 p = (char *)mi->arg[2].p;
1430 /* XXX delay limited to 255 us */
1431 for (i=0; i<iter; i++) {
1432 w_reg(reg, ppc, *p++);
1433 DELAY((unsigned char)*p++);
1439 ppc->ppc_accum = mi->arg[0].i;
1444 if (--ppc->ppc_accum > 0)
1451 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1458 if ((cc & (char)mi->arg[0].i) == 0)
1465 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1473 * If the C call returns !0 then end the microseq.
1474 * The current state of ptr is passed to the C function
1476 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1483 ppc->ppc_ptr = (char *)mi->arg[0].p;
1489 panic("%s: too much calls", __func__);
1492 /* store the state of the actual
1497 /* jump to the new microsequence */
1498 mi = (struct ppb_microseq *)mi->arg[0].p;
1505 /* retrieve microseq and pc state before the call */
1508 /* reset the stack */
1511 /* XXX return code */
1519 /* can't return to ppb level during the execution
1520 * of a submicrosequence */
1522 panic("%s: can't return to ppb level",
1525 /* update pc for ppb level of execution */
1528 /* return to ppb level of execution */
1532 panic("%s: unknown microsequence opcode 0x%x",
1533 __func__, mi->opcode);
1543 device_t dev = (device_t)arg;
1544 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1545 u_char ctr, ecr, str;
1552 printf("![%x/%x/%x]", ctr, ecr, str);
1555 /* don't use ecp mode with IRQENABLE set */
1556 if (ctr & IRQENABLE) {
1560 /* interrupts are generated by nFault signal
1561 * only in ECP mode */
1562 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1563 /* check if ppc driver has programmed the
1564 * nFault interrupt */
1565 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1567 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1568 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1570 /* shall be handled by underlying layers XXX */
1575 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1576 /* disable interrupts (should be done by hardware though) */
1577 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1578 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1581 /* check if DMA completed */
1582 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1587 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1590 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1600 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1602 /* wakeup the waiting process */
1606 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1608 /* classic interrupt I/O */
1609 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1616 ppc_read(device_t dev, char *buf, int len, int mode)
1622 * Call this function if you want to send data in any advanced mode
1623 * of your parallel port: FIFO, DMA
1625 * If what you want is not possible (no ECP, no DMA...),
1626 * EINVAL is returned
1629 ppc_write(device_t dev, char *buf, int len, int how)
1631 struct ppc_data *ppc = DEVTOSOFTC(dev);
1632 char ecr, ecr_sav, ctr, ctr_sav;
1640 ecr_sav = r_ecr(ppc);
1641 ctr_sav = r_ctr(ppc);
1644 * Send buffer with DMA, FIFO and interrupts
1646 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1648 if (ppc->ppc_dmachan > 0) {
1650 /* byte mode, no intr, no DMA, dir=0, flush fifo
1652 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1655 /* disable nAck interrupts */
1660 ppc->ppc_dmaflags = 0;
1661 ppc->ppc_dmaddr = (caddr_t)buf;
1662 ppc->ppc_dmacnt = (u_int)len;
1664 switch (ppc->ppc_mode) {
1665 case PPB_COMPATIBLE:
1666 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1667 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1670 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1680 /* enter splhigh() not to be preempted
1681 * by the dma interrupt, we may miss
1682 * the wakeup otherwise
1686 ppc->ppc_dmastat = PPC_DMA_INIT;
1688 /* enable interrupts */
1689 ecr &= ~PPC_SERVICE_INTR;
1690 ppc->ppc_irqstat = PPC_IRQ_DMA;
1699 printf("s%d", ppc->ppc_dmacnt);
1701 ppc->ppc_dmastat = PPC_DMA_STARTED;
1703 /* Wait for the DMA completed interrupt. We hope we won't
1704 * miss it, otherwise a signal will be necessary to unlock the
1710 PPBPRI | PCATCH, "ppcdma", 0);
1712 } while (error == EWOULDBLOCK);
1722 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1723 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1725 /* no dma, no interrupt, flush the fifo */
1726 w_ecr(ppc, PPC_ECR_RESET);
1728 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1732 /* wait for an empty fifo */
1733 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1735 for (spin=100; spin; spin--)
1736 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1741 error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1742 if (error != EWOULDBLOCK) {
1746 /* no dma, no interrupt, flush the fifo */
1747 w_ecr(ppc, PPC_ECR_RESET);
1749 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1756 /* no dma, no interrupt, flush the fifo */
1757 w_ecr(ppc, PPC_ECR_RESET);
1760 error = EINVAL; /* XXX we should FIFO and
1767 /* PDRQ must be kept unasserted until nPDACK is
1768 * deasserted for a minimum of 350ns (SMC datasheet)
1770 * Consequence may be a FIFO that never empty
1774 w_ecr(ppc, ecr_sav);
1775 w_ctr(ppc, ctr_sav);
1781 ppc_reset_epp(device_t dev)
1783 struct ppc_data *ppc = DEVTOSOFTC(dev);
1785 ppc_reset_epp_timeout(ppc);
1791 ppc_setmode(device_t dev, int mode)
1793 struct ppc_data *ppc = DEVTOSOFTC(dev);
1795 switch (ppc->ppc_type) {
1796 case PPC_TYPE_SMCLIKE:
1797 return (ppc_smclike_setmode(ppc, mode));
1800 case PPC_TYPE_GENERIC:
1802 return (ppc_generic_setmode(ppc, mode));
1810 static struct isa_pnp_id lpc_ids[] = {
1811 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1812 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1817 ppc_isa_probe(device_t dev)
1822 parent = device_get_parent(dev);
1824 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1827 else if (error != 0) /* XXX shall be set after detection */
1828 device_set_desc(dev, "Parallel port");
1830 return(ppc_probe(dev));
1834 ppc_probe(device_t dev)
1837 static short next_bios_ppc = 0;
1839 struct ppc_data *ppc;
1844 * Allocate the ppc_data structure.
1846 ppc = DEVTOSOFTC(dev);
1847 bzero(ppc, sizeof(struct ppc_data));
1849 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1850 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1852 /* retrieve ISA parameters */
1853 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1857 * If port not specified, use bios list.
1860 if((next_bios_ppc < BIOS_MAX_PPC) &&
1861 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1862 port = *(BIOS_PORTS+next_bios_ppc++);
1864 device_printf(dev, "parallel port found at 0x%x\n",
1867 device_printf(dev, "parallel port not found.\n");
1870 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1871 IO_LPTSIZE_EXTENDED);
1876 * There isn't a bios list on alpha. Put it in the usual place.
1879 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc,
1884 /* IO port is mandatory */
1886 /* Try "extended" IO port range...*/
1887 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1888 &ppc->rid_ioport, 0, ~0,
1889 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1891 if (ppc->res_ioport != 0) {
1893 device_printf(dev, "using extended I/O port range\n");
1895 /* Failed? If so, then try the "normal" IO port range... */
1896 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1897 &ppc->rid_ioport, 0, ~0,
1900 if (ppc->res_ioport != 0) {
1902 device_printf(dev, "using normal I/O port range\n");
1904 device_printf(dev, "cannot reserve I/O port range\n");
1909 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1911 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1912 ppc->bst = rman_get_bustag(ppc->res_ioport);
1914 ppc->ppc_flags = device_get_flags(dev);
1916 if (!(ppc->ppc_flags & 0x20)) {
1917 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1920 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1926 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1928 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1930 ppc->ppc_unit = device_get_unit(dev);
1931 ppc->ppc_model = GENERIC;
1933 ppc->ppc_mode = PPB_COMPATIBLE;
1934 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1936 ppc->ppc_type = PPC_TYPE_GENERIC;
1939 * Try to detect the chipset and its mode.
1941 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1947 if (ppc->res_irq != 0) {
1948 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1951 if (ppc->res_ioport != 0) {
1952 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1954 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1957 if (ppc->res_drq != 0) {
1958 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1960 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1967 ppc_attach(device_t dev)
1969 struct ppc_data *ppc = DEVTOSOFTC(dev);
1972 device_t parent = device_get_parent(dev);
1974 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1975 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1976 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1977 ppc_epp_protocol[ppc->ppc_epp] : "");
1980 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1981 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1983 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1984 /* acquire the DMA channel forever */ /* XXX */
1985 isa_dma_acquire(ppc->ppc_dmachan);
1986 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1989 /* add ppbus as a child of this isa to parallel bridge */
1990 ppbus = device_add_child(dev, "ppbus", -1);
1993 * Probe the ppbus and attach devices found.
1995 device_probe_and_attach(ppbus);
1997 /* register the ppc interrupt handler as default */
1999 /* default to the tty mask for registration */ /* XXX */
2000 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY,
2001 ppcintr, dev, &ppc->intr_cookie) == 0) {
2003 /* remember the ppcintr is registered */
2004 ppc->ppc_registered = 1;
2012 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2014 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2017 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2020 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2023 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2026 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2029 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2032 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2035 return (r_dtr(ppc));
2037 return (r_str(ppc));
2039 return (r_ctr(ppc));
2041 return (r_epp_A(ppc));
2043 return (r_epp_D(ppc));
2045 return (r_ecr(ppc));
2047 return (r_fifo(ppc));
2070 panic("%s: unknown I/O operation", __func__);
2074 return (0); /* not significative */
2078 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2080 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2083 case PPC_IVAR_EPP_PROTO:
2084 *val = (u_long)ppc->ppc_epp;
2087 *val = (u_long)ppc->ppc_irq;
2097 * Resource is useless here since ppbus devices' interrupt handlers are
2098 * multiplexed to the same resource initially allocated by ppc
2101 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2102 void (*ihand)(void *), void *arg, void **cookiep)
2105 struct ppc_data *ppc = DEVTOSOFTC(bus);
2107 if (ppc->ppc_registered) {
2108 /* XXX refuse registration if DMA is in progress */
2110 /* first, unregister the default interrupt handler */
2111 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2112 bus, ppc->res_irq, ppc->intr_cookie)))
2115 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2116 /* ppc->res_irq); */
2118 /* DMA/FIFO operation won't be possible anymore */
2119 ppc->ppc_registered = 0;
2122 /* pass registration to the upper layer, ignore the incoming resource */
2123 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2124 r, flags, ihand, arg, cookiep));
2128 * When no underlying device has a registered interrupt, register the ppc
2132 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2135 struct ppc_data *ppc = DEVTOSOFTC(bus);
2136 device_t parent = device_get_parent(bus);
2138 /* pass unregistration to the upper layer */
2139 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2142 /* default to the tty mask for registration */ /* XXX */
2144 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2145 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) {
2147 /* remember the ppcintr is registered */
2148 ppc->ppc_registered = 1;
2154 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);
2155 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0);