2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
49 #include <machine/vmparam.h>
52 #include <dev/ppbus/ppbconf.h>
53 #include <dev/ppbus/ppb_msq.h>
55 #include <dev/ppc/ppcvar.h>
56 #include <dev/ppc/ppcreg.h>
60 static void ppcintr(void *arg);
62 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
63 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
65 #define LOG_PPC(function, ppc, string) \
66 if (bootverbose) printf("%s: %s\n", function, string)
68 #if defined(__i386__) && defined(PC98)
69 #define PC98_IEEE_1284_DISABLE 0x100
70 #define PC98_IEEE_1284_PORT 0x140
73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
75 devclass_t ppc_devclass;
76 const char ppc_driver_name[] = "ppc";
78 static char *ppc_models[] = {
79 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
80 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
81 "SMC FDC37C935", "PC87303", 0
84 /* list of available modes */
85 static char *ppc_avms[] = {
86 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
87 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
88 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
89 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
92 /* list of current executing modes
93 * Note that few modes do not actually exist.
95 static char *ppc_modes[] = {
96 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
97 "EPP", "EPP", "EPP", "ECP",
98 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
99 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
102 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
106 * BIOS printer list - used by BIOS probe.
108 #define BIOS_PPC_PORTS 0x408
109 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
110 #define BIOS_MAX_PPC 4
117 ppc_ecp_sync(device_t dev) {
120 struct ppc_data *ppc = DEVTOSOFTC(dev);
122 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
126 if ((r & 0xe0) != PPC_ECR_EPP)
129 for (i = 0; i < 100; i++) {
136 printf("ppc%d: ECP sync failed as data still " \
137 "present in FIFO.\n", ppc->ppc_unit);
145 * Detect parallel port FIFO
148 ppc_detect_fifo(struct ppc_data *ppc)
151 char ctr_sav, ctr, cc;
155 ecr_sav = r_ecr(ppc);
156 ctr_sav = r_ctr(ppc);
158 /* enter ECP configuration mode, no interrupt, no DMA */
161 /* read PWord size - transfers in FIFO mode must be PWord aligned */
162 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
164 /* XXX 16 and 32 bits implementations not supported */
165 if (ppc->ppc_pword != PPC_PWORD_8) {
166 LOG_PPC(__func__, ppc, "PWord not supported");
170 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
172 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
174 /* enter ECP test mode, no interrupt, no DMA */
178 for (i=0; i<1024; i++) {
179 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
185 LOG_PPC(__func__, ppc, "can't flush FIFO");
189 /* enable interrupts, no DMA */
192 /* determine readIntrThreshold
193 * fill the FIFO until serviceIntr is set
195 for (i=0; i<1024; i++) {
196 w_fifo(ppc, (char)i);
197 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
198 /* readThreshold reached */
201 if (r_ecr(ppc) & PPC_FIFO_FULL) {
208 LOG_PPC(__func__, ppc, "can't fill FIFO");
212 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
213 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
214 w_ecr(ppc, 0xd0); /* enable interrupts */
216 /* determine writeIntrThreshold
217 * empty the FIFO until serviceIntr is set
219 for (i=ppc->ppc_fifo; i>0; i--) {
220 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
221 LOG_PPC(__func__, ppc, "invalid data in FIFO");
224 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
225 /* writeIntrThreshold reached */
226 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
228 /* if FIFO empty before the last byte, error */
229 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
230 LOG_PPC(__func__, ppc, "data lost in FIFO");
235 /* FIFO must be empty after the last byte */
236 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
237 LOG_PPC(__func__, ppc, "can't empty the FIFO");
254 ppc_detect_port(struct ppc_data *ppc)
257 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
259 if (r_dtr(ppc) != 0xaa)
266 * EPP timeout, according to the PC87332 manual
267 * Semantics of clearing EPP timeout bit.
268 * PC87332 - reading SPP_STR does it...
269 * SMC - write 1 to EPP timeout bit XXX
270 * Others - (?) write 0 to EPP timeout bit
273 ppc_reset_epp_timeout(struct ppc_data *ppc)
279 w_str(ppc, r & 0xfe);
285 ppc_check_epp_timeout(struct ppc_data *ppc)
287 ppc_reset_epp_timeout(ppc);
289 return (!(r_str(ppc) & TIMEOUT));
293 * Configure current operating mode
296 ppc_generic_setmode(struct ppc_data *ppc, int mode)
300 /* check if mode is available */
301 if (mode && !(ppc->ppc_avm & mode))
304 /* if ECP mode, configure ecr register */
305 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
306 /* return to byte mode (keeping direction bit),
307 * no interrupt, no DMA to be able to change to
310 w_ecr(ppc, PPC_ECR_RESET);
311 ecr = PPC_DISABLE_INTR;
315 else if (mode & PPB_ECP)
316 /* select ECP mode */
318 else if (mode & PPB_PS2)
319 /* select PS2 mode with ECP */
322 /* select COMPATIBLE/NIBBLE mode */
328 ppc->ppc_mode = mode;
334 * The ppc driver is free to choose options like FIFO or DMA
335 * if ECP mode is available.
337 * The 'RAW' option allows the upper drivers to force the ppc mode
338 * even with FIFO, DMA available.
341 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
345 /* check if mode is available */
346 if (mode && !(ppc->ppc_avm & mode))
349 /* if ECP mode, configure ecr register */
350 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
351 /* return to byte mode (keeping direction bit),
352 * no interrupt, no DMA to be able to change to
355 w_ecr(ppc, PPC_ECR_RESET);
356 ecr = PPC_DISABLE_INTR;
359 /* select EPP mode */
361 else if (mode & PPB_ECP)
362 /* select ECP mode */
364 else if (mode & PPB_PS2)
365 /* select PS2 mode with ECP */
368 /* select COMPATIBLE/NIBBLE mode */
374 ppc->ppc_mode = mode;
379 #ifdef PPC_PROBE_CHIPSET
383 * Probe for a Natsemi PC873xx-family part.
385 * References in this function are to the National Semiconductor
386 * PC87332 datasheet TL/C/11930, May 1995 revision.
388 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
389 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
390 static int pc873xx_irqtab[] = {5, 7, 5, 0};
392 static int pc873xx_regstab[] = {
393 PC873_FER, PC873_FAR, PC873_PTR,
394 PC873_FCR, PC873_PCR, PC873_PMC,
395 PC873_TUP, PC873_SID, PC873_PNP0,
396 PC873_PNP1, PC873_LPTBA, -1
399 static char *pc873xx_rnametab[] = {
400 "FER", "FAR", "PTR", "FCR", "PCR",
401 "PMC", "TUP", "SID", "PNP0", "PNP1",
406 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
408 static int index = 0;
410 int ptr, pcr, val, i;
412 while ((idport = pc873xx_basetab[index++])) {
414 /* XXX should check first to see if this location is already claimed */
417 * Pull the 873xx through the power-on ID cycle (2.2,1.).
418 * We can't use this to locate the chip as it may already have
419 * been used by the BIOS.
421 (void)inb(idport); (void)inb(idport);
422 (void)inb(idport); (void)inb(idport);
425 * Read the SID byte. Possible values are :
432 outb(idport, PC873_SID);
433 val = inb(idport + 1);
434 if ((val & 0xf0) == 0x10) {
435 ppc->ppc_model = NS_PC87332;
436 } else if ((val & 0xf8) == 0x70) {
437 ppc->ppc_model = NS_PC87306;
438 } else if ((val & 0xf8) == 0x50) {
439 ppc->ppc_model = NS_PC87334;
440 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
441 documentation, but probing
443 ppc->ppc_model = NS_PC87303;
445 if (bootverbose && (val != 0xff))
446 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
447 continue ; /* not recognised */
450 /* print registers */
453 for (i=0; pc873xx_regstab[i] != -1; i++) {
454 outb(idport, pc873xx_regstab[i]);
455 printf(" %s=0x%x", pc873xx_rnametab[i],
456 inb(idport + 1) & 0xff);
462 * We think we have one. Is it enabled and where we want it to be?
464 outb(idport, PC873_FER);
465 val = inb(idport + 1);
466 if (!(val & PC873_PPENABLE)) {
468 printf("PC873xx parallel port disabled\n");
471 outb(idport, PC873_FAR);
472 val = inb(idport + 1);
473 /* XXX we should create a driver instance for every port found */
474 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
476 /* First try to change the port address to that requested... */
478 switch(ppc->ppc_base) {
496 outb(idport, PC873_FAR);
497 outb(idport + 1, val);
498 outb(idport + 1, val);
500 /* Check for success by reading back the value we supposedly
501 wrote and comparing...*/
503 outb(idport, PC873_FAR);
504 val = inb(idport + 1) & 0x3;
506 /* If we fail, report the failure... */
508 if (pc873xx_porttab[val] != ppc->ppc_base) {
510 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
511 pc873xx_porttab[val], ppc->ppc_base);
516 outb(idport, PC873_PTR);
517 ptr = inb(idport + 1);
519 /* get irq settings */
520 if (ppc->ppc_base == 0x378)
521 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
523 irq = pc873xx_irqtab[val];
526 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
529 * Check if irq settings are correct
531 if (irq != ppc->ppc_irq) {
533 * If the chipset is not locked and base address is 0x378,
534 * we have another chance
536 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
537 if (ppc->ppc_irq == 7) {
538 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
539 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
541 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
542 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
545 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
548 printf("PC873xx sorry, can't change irq setting\n");
552 printf("PC873xx irq settings are correct\n");
555 outb(idport, PC873_PCR);
556 pcr = inb(idport + 1);
558 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
560 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
562 ppc->ppc_avm |= PPB_NIBBLE;
566 if (pcr & PC873_EPPEN) {
567 ppc->ppc_avm |= PPB_EPP;
572 if (pcr & PC873_EPP19)
573 ppc->ppc_epp = EPP_1_9;
575 ppc->ppc_epp = EPP_1_7;
577 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
578 outb(idport, PC873_PTR);
579 ptr = inb(idport + 1);
580 if (ptr & PC873_EPPRDIR)
581 printf(", Regular mode");
583 printf(", Automatic mode");
585 } else if (pcr & PC873_ECPEN) {
586 ppc->ppc_avm |= PPB_ECP;
590 if (pcr & PC873_ECPCLK) { /* XXX */
591 ppc->ppc_avm |= PPB_PS2;
596 outb(idport, PC873_PTR);
597 ptr = inb(idport + 1);
598 if (ptr & PC873_EXTENDED) {
599 ppc->ppc_avm |= PPB_SPP;
606 printf("PC873xx unlocked");
608 if (chipset_mode & PPB_ECP) {
609 if ((chipset_mode & PPB_EPP) && bootverbose)
610 printf(", ECP+EPP not supported");
613 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
614 outb(idport + 1, pcr);
615 outb(idport + 1, pcr);
620 } else if (chipset_mode & PPB_EPP) {
621 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
622 pcr |= (PC873_EPPEN | PC873_EPP19);
623 outb(idport + 1, pcr);
624 outb(idport + 1, pcr);
626 ppc->ppc_epp = EPP_1_9; /* XXX */
631 /* enable automatic direction turnover */
632 if (ppc->ppc_model == NS_PC87332) {
633 outb(idport, PC873_PTR);
634 ptr = inb(idport + 1);
635 ptr &= ~PC873_EPPRDIR;
636 outb(idport + 1, ptr);
637 outb(idport + 1, ptr);
640 printf(", Automatic mode");
643 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
644 outb(idport + 1, pcr);
645 outb(idport + 1, pcr);
647 /* configure extended bit in PTR */
648 outb(idport, PC873_PTR);
649 ptr = inb(idport + 1);
651 if (chipset_mode & PPB_PS2) {
652 ptr |= PC873_EXTENDED;
658 /* default to NIBBLE mode */
659 ptr &= ~PC873_EXTENDED;
664 outb(idport + 1, ptr);
665 outb(idport + 1, ptr);
668 ppc->ppc_avm = chipset_mode;
674 ppc->ppc_type = PPC_TYPE_GENERIC;
675 ppc_generic_setmode(ppc, chipset_mode);
677 return(chipset_mode);
683 * ppc_smc37c66xgt_detect
685 * SMC FDC37C66xGT configuration.
688 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
693 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
695 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
698 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
701 * Detection: enter configuration mode and read CRD register.
705 outb(csr, SMC665_iCODE);
706 outb(csr, SMC665_iCODE);
710 if (inb(cio) == 0x65) {
715 for (i = 0; i < 2; i++) {
717 outb(csr, SMC666_iCODE);
718 outb(csr, SMC666_iCODE);
722 if (inb(cio) == 0x66) {
727 /* Another chance, CSR may be hard-configured to be at 0x370 */
733 * If chipset not found, do not continue.
741 /* read the port's address: bits 0 and 1 of CR1 */
742 r = inb(cio) & SMC_CR1_ADDR;
743 if (port_address[(int)r] != ppc->ppc_base)
746 ppc->ppc_model = type;
749 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
750 * If SPP mode is detected, try to set ECP+EPP mode
755 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
759 printf(" CR4=0x%x", inb(cio) & 0xff);
766 /* autodetect mode */
768 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
769 if (type == SMC_37C666GT) {
770 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
772 printf(" configuration hardwired, supposing " \
776 if ((inb(cio) & SMC_CR1_MODE) == 0) {
777 /* already in extended parallel port mode, read CR4 */
779 r = (inb(cio) & SMC_CR4_EMODE);
783 ppc->ppc_avm |= PPB_SPP;
789 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
795 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
801 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
803 printf(" ECP+EPP SPP");
807 /* not an extended port mode */
808 ppc->ppc_avm |= PPB_SPP;
815 ppc->ppc_avm = chipset_mode;
817 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
818 if (type == SMC_37C666GT)
822 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
823 /* do not use ECP when the mode is not forced to */
824 outb(cio, r | SMC_CR1_MODE);
828 /* an extended mode is selected */
829 outb(cio, r & ~SMC_CR1_MODE);
831 /* read CR4 register and reset mode field */
833 r = inb(cio) & ~SMC_CR4_EMODE;
835 if (chipset_mode & PPB_ECP) {
836 if (chipset_mode & PPB_EPP) {
837 outb(cio, r | SMC_ECPEPP);
841 outb(cio, r | SMC_ECP);
847 outb(cio, r | SMC_EPPSPP);
852 ppc->ppc_avm = chipset_mode;
855 /* set FIFO threshold to 16 */
856 if (ppc->ppc_avm & PPB_ECP) {
867 if (ppc->ppc_avm & PPB_EPP) {
873 * Set the EPP protocol...
874 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
876 if (ppc->ppc_epp == EPP_1_9)
877 outb(cio, (r & ~SMC_CR4_EPPTYPE));
879 outb(cio, (r | SMC_CR4_EPPTYPE));
882 /* end config mode */
885 ppc->ppc_type = PPC_TYPE_SMCLIKE;
886 ppc_smclike_setmode(ppc, chipset_mode);
888 return (chipset_mode);
892 * SMC FDC37C935 configuration
893 * Found on many Alpha machines
896 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
902 outb(SMC935_CFG, 0x55); /* enter config mode */
903 outb(SMC935_CFG, 0x55);
906 outb(SMC935_IND, SMC935_ID); /* check device id */
907 if (inb(SMC935_DAT) == 0x2)
911 outb(SMC935_CFG, 0xaa); /* exit config mode */
915 ppc->ppc_model = type;
917 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
918 outb(SMC935_DAT, 3); /* which is logical device 3 */
920 /* set io port base */
921 outb(SMC935_IND, SMC935_PORTHI);
922 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
923 outb(SMC935_IND, SMC935_PORTLO);
924 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
927 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
929 ppc->ppc_avm = chipset_mode;
930 outb(SMC935_IND, SMC935_PPMODE);
931 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
933 /* SPP + EPP or just plain SPP */
934 if (chipset_mode & (PPB_SPP)) {
935 if (chipset_mode & PPB_EPP) {
936 if (ppc->ppc_epp == EPP_1_9) {
937 outb(SMC935_IND, SMC935_PPMODE);
938 outb(SMC935_DAT, SMC935_EPP19SPP);
940 if (ppc->ppc_epp == EPP_1_7) {
941 outb(SMC935_IND, SMC935_PPMODE);
942 outb(SMC935_DAT, SMC935_EPP17SPP);
945 outb(SMC935_IND, SMC935_PPMODE);
946 outb(SMC935_DAT, SMC935_SPP);
950 /* ECP + EPP or just plain ECP */
951 if (chipset_mode & PPB_ECP) {
952 if (chipset_mode & PPB_EPP) {
953 if (ppc->ppc_epp == EPP_1_9) {
954 outb(SMC935_IND, SMC935_PPMODE);
955 outb(SMC935_DAT, SMC935_ECPEPP19);
957 if (ppc->ppc_epp == EPP_1_7) {
958 outb(SMC935_IND, SMC935_PPMODE);
959 outb(SMC935_DAT, SMC935_ECPEPP17);
962 outb(SMC935_IND, SMC935_PPMODE);
963 outb(SMC935_DAT, SMC935_ECP);
968 outb(SMC935_CFG, 0xaa); /* exit config mode */
970 ppc->ppc_type = PPC_TYPE_SMCLIKE;
971 ppc_smclike_setmode(ppc, chipset_mode);
973 return (chipset_mode);
977 * Winbond W83877F stuff
979 * EFER: extended function enable register
980 * EFIR: extended function index register
981 * EFDR: extended function data register
983 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
984 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
986 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
987 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
988 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
989 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
992 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
995 unsigned char r, hefere, hefras;
997 for (i = 0; i < 4; i ++) {
998 /* first try to enable configuration registers */
999 efer = w83877f_efers[i];
1001 /* write the key to the EFER */
1002 for (j = 0; j < w83877f_keyiter[i]; j ++)
1003 outb (efer, w83877f_keys[i]);
1005 /* then check HEFERE and HEFRAS bits */
1007 hefere = inb(efdr) & WINB_HEFERE;
1010 hefras = inb(efdr) & WINB_HEFRAS;
1014 * 0 1 write 89h to 250h (power-on default)
1015 * 1 0 write 86h twice to 3f0h
1016 * 1 1 write 87h twice to 3f0h
1017 * 0 0 write 88h to 250h
1019 if ((hefere | hefras) == w83877f_hefs[i])
1023 return (-1); /* failed */
1026 /* check base port address - read from CR23 */
1028 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1031 /* read CHIP ID from CR9/bits0-3 */
1034 switch (inb(efdr) & WINB_CHIPID) {
1035 case WINB_W83877F_ID:
1036 ppc->ppc_model = WINB_W83877F;
1039 case WINB_W83877AF_ID:
1040 ppc->ppc_model = WINB_W83877AF;
1044 ppc->ppc_model = WINB_UNKNOWN;
1048 /* dump of registers */
1049 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1050 for (i = 0; i <= 0xd; i ++) {
1052 printf("0x%x ", inb(efdr));
1054 for (i = 0x10; i <= 0x17; i ++) {
1056 printf("0x%x ", inb(efdr));
1059 printf("0x%x ", inb(efdr));
1060 for (i = 0x20; i <= 0x29; i ++) {
1062 printf("0x%x ", inb(efdr));
1065 printf("ppc%d:", ppc->ppc_unit);
1068 ppc->ppc_type = PPC_TYPE_GENERIC;
1070 if (!chipset_mode) {
1071 /* autodetect mode */
1075 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1079 r |= (inb(efdr) & WINB_PRTMODS2);
1084 printf("ppc%d: W83757 compatible mode\n",
1086 return (-1); /* generic or SMC-like */
1093 printf(" not in parallel port mode\n");
1096 case (WINB_PARALLEL | WINB_EPP_SPP):
1097 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1102 case (WINB_PARALLEL | WINB_ECP):
1103 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1108 case (WINB_PARALLEL | WINB_ECP_EPP):
1109 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1110 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1113 printf(" ECP+EPP SPP");
1116 printf("%s: unknown case (0x%x)!\n", __func__, r);
1122 /* select CR9 and set PRTMODS2 bit */
1124 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1126 /* select CR0 and reset PRTMODSx bits */
1128 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1130 if (chipset_mode & PPB_ECP) {
1131 if (chipset_mode & PPB_EPP) {
1132 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1136 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1139 outb(efdr, inb(efdr) | WINB_ECP);
1144 /* select EPP_SPP otherwise */
1145 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1149 ppc->ppc_avm = chipset_mode;
1155 /* exit configuration mode */
1158 switch (ppc->ppc_type) {
1159 case PPC_TYPE_SMCLIKE:
1160 ppc_smclike_setmode(ppc, chipset_mode);
1163 ppc_generic_setmode(ppc, chipset_mode);
1167 return (chipset_mode);
1172 * ppc_generic_detect
1175 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1177 /* default to generic */
1178 ppc->ppc_type = PPC_TYPE_GENERIC;
1181 printf("ppc%d:", ppc->ppc_unit);
1183 /* first, check for ECP */
1184 w_ecr(ppc, PPC_ECR_PS2);
1185 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1186 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1190 /* search for SMC style ECP+EPP mode */
1191 w_ecr(ppc, PPC_ECR_EPP);
1194 /* try to reset EPP timeout bit */
1195 if (ppc_check_epp_timeout(ppc)) {
1196 ppc->ppc_dtm |= PPB_EPP;
1198 if (ppc->ppc_dtm & PPB_ECP) {
1199 /* SMC like chipset found */
1200 ppc->ppc_model = SMC_LIKE;
1201 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1210 /* restore to standard mode */
1211 w_ecr(ppc, PPC_ECR_STD);
1214 /* XXX try to detect NIBBLE and PS2 modes */
1215 ppc->ppc_dtm |= PPB_NIBBLE;
1221 ppc->ppc_avm = chipset_mode;
1223 ppc->ppc_avm = ppc->ppc_dtm;
1228 switch (ppc->ppc_type) {
1229 case PPC_TYPE_SMCLIKE:
1230 ppc_smclike_setmode(ppc, chipset_mode);
1233 ppc_generic_setmode(ppc, chipset_mode);
1237 return (chipset_mode);
1243 * mode is the mode suggested at boot
1246 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1248 #ifdef PPC_PROBE_CHIPSET
1251 /* list of supported chipsets */
1252 int (*chipset_detect[])(struct ppc_data *, int) = {
1254 ppc_smc37c66xgt_detect,
1256 ppc_smc37c935_detect,
1262 /* if can't find the port and mode not forced return error */
1263 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1264 return (EIO); /* failed, port not present */
1266 /* assume centronics compatible mode is supported */
1267 ppc->ppc_avm = PPB_COMPATIBLE;
1269 #ifdef PPC_PROBE_CHIPSET
1270 /* we have to differenciate available chipset modes,
1271 * chipset running modes and IEEE-1284 operating modes
1273 * after detection, the port must support running in compatible mode
1275 if (ppc->ppc_flags & 0x40) {
1277 printf("ppc: chipset forced to generic\n");
1280 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1282 #ifdef PPC_PROBE_CHIPSET
1284 for (i=0; chipset_detect[i] != NULL; i++) {
1285 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1286 ppc->ppc_mode = mode;
1293 /* configure/detect ECP FIFO */
1294 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1295 ppc_detect_fifo(ppc);
1301 * ppc_exec_microseq()
1303 * Execute a microsequence.
1304 * Microsequence mechanism is supposed to handle fast I/O operations.
1307 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1309 struct ppc_data *ppc = DEVTOSOFTC(dev);
1310 struct ppb_microseq *mi;
1317 register int accum = 0;
1318 register char *ptr = 0;
1320 struct ppb_microseq *stack = 0;
1322 /* microsequence registers are equivalent to PC-like port registers */
1324 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1325 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1327 #define INCR_PC (mi ++) /* increment program counter */
1331 switch (mi->opcode) {
1333 cc = r_reg(mi->arg[0].i, ppc);
1334 cc &= (char)mi->arg[2].i; /* clear mask */
1335 cc |= (char)mi->arg[1].i; /* assert mask */
1336 w_reg(mi->arg[0].i, ppc, cc);
1340 case MS_OP_RASSERT_P:
1344 if ((len = mi->arg[0].i) == MS_ACCUM) {
1345 accum = ppc->ppc_accum;
1346 for (; accum; accum--)
1347 w_reg(reg, ppc, *ptr++);
1348 ppc->ppc_accum = accum;
1350 for (i=0; i<len; i++)
1351 w_reg(reg, ppc, *ptr++);
1357 case MS_OP_RFETCH_P:
1359 mask = (char)mi->arg[2].i;
1362 if ((len = mi->arg[0].i) == MS_ACCUM) {
1363 accum = ppc->ppc_accum;
1364 for (; accum; accum--)
1365 *ptr++ = r_reg(reg, ppc) & mask;
1366 ppc->ppc_accum = accum;
1368 for (i=0; i<len; i++)
1369 *ptr++ = r_reg(reg, ppc) & mask;
1376 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1384 /* let's suppose the next instr. is the same */
1386 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1387 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1389 if (mi->opcode == MS_OP_DELAY) {
1390 DELAY(mi->arg[0].i);
1398 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1404 iter = mi->arg[1].i;
1405 p = (char *)mi->arg[2].p;
1407 /* XXX delay limited to 255 us */
1408 for (i=0; i<iter; i++) {
1409 w_reg(reg, ppc, *p++);
1410 DELAY((unsigned char)*p++);
1416 ppc->ppc_accum = mi->arg[0].i;
1421 if (--ppc->ppc_accum > 0)
1428 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1435 if ((cc & (char)mi->arg[0].i) == 0)
1442 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1450 * If the C call returns !0 then end the microseq.
1451 * The current state of ptr is passed to the C function
1453 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1460 ppc->ppc_ptr = (char *)mi->arg[0].p;
1466 panic("%s: too much calls", __func__);
1469 /* store the state of the actual
1474 /* jump to the new microsequence */
1475 mi = (struct ppb_microseq *)mi->arg[0].p;
1482 /* retrieve microseq and pc state before the call */
1485 /* reset the stack */
1488 /* XXX return code */
1496 /* can't return to ppb level during the execution
1497 * of a submicrosequence */
1499 panic("%s: can't return to ppb level",
1502 /* update pc for ppb level of execution */
1505 /* return to ppb level of execution */
1509 panic("%s: unknown microsequence opcode 0x%x",
1510 __func__, mi->opcode);
1520 struct ppc_data *ppc = arg;
1521 u_char ctr, ecr, str;
1524 * If we have any child interrupt handlers registered, let
1525 * them handle this interrupt.
1527 * XXX: If DMA is in progress should we just complete that w/o
1530 if (ppc->ppc_child_handlers > 0) {
1531 intr_event_execute_handlers(curproc, ppc->ppc_intr_event);
1539 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1540 printf("![%x/%x/%x]", ctr, ecr, str);
1543 /* don't use ecp mode with IRQENABLE set */
1544 if (ctr & IRQENABLE) {
1548 /* interrupts are generated by nFault signal
1549 * only in ECP mode */
1550 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1551 /* check if ppc driver has programmed the
1552 * nFault interrupt */
1553 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1555 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1556 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1558 /* shall be handled by underlying layers XXX */
1563 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1564 /* disable interrupts (should be done by hardware though) */
1565 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1566 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1569 /* check if DMA completed */
1570 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1575 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1578 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1582 ppc->ppc_dmadone(ppc);
1583 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1585 /* wakeup the waiting process */
1589 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1591 /* classic interrupt I/O */
1592 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1599 ppc_read(device_t dev, char *buf, int len, int mode)
1605 ppc_write(device_t dev, char *buf, int len, int how)
1611 ppc_reset_epp(device_t dev)
1613 struct ppc_data *ppc = DEVTOSOFTC(dev);
1615 ppc_reset_epp_timeout(ppc);
1621 ppc_setmode(device_t dev, int mode)
1623 struct ppc_data *ppc = DEVTOSOFTC(dev);
1625 switch (ppc->ppc_type) {
1626 case PPC_TYPE_SMCLIKE:
1627 return (ppc_smclike_setmode(ppc, mode));
1630 case PPC_TYPE_GENERIC:
1632 return (ppc_generic_setmode(ppc, mode));
1641 ppc_probe(device_t dev, int rid)
1644 static short next_bios_ppc = 0;
1646 unsigned int pc98_ieee_mode = 0x00;
1650 struct ppc_data *ppc;
1655 * Allocate the ppc_data structure.
1657 ppc = DEVTOSOFTC(dev);
1658 bzero(ppc, sizeof(struct ppc_data));
1660 ppc->rid_ioport = rid;
1662 /* retrieve ISA parameters */
1663 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1667 * If port not specified, use bios list.
1671 if (next_bios_ppc == 0) {
1672 /* Use default IEEE-1284 port of NEC PC-98x1 */
1673 port = PC98_IEEE_1284_PORT;
1677 "parallel port found at 0x%x\n",
1681 if((next_bios_ppc < BIOS_MAX_PPC) &&
1682 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1683 port = *(BIOS_PORTS+next_bios_ppc++);
1685 device_printf(dev, "parallel port found at 0x%x\n",
1688 device_printf(dev, "parallel port not found.\n");
1692 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1693 IO_LPTSIZE_EXTENDED);
1697 /* IO port is mandatory */
1699 /* Try "extended" IO port range...*/
1700 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1701 &ppc->rid_ioport, 0, ~0,
1702 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1704 if (ppc->res_ioport != 0) {
1706 device_printf(dev, "using extended I/O port range\n");
1708 /* Failed? If so, then try the "normal" IO port range... */
1709 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1710 &ppc->rid_ioport, 0, ~0,
1713 if (ppc->res_ioport != 0) {
1715 device_printf(dev, "using normal I/O port range\n");
1717 device_printf(dev, "cannot reserve I/O port range\n");
1722 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1724 ppc->ppc_flags = device_get_flags(dev);
1726 if (!(ppc->ppc_flags & 0x20)) {
1727 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1730 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1736 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1738 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1740 ppc->ppc_unit = device_get_unit(dev);
1741 ppc->ppc_model = GENERIC;
1743 ppc->ppc_mode = PPB_COMPATIBLE;
1744 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1746 ppc->ppc_type = PPC_TYPE_GENERIC;
1748 #if defined(__i386__) && defined(PC98)
1750 * IEEE STD 1284 Function Check and Enable
1751 * for default IEEE-1284 port of NEC PC-98x1
1753 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1754 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1755 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1756 pc98_ieee_mode = tmp;
1757 if ((tmp & 0x10) == 0x10) {
1758 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1759 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1760 if ((tmp & 0x10) == 0x10)
1763 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1764 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1765 if ((tmp & 0x10) != 0x10)
1768 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1773 * Try to detect the chipset and its mode.
1775 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1781 #if defined(__i386__) && defined(PC98)
1782 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1783 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1784 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1787 if (ppc->res_irq != 0) {
1788 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1791 if (ppc->res_ioport != 0) {
1792 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1795 if (ppc->res_drq != 0) {
1796 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1803 ppc_attach(device_t dev)
1805 struct ppc_data *ppc = DEVTOSOFTC(dev);
1809 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1810 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1811 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1812 ppc_epp_protocol[ppc->ppc_epp] : "");
1815 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1816 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1820 * Create an interrupt event to manage the handlers of
1823 error = intr_event_create(&ppc->ppc_intr_event, ppc, 0, -1,
1824 NULL, NULL, NULL, NULL, "%s:", device_get_nameunit(dev));
1827 "failed to create interrupt event: %d\n", error);
1831 /* default to the tty mask for registration */ /* XXX */
1832 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY,
1833 NULL, ppcintr, ppc, &ppc->intr_cookie);
1836 "failed to register interrupt handler: %d\n",
1842 /* add ppbus as a child of this isa to parallel bridge */
1843 ppbus = device_add_child(dev, "ppbus", -1);
1846 * Probe the ppbus and attach devices found.
1848 device_probe_and_attach(ppbus);
1854 ppc_detach(device_t dev)
1856 struct ppc_data *ppc = DEVTOSOFTC(dev);
1860 if (ppc->res_irq == 0) {
1864 /* detach & delete all children */
1865 if (!device_get_children(dev, &children, &nchildren)) {
1866 for (i = 0; i < nchildren; i++)
1868 device_delete_child(dev, children[i]);
1869 free(children, M_TEMP);
1872 if (ppc->res_irq != 0) {
1873 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1874 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1877 if (ppc->res_ioport != 0) {
1878 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1881 if (ppc->res_drq != 0) {
1882 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1890 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1892 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1895 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1898 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1901 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1904 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1907 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1910 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1913 return (r_dtr(ppc));
1915 return (r_str(ppc));
1917 return (r_ctr(ppc));
1919 return (r_epp_A(ppc));
1921 return (r_epp_D(ppc));
1923 return (r_ecr(ppc));
1925 return (r_fifo(ppc));
1948 panic("%s: unknown I/O operation", __func__);
1952 return (0); /* not significative */
1956 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1958 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1961 case PPC_IVAR_EPP_PROTO:
1962 *val = (u_long)ppc->ppc_epp;
1972 * We allow child devices to allocate an IRQ resource at rid 0 for their
1973 * interrupt handlers.
1976 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1977 u_long start, u_long end, u_long count, u_int flags)
1979 struct ppc_data *ppc = DEVTOSOFTC(bus);
1984 return (ppc->res_irq);
1991 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1995 struct ppc_data *ppc = DEVTOSOFTC(bus);
2001 KASSERT(r == ppc->res_irq,
2002 ("ppc child IRQ resource mismatch"));
2011 * If a child wants to add a handler for our IRQ, add it to our interrupt
2012 * event. Otherwise, fail the request.
2015 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2016 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep)
2018 struct ppc_data *ppc = DEVTOSOFTC(bus);
2021 if (r != ppc->res_irq)
2024 /* We don't allow filters. */
2028 error = intr_event_add_handler(ppc->ppc_intr_event,
2029 device_get_nameunit(child), NULL, ihand, arg, intr_priority(flags),
2032 ppc->ppc_child_handlers++;
2037 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *cookie)
2039 struct ppc_data *ppc = DEVTOSOFTC(bus);
2042 if (r != ppc->res_irq)
2045 KASSERT(intr_handler_source(cookie) == ppc,
2046 ("ppc_teardown_intr: source mismatch"));
2047 error = intr_event_remove_handler(cookie);
2049 ppc->ppc_child_handlers--;
2053 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);