2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/interrupt.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
51 #include <machine/vmparam.h>
54 #include <dev/ppbus/ppbconf.h>
55 #include <dev/ppbus/ppb_msq.h>
57 #include <dev/ppc/ppcvar.h>
58 #include <dev/ppc/ppcreg.h>
62 static void ppcintr(void *arg);
64 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
65 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
67 #define LOG_PPC(function, ppc, string) \
68 if (bootverbose) printf("%s: %s\n", function, string)
70 #if defined(__i386__) && defined(PC98)
71 #define PC98_IEEE_1284_DISABLE 0x100
72 #define PC98_IEEE_1284_PORT 0x140
75 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
78 * We use critical enter/exit for the simple config locking needed to
79 * detect the devices. We just want to make sure that both of our writes
80 * happen without someone else also writing to those config registers. Since
81 * we just do this at startup, Giant keeps multiple threads from executing,
82 * and critical_enter() then is all that's needed to keep us from being preempted
83 * during the critical sequences with the hardware.
85 * Note: this doesn't prevent multiple threads from putting the chips into
86 * config mode, but since we only do that to detect the type at startup the
87 * extra overhead isn't needed since Giant protects us from multiple entry
88 * and no other code changes these registers.
90 #define PPC_CONFIG_LOCK(ppc) critical_enter()
91 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
93 devclass_t ppc_devclass;
94 const char ppc_driver_name[] = "ppc";
96 static char *ppc_models[] = {
97 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
98 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
99 "SMC FDC37C935", "PC87303", 0
102 /* list of available modes */
103 static char *ppc_avms[] = {
104 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
105 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
106 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
107 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
110 /* list of current executing modes
111 * Note that few modes do not actually exist.
113 static char *ppc_modes[] = {
114 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
115 "EPP", "EPP", "EPP", "ECP",
116 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
117 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
120 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
124 * BIOS printer list - used by BIOS probe.
126 #define BIOS_PPC_PORTS 0x408
127 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
128 #define BIOS_MAX_PPC 4
135 ppc_ecp_sync(device_t dev)
138 struct ppc_data *ppc = DEVTOSOFTC(dev);
140 PPC_ASSERT_LOCKED(ppc);
141 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
145 if ((r & 0xe0) != PPC_ECR_EPP)
148 for (i = 0; i < 100; i++) {
155 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
163 * Detect parallel port FIFO
166 ppc_detect_fifo(struct ppc_data *ppc)
169 char ctr_sav, ctr, cc;
173 ecr_sav = r_ecr(ppc);
174 ctr_sav = r_ctr(ppc);
176 /* enter ECP configuration mode, no interrupt, no DMA */
179 /* read PWord size - transfers in FIFO mode must be PWord aligned */
180 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
182 /* XXX 16 and 32 bits implementations not supported */
183 if (ppc->ppc_pword != PPC_PWORD_8) {
184 LOG_PPC(__func__, ppc, "PWord not supported");
188 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
190 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
192 /* enter ECP test mode, no interrupt, no DMA */
196 for (i=0; i<1024; i++) {
197 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
203 LOG_PPC(__func__, ppc, "can't flush FIFO");
207 /* enable interrupts, no DMA */
210 /* determine readIntrThreshold
211 * fill the FIFO until serviceIntr is set
213 for (i=0; i<1024; i++) {
214 w_fifo(ppc, (char)i);
215 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
216 /* readThreshold reached */
219 if (r_ecr(ppc) & PPC_FIFO_FULL) {
226 LOG_PPC(__func__, ppc, "can't fill FIFO");
230 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
231 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
232 w_ecr(ppc, 0xd0); /* enable interrupts */
234 /* determine writeIntrThreshold
235 * empty the FIFO until serviceIntr is set
237 for (i=ppc->ppc_fifo; i>0; i--) {
238 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
239 LOG_PPC(__func__, ppc, "invalid data in FIFO");
242 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
243 /* writeIntrThreshold reached */
244 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
246 /* if FIFO empty before the last byte, error */
247 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
248 LOG_PPC(__func__, ppc, "data lost in FIFO");
253 /* FIFO must be empty after the last byte */
254 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
255 LOG_PPC(__func__, ppc, "can't empty the FIFO");
272 ppc_detect_port(struct ppc_data *ppc)
275 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
277 if (r_dtr(ppc) != 0xaa)
284 * EPP timeout, according to the PC87332 manual
285 * Semantics of clearing EPP timeout bit.
286 * PC87332 - reading SPP_STR does it...
287 * SMC - write 1 to EPP timeout bit XXX
288 * Others - (?) write 0 to EPP timeout bit
291 ppc_reset_epp_timeout(struct ppc_data *ppc)
297 w_str(ppc, r & 0xfe);
303 ppc_check_epp_timeout(struct ppc_data *ppc)
305 ppc_reset_epp_timeout(ppc);
307 return (!(r_str(ppc) & TIMEOUT));
311 * Configure current operating mode
314 ppc_generic_setmode(struct ppc_data *ppc, int mode)
318 /* check if mode is available */
319 if (mode && !(ppc->ppc_avm & mode))
322 /* if ECP mode, configure ecr register */
323 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
324 /* return to byte mode (keeping direction bit),
325 * no interrupt, no DMA to be able to change to
328 w_ecr(ppc, PPC_ECR_RESET);
329 ecr = PPC_DISABLE_INTR;
333 else if (mode & PPB_ECP)
334 /* select ECP mode */
336 else if (mode & PPB_PS2)
337 /* select PS2 mode with ECP */
340 /* select COMPATIBLE/NIBBLE mode */
346 ppc->ppc_mode = mode;
352 * The ppc driver is free to choose options like FIFO or DMA
353 * if ECP mode is available.
355 * The 'RAW' option allows the upper drivers to force the ppc mode
356 * even with FIFO, DMA available.
359 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
363 /* check if mode is available */
364 if (mode && !(ppc->ppc_avm & mode))
367 /* if ECP mode, configure ecr register */
368 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
369 /* return to byte mode (keeping direction bit),
370 * no interrupt, no DMA to be able to change to
373 w_ecr(ppc, PPC_ECR_RESET);
374 ecr = PPC_DISABLE_INTR;
377 /* select EPP mode */
379 else if (mode & PPB_ECP)
380 /* select ECP mode */
382 else if (mode & PPB_PS2)
383 /* select PS2 mode with ECP */
386 /* select COMPATIBLE/NIBBLE mode */
392 ppc->ppc_mode = mode;
397 #ifdef PPC_PROBE_CHIPSET
401 * Probe for a Natsemi PC873xx-family part.
403 * References in this function are to the National Semiconductor
404 * PC87332 datasheet TL/C/11930, May 1995 revision.
406 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
407 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
408 static int pc873xx_irqtab[] = {5, 7, 5, 0};
410 static int pc873xx_regstab[] = {
411 PC873_FER, PC873_FAR, PC873_PTR,
412 PC873_FCR, PC873_PCR, PC873_PMC,
413 PC873_TUP, PC873_SID, PC873_PNP0,
414 PC873_PNP1, PC873_LPTBA, -1
417 static char *pc873xx_rnametab[] = {
418 "FER", "FAR", "PTR", "FCR", "PCR",
419 "PMC", "TUP", "SID", "PNP0", "PNP1",
424 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
426 static int index = 0;
428 int ptr, pcr, val, i;
430 while ((idport = pc873xx_basetab[index++])) {
432 /* XXX should check first to see if this location is already claimed */
435 * Pull the 873xx through the power-on ID cycle (2.2,1.).
436 * We can't use this to locate the chip as it may already have
437 * been used by the BIOS.
439 (void)inb(idport); (void)inb(idport);
440 (void)inb(idport); (void)inb(idport);
443 * Read the SID byte. Possible values are :
450 outb(idport, PC873_SID);
451 val = inb(idport + 1);
452 if ((val & 0xf0) == 0x10) {
453 ppc->ppc_model = NS_PC87332;
454 } else if ((val & 0xf8) == 0x70) {
455 ppc->ppc_model = NS_PC87306;
456 } else if ((val & 0xf8) == 0x50) {
457 ppc->ppc_model = NS_PC87334;
458 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
459 documentation, but probing
461 ppc->ppc_model = NS_PC87303;
463 if (bootverbose && (val != 0xff))
464 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
465 continue ; /* not recognised */
468 /* print registers */
471 for (i=0; pc873xx_regstab[i] != -1; i++) {
472 outb(idport, pc873xx_regstab[i]);
473 printf(" %s=0x%x", pc873xx_rnametab[i],
474 inb(idport + 1) & 0xff);
480 * We think we have one. Is it enabled and where we want it to be?
482 outb(idport, PC873_FER);
483 val = inb(idport + 1);
484 if (!(val & PC873_PPENABLE)) {
486 printf("PC873xx parallel port disabled\n");
489 outb(idport, PC873_FAR);
490 val = inb(idport + 1);
491 /* XXX we should create a driver instance for every port found */
492 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
494 /* First try to change the port address to that requested... */
496 switch (ppc->ppc_base) {
514 outb(idport, PC873_FAR);
515 outb(idport + 1, val);
516 outb(idport + 1, val);
518 /* Check for success by reading back the value we supposedly
519 wrote and comparing...*/
521 outb(idport, PC873_FAR);
522 val = inb(idport + 1) & 0x3;
524 /* If we fail, report the failure... */
526 if (pc873xx_porttab[val] != ppc->ppc_base) {
528 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
529 pc873xx_porttab[val], ppc->ppc_base);
534 outb(idport, PC873_PTR);
535 ptr = inb(idport + 1);
537 /* get irq settings */
538 if (ppc->ppc_base == 0x378)
539 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
541 irq = pc873xx_irqtab[val];
544 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
547 * Check if irq settings are correct
549 if (irq != ppc->ppc_irq) {
551 * If the chipset is not locked and base address is 0x378,
552 * we have another chance
554 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
555 if (ppc->ppc_irq == 7) {
556 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
557 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
559 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
560 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
563 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
566 printf("PC873xx sorry, can't change irq setting\n");
570 printf("PC873xx irq settings are correct\n");
573 outb(idport, PC873_PCR);
574 pcr = inb(idport + 1);
576 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
578 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
580 ppc->ppc_avm |= PPB_NIBBLE;
584 if (pcr & PC873_EPPEN) {
585 ppc->ppc_avm |= PPB_EPP;
590 if (pcr & PC873_EPP19)
591 ppc->ppc_epp = EPP_1_9;
593 ppc->ppc_epp = EPP_1_7;
595 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
596 outb(idport, PC873_PTR);
597 ptr = inb(idport + 1);
598 if (ptr & PC873_EPPRDIR)
599 printf(", Regular mode");
601 printf(", Automatic mode");
603 } else if (pcr & PC873_ECPEN) {
604 ppc->ppc_avm |= PPB_ECP;
608 if (pcr & PC873_ECPCLK) { /* XXX */
609 ppc->ppc_avm |= PPB_PS2;
614 outb(idport, PC873_PTR);
615 ptr = inb(idport + 1);
616 if (ptr & PC873_EXTENDED) {
617 ppc->ppc_avm |= PPB_SPP;
624 printf("PC873xx unlocked");
626 if (chipset_mode & PPB_ECP) {
627 if ((chipset_mode & PPB_EPP) && bootverbose)
628 printf(", ECP+EPP not supported");
631 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
632 outb(idport + 1, pcr);
633 outb(idport + 1, pcr);
638 } else if (chipset_mode & PPB_EPP) {
639 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
640 pcr |= (PC873_EPPEN | PC873_EPP19);
641 outb(idport + 1, pcr);
642 outb(idport + 1, pcr);
644 ppc->ppc_epp = EPP_1_9; /* XXX */
649 /* enable automatic direction turnover */
650 if (ppc->ppc_model == NS_PC87332) {
651 outb(idport, PC873_PTR);
652 ptr = inb(idport + 1);
653 ptr &= ~PC873_EPPRDIR;
654 outb(idport + 1, ptr);
655 outb(idport + 1, ptr);
658 printf(", Automatic mode");
661 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
662 outb(idport + 1, pcr);
663 outb(idport + 1, pcr);
665 /* configure extended bit in PTR */
666 outb(idport, PC873_PTR);
667 ptr = inb(idport + 1);
669 if (chipset_mode & PPB_PS2) {
670 ptr |= PC873_EXTENDED;
676 /* default to NIBBLE mode */
677 ptr &= ~PC873_EXTENDED;
682 outb(idport + 1, ptr);
683 outb(idport + 1, ptr);
686 ppc->ppc_avm = chipset_mode;
692 ppc->ppc_type = PPC_TYPE_GENERIC;
693 ppc_generic_setmode(ppc, chipset_mode);
695 return(chipset_mode);
701 * ppc_smc37c66xgt_detect
703 * SMC FDC37C66xGT configuration.
706 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
711 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
713 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
716 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
719 * Detection: enter configuration mode and read CRD register.
721 PPC_CONFIG_LOCK(ppc);
722 outb(csr, SMC665_iCODE);
723 outb(csr, SMC665_iCODE);
724 PPC_CONFIG_UNLOCK(ppc);
727 if (inb(cio) == 0x65) {
732 for (i = 0; i < 2; i++) {
733 PPC_CONFIG_LOCK(ppc);
734 outb(csr, SMC666_iCODE);
735 outb(csr, SMC666_iCODE);
736 PPC_CONFIG_UNLOCK(ppc);
739 if (inb(cio) == 0x66) {
744 /* Another chance, CSR may be hard-configured to be at 0x370 */
750 * If chipset not found, do not continue.
753 outb(csr, 0xaa); /* end config mode */
760 /* read the port's address: bits 0 and 1 of CR1 */
761 r = inb(cio) & SMC_CR1_ADDR;
762 if (port_address[(int)r] != ppc->ppc_base) {
763 outb(csr, 0xaa); /* end config mode */
767 ppc->ppc_model = type;
770 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
771 * If SPP mode is detected, try to set ECP+EPP mode
776 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
780 printf(" CR4=0x%x", inb(cio) & 0xff);
787 /* autodetect mode */
789 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
790 if (type == SMC_37C666GT) {
791 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
793 printf(" configuration hardwired, supposing " \
797 if ((inb(cio) & SMC_CR1_MODE) == 0) {
798 /* already in extended parallel port mode, read CR4 */
800 r = (inb(cio) & SMC_CR4_EMODE);
804 ppc->ppc_avm |= PPB_SPP;
810 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
816 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
822 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
824 printf(" ECP+EPP SPP");
828 /* not an extended port mode */
829 ppc->ppc_avm |= PPB_SPP;
836 ppc->ppc_avm = chipset_mode;
838 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
839 if (type == SMC_37C666GT)
843 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
844 /* do not use ECP when the mode is not forced to */
845 outb(cio, r | SMC_CR1_MODE);
849 /* an extended mode is selected */
850 outb(cio, r & ~SMC_CR1_MODE);
852 /* read CR4 register and reset mode field */
854 r = inb(cio) & ~SMC_CR4_EMODE;
856 if (chipset_mode & PPB_ECP) {
857 if (chipset_mode & PPB_EPP) {
858 outb(cio, r | SMC_ECPEPP);
862 outb(cio, r | SMC_ECP);
868 outb(cio, r | SMC_EPPSPP);
873 ppc->ppc_avm = chipset_mode;
876 /* set FIFO threshold to 16 */
877 if (ppc->ppc_avm & PPB_ECP) {
888 if (ppc->ppc_avm & PPB_EPP) {
894 * Set the EPP protocol...
895 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
897 if (ppc->ppc_epp == EPP_1_9)
898 outb(cio, (r & ~SMC_CR4_EPPTYPE));
900 outb(cio, (r | SMC_CR4_EPPTYPE));
903 outb(csr, 0xaa); /* end config mode */
905 ppc->ppc_type = PPC_TYPE_SMCLIKE;
906 ppc_smclike_setmode(ppc, chipset_mode);
908 return (chipset_mode);
912 * SMC FDC37C935 configuration
913 * Found on many Alpha machines
916 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
920 PPC_CONFIG_LOCK(ppc);
921 outb(SMC935_CFG, 0x55); /* enter config mode */
922 outb(SMC935_CFG, 0x55);
923 PPC_CONFIG_UNLOCK(ppc);
925 outb(SMC935_IND, SMC935_ID); /* check device id */
926 if (inb(SMC935_DAT) == 0x2)
930 outb(SMC935_CFG, 0xaa); /* exit config mode */
934 ppc->ppc_model = type;
936 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
937 outb(SMC935_DAT, 3); /* which is logical device 3 */
939 /* set io port base */
940 outb(SMC935_IND, SMC935_PORTHI);
941 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
942 outb(SMC935_IND, SMC935_PORTLO);
943 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
946 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
948 ppc->ppc_avm = chipset_mode;
949 outb(SMC935_IND, SMC935_PPMODE);
950 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
952 /* SPP + EPP or just plain SPP */
953 if (chipset_mode & (PPB_SPP)) {
954 if (chipset_mode & PPB_EPP) {
955 if (ppc->ppc_epp == EPP_1_9) {
956 outb(SMC935_IND, SMC935_PPMODE);
957 outb(SMC935_DAT, SMC935_EPP19SPP);
959 if (ppc->ppc_epp == EPP_1_7) {
960 outb(SMC935_IND, SMC935_PPMODE);
961 outb(SMC935_DAT, SMC935_EPP17SPP);
964 outb(SMC935_IND, SMC935_PPMODE);
965 outb(SMC935_DAT, SMC935_SPP);
969 /* ECP + EPP or just plain ECP */
970 if (chipset_mode & PPB_ECP) {
971 if (chipset_mode & PPB_EPP) {
972 if (ppc->ppc_epp == EPP_1_9) {
973 outb(SMC935_IND, SMC935_PPMODE);
974 outb(SMC935_DAT, SMC935_ECPEPP19);
976 if (ppc->ppc_epp == EPP_1_7) {
977 outb(SMC935_IND, SMC935_PPMODE);
978 outb(SMC935_DAT, SMC935_ECPEPP17);
981 outb(SMC935_IND, SMC935_PPMODE);
982 outb(SMC935_DAT, SMC935_ECP);
987 outb(SMC935_CFG, 0xaa); /* exit config mode */
989 ppc->ppc_type = PPC_TYPE_SMCLIKE;
990 ppc_smclike_setmode(ppc, chipset_mode);
992 return (chipset_mode);
996 * Winbond W83877F stuff
998 * EFER: extended function enable register
999 * EFIR: extended function index register
1000 * EFDR: extended function data register
1002 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1003 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1005 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1006 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1007 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1008 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1011 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1014 unsigned char r, hefere, hefras;
1016 for (i = 0; i < 4; i ++) {
1017 /* first try to enable configuration registers */
1018 efer = w83877f_efers[i];
1020 /* write the key to the EFER */
1021 for (j = 0; j < w83877f_keyiter[i]; j ++)
1022 outb (efer, w83877f_keys[i]);
1024 /* then check HEFERE and HEFRAS bits */
1026 hefere = inb(efdr) & WINB_HEFERE;
1029 hefras = inb(efdr) & WINB_HEFRAS;
1033 * 0 1 write 89h to 250h (power-on default)
1034 * 1 0 write 86h twice to 3f0h
1035 * 1 1 write 87h twice to 3f0h
1036 * 0 0 write 88h to 250h
1038 if ((hefere | hefras) == w83877f_hefs[i])
1042 return (-1); /* failed */
1045 /* check base port address - read from CR23 */
1047 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1050 /* read CHIP ID from CR9/bits0-3 */
1053 switch (inb(efdr) & WINB_CHIPID) {
1054 case WINB_W83877F_ID:
1055 ppc->ppc_model = WINB_W83877F;
1058 case WINB_W83877AF_ID:
1059 ppc->ppc_model = WINB_W83877AF;
1063 ppc->ppc_model = WINB_UNKNOWN;
1067 /* dump of registers */
1068 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1069 for (i = 0; i <= 0xd; i ++) {
1071 printf("0x%x ", inb(efdr));
1073 for (i = 0x10; i <= 0x17; i ++) {
1075 printf("0x%x ", inb(efdr));
1078 printf("0x%x ", inb(efdr));
1079 for (i = 0x20; i <= 0x29; i ++) {
1081 printf("0x%x ", inb(efdr));
1086 ppc->ppc_type = PPC_TYPE_GENERIC;
1088 if (!chipset_mode) {
1089 /* autodetect mode */
1093 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1097 r |= (inb(efdr) & WINB_PRTMODS2);
1102 device_printf(ppc->ppc_dev,
1103 "W83757 compatible mode\n");
1104 return (-1); /* generic or SMC-like */
1111 device_printf(ppc->ppc_dev,
1112 "not in parallel port mode\n");
1115 case (WINB_PARALLEL | WINB_EPP_SPP):
1116 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1118 device_printf(ppc->ppc_dev, "EPP SPP\n");
1121 case (WINB_PARALLEL | WINB_ECP):
1122 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1124 device_printf(ppc->ppc_dev, "ECP SPP\n");
1127 case (WINB_PARALLEL | WINB_ECP_EPP):
1128 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1129 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1132 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1135 printf("%s: unknown case (0x%x)!\n", __func__, r);
1141 /* select CR9 and set PRTMODS2 bit */
1143 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1145 /* select CR0 and reset PRTMODSx bits */
1147 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1149 if (chipset_mode & PPB_ECP) {
1150 if (chipset_mode & PPB_EPP) {
1151 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1153 device_printf(ppc->ppc_dev,
1156 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1159 outb(efdr, inb(efdr) | WINB_ECP);
1161 device_printf(ppc->ppc_dev, "ECP\n");
1164 /* select EPP_SPP otherwise */
1165 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1167 device_printf(ppc->ppc_dev, "EPP SPP\n");
1169 ppc->ppc_avm = chipset_mode;
1172 /* exit configuration mode */
1175 switch (ppc->ppc_type) {
1176 case PPC_TYPE_SMCLIKE:
1177 ppc_smclike_setmode(ppc, chipset_mode);
1180 ppc_generic_setmode(ppc, chipset_mode);
1184 return (chipset_mode);
1189 * ppc_generic_detect
1192 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1194 /* default to generic */
1195 ppc->ppc_type = PPC_TYPE_GENERIC;
1198 device_printf(ppc->ppc_dev, "SPP");
1200 /* first, check for ECP */
1201 w_ecr(ppc, PPC_ECR_PS2);
1202 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1203 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1207 /* search for SMC style ECP+EPP mode */
1208 w_ecr(ppc, PPC_ECR_EPP);
1211 /* try to reset EPP timeout bit */
1212 if (ppc_check_epp_timeout(ppc)) {
1213 ppc->ppc_dtm |= PPB_EPP;
1215 if (ppc->ppc_dtm & PPB_ECP) {
1216 /* SMC like chipset found */
1217 ppc->ppc_model = SMC_LIKE;
1218 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1227 /* restore to standard mode */
1228 w_ecr(ppc, PPC_ECR_STD);
1231 /* XXX try to detect NIBBLE and PS2 modes */
1232 ppc->ppc_dtm |= PPB_NIBBLE;
1235 ppc->ppc_avm = chipset_mode;
1237 ppc->ppc_avm = ppc->ppc_dtm;
1242 switch (ppc->ppc_type) {
1243 case PPC_TYPE_SMCLIKE:
1244 ppc_smclike_setmode(ppc, chipset_mode);
1247 ppc_generic_setmode(ppc, chipset_mode);
1251 return (chipset_mode);
1257 * mode is the mode suggested at boot
1260 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1262 #ifdef PPC_PROBE_CHIPSET
1265 /* list of supported chipsets */
1266 int (*chipset_detect[])(struct ppc_data *, int) = {
1268 ppc_smc37c66xgt_detect,
1270 ppc_smc37c935_detect,
1276 /* if can't find the port and mode not forced return error */
1277 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1278 return (EIO); /* failed, port not present */
1280 /* assume centronics compatible mode is supported */
1281 ppc->ppc_avm = PPB_COMPATIBLE;
1283 #ifdef PPC_PROBE_CHIPSET
1284 /* we have to differenciate available chipset modes,
1285 * chipset running modes and IEEE-1284 operating modes
1287 * after detection, the port must support running in compatible mode
1289 if (ppc->ppc_flags & 0x40) {
1291 printf("ppc: chipset forced to generic\n");
1294 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1296 #ifdef PPC_PROBE_CHIPSET
1298 for (i=0; chipset_detect[i] != NULL; i++) {
1299 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1300 ppc->ppc_mode = mode;
1307 /* configure/detect ECP FIFO */
1308 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1309 ppc_detect_fifo(ppc);
1315 * ppc_exec_microseq()
1317 * Execute a microsequence.
1318 * Microsequence mechanism is supposed to handle fast I/O operations.
1321 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1323 struct ppc_data *ppc = DEVTOSOFTC(dev);
1324 struct ppb_microseq *mi;
1331 register int accum = 0;
1332 register char *ptr = 0;
1334 struct ppb_microseq *stack = 0;
1336 /* microsequence registers are equivalent to PC-like port registers */
1338 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1339 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1341 #define INCR_PC (mi ++) /* increment program counter */
1343 PPC_ASSERT_LOCKED(ppc);
1346 switch (mi->opcode) {
1348 cc = r_reg(mi->arg[0].i, ppc);
1349 cc &= (char)mi->arg[2].i; /* clear mask */
1350 cc |= (char)mi->arg[1].i; /* assert mask */
1351 w_reg(mi->arg[0].i, ppc, cc);
1355 case MS_OP_RASSERT_P:
1359 if ((len = mi->arg[0].i) == MS_ACCUM) {
1360 accum = ppc->ppc_accum;
1361 for (; accum; accum--)
1362 w_reg(reg, ppc, *ptr++);
1363 ppc->ppc_accum = accum;
1365 for (i=0; i<len; i++)
1366 w_reg(reg, ppc, *ptr++);
1372 case MS_OP_RFETCH_P:
1374 mask = (char)mi->arg[2].i;
1377 if ((len = mi->arg[0].i) == MS_ACCUM) {
1378 accum = ppc->ppc_accum;
1379 for (; accum; accum--)
1380 *ptr++ = r_reg(reg, ppc) & mask;
1381 ppc->ppc_accum = accum;
1383 for (i=0; i<len; i++)
1384 *ptr++ = r_reg(reg, ppc) & mask;
1391 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1399 /* let's suppose the next instr. is the same */
1401 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1402 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1404 if (mi->opcode == MS_OP_DELAY) {
1405 DELAY(mi->arg[0].i);
1414 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1422 iter = mi->arg[1].i;
1423 p = (char *)mi->arg[2].p;
1425 /* XXX delay limited to 255 us */
1426 for (i=0; i<iter; i++) {
1427 w_reg(reg, ppc, *p++);
1428 DELAY((unsigned char)*p++);
1434 ppc->ppc_accum = mi->arg[0].i;
1439 if (--ppc->ppc_accum > 0)
1446 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1453 if ((cc & (char)mi->arg[0].i) == 0)
1460 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1468 * If the C call returns !0 then end the microseq.
1469 * The current state of ptr is passed to the C function
1471 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1478 ppc->ppc_ptr = (char *)mi->arg[0].p;
1484 panic("%s: too much calls", __func__);
1487 /* store the state of the actual
1492 /* jump to the new microsequence */
1493 mi = (struct ppb_microseq *)mi->arg[0].p;
1500 /* retrieve microseq and pc state before the call */
1503 /* reset the stack */
1506 /* XXX return code */
1514 /* can't return to ppb level during the execution
1515 * of a submicrosequence */
1517 panic("%s: can't return to ppb level",
1520 /* update pc for ppb level of execution */
1523 /* return to ppb level of execution */
1527 panic("%s: unknown microsequence opcode 0x%x",
1528 __func__, mi->opcode);
1538 struct ppc_data *ppc = arg;
1539 u_char ctr, ecr, str;
1542 * If we have any child interrupt handlers registered, let
1543 * them handle this interrupt.
1545 * XXX: If DMA is in progress should we just complete that w/o
1549 if (ppc->ppc_intr_hook != NULL &&
1550 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1559 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1560 printf("![%x/%x/%x]", ctr, ecr, str);
1563 /* don't use ecp mode with IRQENABLE set */
1564 if (ctr & IRQENABLE) {
1569 /* interrupts are generated by nFault signal
1570 * only in ECP mode */
1571 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1572 /* check if ppc driver has programmed the
1573 * nFault interrupt */
1574 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1576 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1577 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1579 /* shall be handled by underlying layers XXX */
1585 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1586 /* disable interrupts (should be done by hardware though) */
1587 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1588 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1591 /* check if DMA completed */
1592 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1597 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1600 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1604 ppc->ppc_dmadone(ppc);
1605 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1607 /* wakeup the waiting process */
1611 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1613 /* classic interrupt I/O */
1614 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1622 ppc_read(device_t dev, char *buf, int len, int mode)
1628 ppc_write(device_t dev, char *buf, int len, int how)
1634 ppc_reset_epp(device_t dev)
1636 struct ppc_data *ppc = DEVTOSOFTC(dev);
1638 PPC_ASSERT_LOCKED(ppc);
1639 ppc_reset_epp_timeout(ppc);
1645 ppc_setmode(device_t dev, int mode)
1647 struct ppc_data *ppc = DEVTOSOFTC(dev);
1649 PPC_ASSERT_LOCKED(ppc);
1650 switch (ppc->ppc_type) {
1651 case PPC_TYPE_SMCLIKE:
1652 return (ppc_smclike_setmode(ppc, mode));
1655 case PPC_TYPE_GENERIC:
1657 return (ppc_generic_setmode(ppc, mode));
1666 ppc_probe(device_t dev, int rid)
1669 static short next_bios_ppc = 0;
1671 unsigned int pc98_ieee_mode = 0x00;
1675 struct ppc_data *ppc;
1680 * Allocate the ppc_data structure.
1682 ppc = DEVTOSOFTC(dev);
1683 bzero(ppc, sizeof(struct ppc_data));
1685 ppc->rid_ioport = rid;
1687 /* retrieve ISA parameters */
1688 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1692 * If port not specified, use bios list.
1696 if (next_bios_ppc == 0) {
1697 /* Use default IEEE-1284 port of NEC PC-98x1 */
1698 port = PC98_IEEE_1284_PORT;
1702 "parallel port found at 0x%lx\n", port);
1705 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1706 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1707 port = *(BIOS_PORTS + next_bios_ppc++);
1710 "parallel port found at 0x%lx\n", port);
1712 device_printf(dev, "parallel port not found.\n");
1716 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1717 IO_LPTSIZE_EXTENDED);
1721 /* IO port is mandatory */
1723 /* Try "extended" IO port range...*/
1724 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1725 &ppc->rid_ioport, 0, ~0,
1726 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1728 if (ppc->res_ioport != 0) {
1730 device_printf(dev, "using extended I/O port range\n");
1732 /* Failed? If so, then try the "normal" IO port range... */
1733 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1734 &ppc->rid_ioport, 0, ~0,
1737 if (ppc->res_ioport != 0) {
1739 device_printf(dev, "using normal I/O port range\n");
1741 device_printf(dev, "cannot reserve I/O port range\n");
1746 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1748 ppc->ppc_flags = device_get_flags(dev);
1750 if (!(ppc->ppc_flags & 0x20)) {
1751 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1754 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1760 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1762 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1765 ppc->ppc_model = GENERIC;
1767 ppc->ppc_mode = PPB_COMPATIBLE;
1768 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1770 ppc->ppc_type = PPC_TYPE_GENERIC;
1772 #if defined(__i386__) && defined(PC98)
1774 * IEEE STD 1284 Function Check and Enable
1775 * for default IEEE-1284 port of NEC PC-98x1
1777 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1778 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1779 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1780 pc98_ieee_mode = tmp;
1781 if ((tmp & 0x10) == 0x10) {
1782 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1783 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1784 if ((tmp & 0x10) == 0x10)
1787 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1788 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1789 if ((tmp & 0x10) != 0x10)
1792 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1797 * Try to detect the chipset and its mode.
1799 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1805 #if defined(__i386__) && defined(PC98)
1806 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1807 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1808 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1811 if (ppc->res_irq != 0) {
1812 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1815 if (ppc->res_ioport != 0) {
1816 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1819 if (ppc->res_drq != 0) {
1820 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1827 ppc_attach(device_t dev)
1829 struct ppc_data *ppc = DEVTOSOFTC(dev);
1832 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1834 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1835 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1836 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1837 ppc_epp_protocol[ppc->ppc_epp] : "");
1840 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1841 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1844 /* default to the tty mask for registration */ /* XXX */
1845 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1846 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1849 "failed to register interrupt handler: %d\n",
1851 mtx_destroy(&ppc->ppc_lock);
1856 /* add ppbus as a child of this isa to parallel bridge */
1857 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1860 * Probe the ppbus and attach devices found.
1862 device_probe_and_attach(ppc->ppbus);
1868 ppc_detach(device_t dev)
1870 struct ppc_data *ppc = DEVTOSOFTC(dev);
1872 if (ppc->res_irq == 0) {
1876 /* detach & delete all children */
1877 device_delete_children(dev);
1879 if (ppc->res_irq != 0) {
1880 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1881 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1884 if (ppc->res_ioport != 0) {
1885 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1888 if (ppc->res_drq != 0) {
1889 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1893 mtx_destroy(&ppc->ppc_lock);
1899 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1901 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1903 PPC_ASSERT_LOCKED(ppc);
1906 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1909 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1912 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1915 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1918 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1921 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1924 return (r_dtr(ppc));
1926 return (r_str(ppc));
1928 return (r_ctr(ppc));
1930 return (r_epp_A(ppc));
1932 return (r_epp_D(ppc));
1934 return (r_ecr(ppc));
1936 return (r_fifo(ppc));
1959 panic("%s: unknown I/O operation", __func__);
1963 return (0); /* not significative */
1967 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1969 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1972 case PPC_IVAR_EPP_PROTO:
1973 PPC_ASSERT_LOCKED(ppc);
1974 *val = (u_long)ppc->ppc_epp;
1977 *val = (uintptr_t)&ppc->ppc_lock;
1987 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1989 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1992 case PPC_IVAR_INTR_HANDLER:
1993 PPC_ASSERT_LOCKED(ppc);
1994 if (dev != ppc->ppbus)
1997 ppc->ppc_intr_hook = NULL;
2000 if (ppc->ppc_intr_hook != NULL)
2002 ppc->ppc_intr_hook = (void *)val;
2003 ppc->ppc_intr_arg = device_get_softc(dev);
2013 * We allow child devices to allocate an IRQ resource at rid 0 for their
2014 * interrupt handlers.
2017 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
2018 u_long start, u_long end, u_long count, u_int flags)
2020 struct ppc_data *ppc = DEVTOSOFTC(bus);
2025 return (ppc->res_irq);
2032 ppc_release_resource(device_t bus, device_t child, int type, int rid,
2036 struct ppc_data *ppc = DEVTOSOFTC(bus);
2042 KASSERT(r == ppc->res_irq,
2043 ("ppc child IRQ resource mismatch"));
2051 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);