2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/mutex.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
53 #include <machine/vmparam.h>
56 #include <dev/ppbus/ppbconf.h>
57 #include <dev/ppbus/ppb_msq.h>
59 #include <dev/ppc/ppcvar.h>
60 #include <dev/ppc/ppcreg.h>
64 static void ppcintr(void *arg);
66 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
67 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
69 #define LOG_PPC(function, ppc, string) \
70 if (bootverbose) printf("%s: %s\n", function, string)
72 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
75 * We use critical enter/exit for the simple config locking needed to
76 * detect the devices. We just want to make sure that both of our writes
77 * happen without someone else also writing to those config registers. Since
78 * we just do this at startup, Giant keeps multiple threads from executing,
79 * and critical_enter() then is all that's needed to keep us from being preempted
80 * during the critical sequences with the hardware.
82 * Note: this doesn't prevent multiple threads from putting the chips into
83 * config mode, but since we only do that to detect the type at startup the
84 * extra overhead isn't needed since Giant protects us from multiple entry
85 * and no other code changes these registers.
87 #define PPC_CONFIG_LOCK(ppc) critical_enter()
88 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
90 devclass_t ppc_devclass;
91 const char ppc_driver_name[] = "ppc";
93 static char *ppc_models[] = {
94 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
95 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
96 "SMC FDC37C935", "PC87303", 0
99 /* list of available modes */
100 static char *ppc_avms[] = {
101 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
102 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
103 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
104 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
107 /* list of current executing modes
108 * Note that few modes do not actually exist.
110 static char *ppc_modes[] = {
111 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
112 "EPP", "EPP", "EPP", "ECP",
113 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
114 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
117 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
121 * BIOS printer list - used by BIOS probe.
123 #define BIOS_PPC_PORTS 0x408
124 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
125 #define BIOS_MAX_PPC 4
132 ppc_ecp_sync(device_t dev)
135 struct ppc_data *ppc = DEVTOSOFTC(dev);
137 PPC_ASSERT_LOCKED(ppc);
138 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
142 if ((r & 0xe0) != PPC_ECR_EPP)
145 for (i = 0; i < 100; i++) {
152 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
160 * Detect parallel port FIFO
163 ppc_detect_fifo(struct ppc_data *ppc)
166 char ctr_sav, ctr, cc;
170 ecr_sav = r_ecr(ppc);
171 ctr_sav = r_ctr(ppc);
173 /* enter ECP configuration mode, no interrupt, no DMA */
176 /* read PWord size - transfers in FIFO mode must be PWord aligned */
177 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
179 /* XXX 16 and 32 bits implementations not supported */
180 if (ppc->ppc_pword != PPC_PWORD_8) {
181 LOG_PPC(__func__, ppc, "PWord not supported");
185 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
187 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
189 /* enter ECP test mode, no interrupt, no DMA */
193 for (i=0; i<1024; i++) {
194 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
200 LOG_PPC(__func__, ppc, "can't flush FIFO");
204 /* enable interrupts, no DMA */
207 /* determine readIntrThreshold
208 * fill the FIFO until serviceIntr is set
210 for (i=0; i<1024; i++) {
211 w_fifo(ppc, (char)i);
212 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
213 /* readThreshold reached */
216 if (r_ecr(ppc) & PPC_FIFO_FULL) {
223 LOG_PPC(__func__, ppc, "can't fill FIFO");
227 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
228 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
229 w_ecr(ppc, 0xd0); /* enable interrupts */
231 /* determine writeIntrThreshold
232 * empty the FIFO until serviceIntr is set
234 for (i=ppc->ppc_fifo; i>0; i--) {
235 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
236 LOG_PPC(__func__, ppc, "invalid data in FIFO");
239 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
240 /* writeIntrThreshold reached */
241 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
243 /* if FIFO empty before the last byte, error */
244 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
245 LOG_PPC(__func__, ppc, "data lost in FIFO");
250 /* FIFO must be empty after the last byte */
251 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
252 LOG_PPC(__func__, ppc, "can't empty the FIFO");
269 ppc_detect_port(struct ppc_data *ppc)
272 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
274 if (r_dtr(ppc) != 0xaa)
281 * EPP timeout, according to the PC87332 manual
282 * Semantics of clearing EPP timeout bit.
283 * PC87332 - reading SPP_STR does it...
284 * SMC - write 1 to EPP timeout bit XXX
285 * Others - (?) write 0 to EPP timeout bit
288 ppc_reset_epp_timeout(struct ppc_data *ppc)
294 w_str(ppc, r & 0xfe);
300 ppc_check_epp_timeout(struct ppc_data *ppc)
302 ppc_reset_epp_timeout(ppc);
304 return (!(r_str(ppc) & TIMEOUT));
308 * Configure current operating mode
311 ppc_generic_setmode(struct ppc_data *ppc, int mode)
315 /* check if mode is available */
316 if (mode && !(ppc->ppc_avm & mode))
319 /* if ECP mode, configure ecr register */
320 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
321 /* return to byte mode (keeping direction bit),
322 * no interrupt, no DMA to be able to change to
325 w_ecr(ppc, PPC_ECR_RESET);
326 ecr = PPC_DISABLE_INTR;
330 else if (mode & PPB_ECP)
331 /* select ECP mode */
333 else if (mode & PPB_PS2)
334 /* select PS2 mode with ECP */
337 /* select COMPATIBLE/NIBBLE mode */
343 ppc->ppc_mode = mode;
349 * The ppc driver is free to choose options like FIFO or DMA
350 * if ECP mode is available.
352 * The 'RAW' option allows the upper drivers to force the ppc mode
353 * even with FIFO, DMA available.
356 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
360 /* check if mode is available */
361 if (mode && !(ppc->ppc_avm & mode))
364 /* if ECP mode, configure ecr register */
365 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
366 /* return to byte mode (keeping direction bit),
367 * no interrupt, no DMA to be able to change to
370 w_ecr(ppc, PPC_ECR_RESET);
371 ecr = PPC_DISABLE_INTR;
374 /* select EPP mode */
376 else if (mode & PPB_ECP)
377 /* select ECP mode */
379 else if (mode & PPB_PS2)
380 /* select PS2 mode with ECP */
383 /* select COMPATIBLE/NIBBLE mode */
389 ppc->ppc_mode = mode;
394 #ifdef PPC_PROBE_CHIPSET
398 * Probe for a Natsemi PC873xx-family part.
400 * References in this function are to the National Semiconductor
401 * PC87332 datasheet TL/C/11930, May 1995 revision.
403 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
404 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
405 static int pc873xx_irqtab[] = {5, 7, 5, 0};
407 static int pc873xx_regstab[] = {
408 PC873_FER, PC873_FAR, PC873_PTR,
409 PC873_FCR, PC873_PCR, PC873_PMC,
410 PC873_TUP, PC873_SID, PC873_PNP0,
411 PC873_PNP1, PC873_LPTBA, -1
414 static char *pc873xx_rnametab[] = {
415 "FER", "FAR", "PTR", "FCR", "PCR",
416 "PMC", "TUP", "SID", "PNP0", "PNP1",
421 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
423 static int index = 0;
425 int ptr, pcr, val, i;
427 while ((idport = pc873xx_basetab[index++])) {
429 /* XXX should check first to see if this location is already claimed */
432 * Pull the 873xx through the power-on ID cycle (2.2,1.).
433 * We can't use this to locate the chip as it may already have
434 * been used by the BIOS.
436 (void)inb(idport); (void)inb(idport);
437 (void)inb(idport); (void)inb(idport);
440 * Read the SID byte. Possible values are :
447 outb(idport, PC873_SID);
448 val = inb(idport + 1);
449 if ((val & 0xf0) == 0x10) {
450 ppc->ppc_model = NS_PC87332;
451 } else if ((val & 0xf8) == 0x70) {
452 ppc->ppc_model = NS_PC87306;
453 } else if ((val & 0xf8) == 0x50) {
454 ppc->ppc_model = NS_PC87334;
455 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
456 documentation, but probing
458 ppc->ppc_model = NS_PC87303;
460 if (bootverbose && (val != 0xff))
461 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
462 continue ; /* not recognised */
465 /* print registers */
468 for (i=0; pc873xx_regstab[i] != -1; i++) {
469 outb(idport, pc873xx_regstab[i]);
470 printf(" %s=0x%x", pc873xx_rnametab[i],
471 inb(idport + 1) & 0xff);
477 * We think we have one. Is it enabled and where we want it to be?
479 outb(idport, PC873_FER);
480 val = inb(idport + 1);
481 if (!(val & PC873_PPENABLE)) {
483 printf("PC873xx parallel port disabled\n");
486 outb(idport, PC873_FAR);
487 val = inb(idport + 1);
488 /* XXX we should create a driver instance for every port found */
489 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
491 /* First try to change the port address to that requested... */
493 switch (ppc->ppc_base) {
511 outb(idport, PC873_FAR);
512 outb(idport + 1, val);
513 outb(idport + 1, val);
515 /* Check for success by reading back the value we supposedly
516 wrote and comparing...*/
518 outb(idport, PC873_FAR);
519 val = inb(idport + 1) & 0x3;
521 /* If we fail, report the failure... */
523 if (pc873xx_porttab[val] != ppc->ppc_base) {
525 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
526 pc873xx_porttab[val], ppc->ppc_base);
531 outb(idport, PC873_PTR);
532 ptr = inb(idport + 1);
534 /* get irq settings */
535 if (ppc->ppc_base == 0x378)
536 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
538 irq = pc873xx_irqtab[val];
541 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
544 * Check if irq settings are correct
546 if (irq != ppc->ppc_irq) {
548 * If the chipset is not locked and base address is 0x378,
549 * we have another chance
551 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
552 if (ppc->ppc_irq == 7) {
553 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
554 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
556 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
557 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
560 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
563 printf("PC873xx sorry, can't change irq setting\n");
567 printf("PC873xx irq settings are correct\n");
570 outb(idport, PC873_PCR);
571 pcr = inb(idport + 1);
573 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
575 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
577 ppc->ppc_avm |= PPB_NIBBLE;
581 if (pcr & PC873_EPPEN) {
582 ppc->ppc_avm |= PPB_EPP;
587 if (pcr & PC873_EPP19)
588 ppc->ppc_epp = EPP_1_9;
590 ppc->ppc_epp = EPP_1_7;
592 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
593 outb(idport, PC873_PTR);
594 ptr = inb(idport + 1);
595 if (ptr & PC873_EPPRDIR)
596 printf(", Regular mode");
598 printf(", Automatic mode");
600 } else if (pcr & PC873_ECPEN) {
601 ppc->ppc_avm |= PPB_ECP;
605 if (pcr & PC873_ECPCLK) { /* XXX */
606 ppc->ppc_avm |= PPB_PS2;
611 outb(idport, PC873_PTR);
612 ptr = inb(idport + 1);
613 if (ptr & PC873_EXTENDED) {
614 ppc->ppc_avm |= PPB_SPP;
621 printf("PC873xx unlocked");
623 if (chipset_mode & PPB_ECP) {
624 if ((chipset_mode & PPB_EPP) && bootverbose)
625 printf(", ECP+EPP not supported");
628 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
629 outb(idport + 1, pcr);
630 outb(idport + 1, pcr);
635 } else if (chipset_mode & PPB_EPP) {
636 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
637 pcr |= (PC873_EPPEN | PC873_EPP19);
638 outb(idport + 1, pcr);
639 outb(idport + 1, pcr);
641 ppc->ppc_epp = EPP_1_9; /* XXX */
646 /* enable automatic direction turnover */
647 if (ppc->ppc_model == NS_PC87332) {
648 outb(idport, PC873_PTR);
649 ptr = inb(idport + 1);
650 ptr &= ~PC873_EPPRDIR;
651 outb(idport + 1, ptr);
652 outb(idport + 1, ptr);
655 printf(", Automatic mode");
658 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
659 outb(idport + 1, pcr);
660 outb(idport + 1, pcr);
662 /* configure extended bit in PTR */
663 outb(idport, PC873_PTR);
664 ptr = inb(idport + 1);
666 if (chipset_mode & PPB_PS2) {
667 ptr |= PC873_EXTENDED;
673 /* default to NIBBLE mode */
674 ptr &= ~PC873_EXTENDED;
679 outb(idport + 1, ptr);
680 outb(idport + 1, ptr);
683 ppc->ppc_avm = chipset_mode;
689 ppc->ppc_type = PPC_TYPE_GENERIC;
690 ppc_generic_setmode(ppc, chipset_mode);
692 return(chipset_mode);
698 * ppc_smc37c66xgt_detect
700 * SMC FDC37C66xGT configuration.
703 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
708 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
710 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
713 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
716 * Detection: enter configuration mode and read CRD register.
718 PPC_CONFIG_LOCK(ppc);
719 outb(csr, SMC665_iCODE);
720 outb(csr, SMC665_iCODE);
721 PPC_CONFIG_UNLOCK(ppc);
724 if (inb(cio) == 0x65) {
729 for (i = 0; i < 2; i++) {
730 PPC_CONFIG_LOCK(ppc);
731 outb(csr, SMC666_iCODE);
732 outb(csr, SMC666_iCODE);
733 PPC_CONFIG_UNLOCK(ppc);
736 if (inb(cio) == 0x66) {
741 /* Another chance, CSR may be hard-configured to be at 0x370 */
747 * If chipset not found, do not continue.
750 outb(csr, 0xaa); /* end config mode */
757 /* read the port's address: bits 0 and 1 of CR1 */
758 r = inb(cio) & SMC_CR1_ADDR;
759 if (port_address[(int)r] != ppc->ppc_base) {
760 outb(csr, 0xaa); /* end config mode */
764 ppc->ppc_model = type;
767 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
768 * If SPP mode is detected, try to set ECP+EPP mode
773 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
777 printf(" CR4=0x%x", inb(cio) & 0xff);
784 /* autodetect mode */
786 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
787 if (type == SMC_37C666GT) {
788 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
790 printf(" configuration hardwired, supposing " \
794 if ((inb(cio) & SMC_CR1_MODE) == 0) {
795 /* already in extended parallel port mode, read CR4 */
797 r = (inb(cio) & SMC_CR4_EMODE);
801 ppc->ppc_avm |= PPB_SPP;
807 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
813 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
819 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
821 printf(" ECP+EPP SPP");
825 /* not an extended port mode */
826 ppc->ppc_avm |= PPB_SPP;
833 ppc->ppc_avm = chipset_mode;
835 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
836 if (type == SMC_37C666GT)
840 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
841 /* do not use ECP when the mode is not forced to */
842 outb(cio, r | SMC_CR1_MODE);
846 /* an extended mode is selected */
847 outb(cio, r & ~SMC_CR1_MODE);
849 /* read CR4 register and reset mode field */
851 r = inb(cio) & ~SMC_CR4_EMODE;
853 if (chipset_mode & PPB_ECP) {
854 if (chipset_mode & PPB_EPP) {
855 outb(cio, r | SMC_ECPEPP);
859 outb(cio, r | SMC_ECP);
865 outb(cio, r | SMC_EPPSPP);
870 ppc->ppc_avm = chipset_mode;
873 /* set FIFO threshold to 16 */
874 if (ppc->ppc_avm & PPB_ECP) {
885 if (ppc->ppc_avm & PPB_EPP) {
891 * Set the EPP protocol...
892 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
894 if (ppc->ppc_epp == EPP_1_9)
895 outb(cio, (r & ~SMC_CR4_EPPTYPE));
897 outb(cio, (r | SMC_CR4_EPPTYPE));
900 outb(csr, 0xaa); /* end config mode */
902 ppc->ppc_type = PPC_TYPE_SMCLIKE;
903 ppc_smclike_setmode(ppc, chipset_mode);
905 return (chipset_mode);
909 * SMC FDC37C935 configuration
910 * Found on many Alpha machines
913 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
917 PPC_CONFIG_LOCK(ppc);
918 outb(SMC935_CFG, 0x55); /* enter config mode */
919 outb(SMC935_CFG, 0x55);
920 PPC_CONFIG_UNLOCK(ppc);
922 outb(SMC935_IND, SMC935_ID); /* check device id */
923 if (inb(SMC935_DAT) == 0x2)
927 outb(SMC935_CFG, 0xaa); /* exit config mode */
931 ppc->ppc_model = type;
933 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
934 outb(SMC935_DAT, 3); /* which is logical device 3 */
936 /* set io port base */
937 outb(SMC935_IND, SMC935_PORTHI);
938 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
939 outb(SMC935_IND, SMC935_PORTLO);
940 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
943 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
945 ppc->ppc_avm = chipset_mode;
946 outb(SMC935_IND, SMC935_PPMODE);
947 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
949 /* SPP + EPP or just plain SPP */
950 if (chipset_mode & (PPB_SPP)) {
951 if (chipset_mode & PPB_EPP) {
952 if (ppc->ppc_epp == EPP_1_9) {
953 outb(SMC935_IND, SMC935_PPMODE);
954 outb(SMC935_DAT, SMC935_EPP19SPP);
956 if (ppc->ppc_epp == EPP_1_7) {
957 outb(SMC935_IND, SMC935_PPMODE);
958 outb(SMC935_DAT, SMC935_EPP17SPP);
961 outb(SMC935_IND, SMC935_PPMODE);
962 outb(SMC935_DAT, SMC935_SPP);
966 /* ECP + EPP or just plain ECP */
967 if (chipset_mode & PPB_ECP) {
968 if (chipset_mode & PPB_EPP) {
969 if (ppc->ppc_epp == EPP_1_9) {
970 outb(SMC935_IND, SMC935_PPMODE);
971 outb(SMC935_DAT, SMC935_ECPEPP19);
973 if (ppc->ppc_epp == EPP_1_7) {
974 outb(SMC935_IND, SMC935_PPMODE);
975 outb(SMC935_DAT, SMC935_ECPEPP17);
978 outb(SMC935_IND, SMC935_PPMODE);
979 outb(SMC935_DAT, SMC935_ECP);
984 outb(SMC935_CFG, 0xaa); /* exit config mode */
986 ppc->ppc_type = PPC_TYPE_SMCLIKE;
987 ppc_smclike_setmode(ppc, chipset_mode);
989 return (chipset_mode);
993 * Winbond W83877F stuff
995 * EFER: extended function enable register
996 * EFIR: extended function index register
997 * EFDR: extended function data register
999 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1000 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1002 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1003 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1004 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1005 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1008 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1011 unsigned char r, hefere, hefras;
1013 for (i = 0; i < 4; i ++) {
1014 /* first try to enable configuration registers */
1015 efer = w83877f_efers[i];
1017 /* write the key to the EFER */
1018 for (j = 0; j < w83877f_keyiter[i]; j ++)
1019 outb (efer, w83877f_keys[i]);
1021 /* then check HEFERE and HEFRAS bits */
1023 hefere = inb(efdr) & WINB_HEFERE;
1026 hefras = inb(efdr) & WINB_HEFRAS;
1030 * 0 1 write 89h to 250h (power-on default)
1031 * 1 0 write 86h twice to 3f0h
1032 * 1 1 write 87h twice to 3f0h
1033 * 0 0 write 88h to 250h
1035 if ((hefere | hefras) == w83877f_hefs[i])
1039 return (-1); /* failed */
1042 /* check base port address - read from CR23 */
1044 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1047 /* read CHIP ID from CR9/bits0-3 */
1050 switch (inb(efdr) & WINB_CHIPID) {
1051 case WINB_W83877F_ID:
1052 ppc->ppc_model = WINB_W83877F;
1055 case WINB_W83877AF_ID:
1056 ppc->ppc_model = WINB_W83877AF;
1060 ppc->ppc_model = WINB_UNKNOWN;
1064 /* dump of registers */
1065 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1066 for (i = 0; i <= 0xd; i ++) {
1068 printf("0x%x ", inb(efdr));
1070 for (i = 0x10; i <= 0x17; i ++) {
1072 printf("0x%x ", inb(efdr));
1075 printf("0x%x ", inb(efdr));
1076 for (i = 0x20; i <= 0x29; i ++) {
1078 printf("0x%x ", inb(efdr));
1083 ppc->ppc_type = PPC_TYPE_GENERIC;
1085 if (!chipset_mode) {
1086 /* autodetect mode */
1090 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1094 r |= (inb(efdr) & WINB_PRTMODS2);
1099 device_printf(ppc->ppc_dev,
1100 "W83757 compatible mode\n");
1101 return (-1); /* generic or SMC-like */
1108 device_printf(ppc->ppc_dev,
1109 "not in parallel port mode\n");
1112 case (WINB_PARALLEL | WINB_EPP_SPP):
1113 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1115 device_printf(ppc->ppc_dev, "EPP SPP\n");
1118 case (WINB_PARALLEL | WINB_ECP):
1119 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1121 device_printf(ppc->ppc_dev, "ECP SPP\n");
1124 case (WINB_PARALLEL | WINB_ECP_EPP):
1125 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1126 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1129 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1132 printf("%s: unknown case (0x%x)!\n", __func__, r);
1138 /* select CR9 and set PRTMODS2 bit */
1140 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1142 /* select CR0 and reset PRTMODSx bits */
1144 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1146 if (chipset_mode & PPB_ECP) {
1147 if (chipset_mode & PPB_EPP) {
1148 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1150 device_printf(ppc->ppc_dev,
1153 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1156 outb(efdr, inb(efdr) | WINB_ECP);
1158 device_printf(ppc->ppc_dev, "ECP\n");
1161 /* select EPP_SPP otherwise */
1162 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1164 device_printf(ppc->ppc_dev, "EPP SPP\n");
1166 ppc->ppc_avm = chipset_mode;
1169 /* exit configuration mode */
1172 switch (ppc->ppc_type) {
1173 case PPC_TYPE_SMCLIKE:
1174 ppc_smclike_setmode(ppc, chipset_mode);
1177 ppc_generic_setmode(ppc, chipset_mode);
1181 return (chipset_mode);
1186 * ppc_generic_detect
1189 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1191 /* default to generic */
1192 ppc->ppc_type = PPC_TYPE_GENERIC;
1195 device_printf(ppc->ppc_dev, "SPP");
1197 /* first, check for ECP */
1198 w_ecr(ppc, PPC_ECR_PS2);
1199 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1200 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1204 /* search for SMC style ECP+EPP mode */
1205 w_ecr(ppc, PPC_ECR_EPP);
1208 /* try to reset EPP timeout bit */
1209 if (ppc_check_epp_timeout(ppc)) {
1210 ppc->ppc_dtm |= PPB_EPP;
1212 if (ppc->ppc_dtm & PPB_ECP) {
1213 /* SMC like chipset found */
1214 ppc->ppc_model = SMC_LIKE;
1215 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1224 /* restore to standard mode */
1225 w_ecr(ppc, PPC_ECR_STD);
1228 /* XXX try to detect NIBBLE and PS2 modes */
1229 ppc->ppc_dtm |= PPB_NIBBLE;
1232 ppc->ppc_avm = chipset_mode;
1234 ppc->ppc_avm = ppc->ppc_dtm;
1239 switch (ppc->ppc_type) {
1240 case PPC_TYPE_SMCLIKE:
1241 ppc_smclike_setmode(ppc, chipset_mode);
1244 ppc_generic_setmode(ppc, chipset_mode);
1248 return (chipset_mode);
1254 * mode is the mode suggested at boot
1257 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1259 #ifdef PPC_PROBE_CHIPSET
1262 /* list of supported chipsets */
1263 int (*chipset_detect[])(struct ppc_data *, int) = {
1265 ppc_smc37c66xgt_detect,
1267 ppc_smc37c935_detect,
1273 /* if can't find the port and mode not forced return error */
1274 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1275 return (EIO); /* failed, port not present */
1277 /* assume centronics compatible mode is supported */
1278 ppc->ppc_avm = PPB_COMPATIBLE;
1280 #ifdef PPC_PROBE_CHIPSET
1281 /* we have to differenciate available chipset modes,
1282 * chipset running modes and IEEE-1284 operating modes
1284 * after detection, the port must support running in compatible mode
1286 if (ppc->ppc_flags & 0x40) {
1288 printf("ppc: chipset forced to generic\n");
1291 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1293 #ifdef PPC_PROBE_CHIPSET
1295 for (i=0; chipset_detect[i] != NULL; i++) {
1296 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1297 ppc->ppc_mode = mode;
1304 /* configure/detect ECP FIFO */
1305 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1306 ppc_detect_fifo(ppc);
1312 * ppc_exec_microseq()
1314 * Execute a microsequence.
1315 * Microsequence mechanism is supposed to handle fast I/O operations.
1318 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1320 struct ppc_data *ppc = DEVTOSOFTC(dev);
1321 struct ppb_microseq *mi;
1331 struct ppb_microseq *stack = NULL;
1333 /* microsequence registers are equivalent to PC-like port registers */
1335 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1336 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1338 #define INCR_PC (mi ++) /* increment program counter */
1340 PPC_ASSERT_LOCKED(ppc);
1343 switch (mi->opcode) {
1345 cc = r_reg(mi->arg[0].i, ppc);
1346 cc &= (char)mi->arg[2].i; /* clear mask */
1347 cc |= (char)mi->arg[1].i; /* assert mask */
1348 w_reg(mi->arg[0].i, ppc, cc);
1352 case MS_OP_RASSERT_P:
1356 if ((len = mi->arg[0].i) == MS_ACCUM) {
1357 accum = ppc->ppc_accum;
1358 for (; accum; accum--)
1359 w_reg(reg, ppc, *ptr++);
1360 ppc->ppc_accum = accum;
1362 for (i=0; i<len; i++)
1363 w_reg(reg, ppc, *ptr++);
1369 case MS_OP_RFETCH_P:
1371 mask = (char)mi->arg[2].i;
1374 if ((len = mi->arg[0].i) == MS_ACCUM) {
1375 accum = ppc->ppc_accum;
1376 for (; accum; accum--)
1377 *ptr++ = r_reg(reg, ppc) & mask;
1378 ppc->ppc_accum = accum;
1380 for (i=0; i<len; i++)
1381 *ptr++ = r_reg(reg, ppc) & mask;
1388 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1396 /* let's suppose the next instr. is the same */
1398 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1399 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1401 if (mi->opcode == MS_OP_DELAY) {
1402 DELAY(mi->arg[0].i);
1411 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1419 iter = mi->arg[1].i;
1420 p = (char *)mi->arg[2].p;
1422 /* XXX delay limited to 255 us */
1423 for (i=0; i<iter; i++) {
1424 w_reg(reg, ppc, *p++);
1425 DELAY((unsigned char)*p++);
1431 ppc->ppc_accum = mi->arg[0].i;
1436 if (--ppc->ppc_accum > 0)
1443 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1450 if ((cc & (char)mi->arg[0].i) == 0)
1457 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1465 * If the C call returns !0 then end the microseq.
1466 * The current state of ptr is passed to the C function
1468 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1475 ppc->ppc_ptr = (char *)mi->arg[0].p;
1481 panic("%s: too much calls", __func__);
1484 /* store the state of the actual
1489 /* jump to the new microsequence */
1490 mi = (struct ppb_microseq *)mi->arg[0].p;
1497 /* retrieve microseq and pc state before the call */
1500 /* reset the stack */
1503 /* XXX return code */
1511 /* can't return to ppb level during the execution
1512 * of a submicrosequence */
1514 panic("%s: can't return to ppb level",
1517 /* update pc for ppb level of execution */
1520 /* return to ppb level of execution */
1524 panic("%s: unknown microsequence opcode 0x%x",
1525 __func__, mi->opcode);
1535 struct ppc_data *ppc = arg;
1536 u_char ctr, ecr, str;
1539 * If we have any child interrupt handlers registered, let
1540 * them handle this interrupt.
1542 * XXX: If DMA is in progress should we just complete that w/o
1546 if (ppc->ppc_intr_hook != NULL &&
1547 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1556 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1557 printf("![%x/%x/%x]", ctr, ecr, str);
1560 /* don't use ecp mode with IRQENABLE set */
1561 if (ctr & IRQENABLE) {
1566 /* interrupts are generated by nFault signal
1567 * only in ECP mode */
1568 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1569 /* check if ppc driver has programmed the
1570 * nFault interrupt */
1571 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1573 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1574 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1576 /* shall be handled by underlying layers XXX */
1582 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1583 /* disable interrupts (should be done by hardware though) */
1584 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1585 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1588 /* check if DMA completed */
1589 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1594 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1597 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1601 ppc->ppc_dmadone(ppc);
1602 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1604 /* wakeup the waiting process */
1608 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1610 /* classic interrupt I/O */
1611 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1619 ppc_read(device_t dev, char *buf, int len, int mode)
1625 ppc_write(device_t dev, char *buf, int len, int how)
1631 ppc_reset_epp(device_t dev)
1633 struct ppc_data *ppc = DEVTOSOFTC(dev);
1635 PPC_ASSERT_LOCKED(ppc);
1636 ppc_reset_epp_timeout(ppc);
1642 ppc_setmode(device_t dev, int mode)
1644 struct ppc_data *ppc = DEVTOSOFTC(dev);
1646 PPC_ASSERT_LOCKED(ppc);
1647 switch (ppc->ppc_type) {
1648 case PPC_TYPE_SMCLIKE:
1649 return (ppc_smclike_setmode(ppc, mode));
1652 case PPC_TYPE_GENERIC:
1654 return (ppc_generic_setmode(ppc, mode));
1663 ppc_probe(device_t dev, int rid)
1666 static short next_bios_ppc = 0;
1668 struct ppc_data *ppc;
1673 * Allocate the ppc_data structure.
1675 ppc = DEVTOSOFTC(dev);
1676 bzero(ppc, sizeof(struct ppc_data));
1678 ppc->rid_ioport = rid;
1680 /* retrieve ISA parameters */
1681 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1685 * If port not specified, use bios list.
1688 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1689 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1690 port = *(BIOS_PORTS + next_bios_ppc++);
1693 "parallel port found at 0x%jx\n", port);
1695 device_printf(dev, "parallel port not found.\n");
1698 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1699 IO_LPTSIZE_EXTENDED);
1703 /* IO port is mandatory */
1705 /* Try "extended" IO port range...*/
1706 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1708 IO_LPTSIZE_EXTENDED,
1711 if (ppc->res_ioport != 0) {
1713 device_printf(dev, "using extended I/O port range\n");
1715 /* Failed? If so, then try the "normal" IO port range... */
1716 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1721 if (ppc->res_ioport != 0) {
1723 device_printf(dev, "using normal I/O port range\n");
1726 device_printf(dev, "cannot reserve I/O port range\n");
1731 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1733 ppc->ppc_flags = device_get_flags(dev);
1735 if (!(ppc->ppc_flags & 0x20)) {
1736 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1739 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1745 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1747 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1750 ppc->ppc_model = GENERIC;
1752 ppc->ppc_mode = PPB_COMPATIBLE;
1753 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1755 ppc->ppc_type = PPC_TYPE_GENERIC;
1758 * Try to detect the chipset and its mode.
1760 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1766 if (ppc->res_irq != 0) {
1767 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1770 if (ppc->res_ioport != 0) {
1771 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1774 if (ppc->res_drq != 0) {
1775 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1782 ppc_attach(device_t dev)
1784 struct ppc_data *ppc = DEVTOSOFTC(dev);
1787 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1789 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1790 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1791 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1792 ppc_epp_protocol[ppc->ppc_epp] : "");
1795 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1796 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1799 /* default to the tty mask for registration */ /* XXX */
1800 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1801 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1804 "failed to register interrupt handler: %d\n",
1806 mtx_destroy(&ppc->ppc_lock);
1811 /* add ppbus as a child of this isa to parallel bridge */
1812 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1815 * Probe the ppbus and attach devices found.
1817 device_probe_and_attach(ppc->ppbus);
1823 ppc_detach(device_t dev)
1825 struct ppc_data *ppc = DEVTOSOFTC(dev);
1827 if (ppc->res_irq == 0) {
1831 /* detach & delete all children */
1832 device_delete_children(dev);
1834 if (ppc->res_irq != 0) {
1835 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1836 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1839 if (ppc->res_ioport != 0) {
1840 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1843 if (ppc->res_drq != 0) {
1844 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1848 mtx_destroy(&ppc->ppc_lock);
1854 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1856 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1858 PPC_ASSERT_LOCKED(ppc);
1861 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1864 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1867 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1870 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1873 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1876 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1879 return (r_dtr(ppc));
1881 return (r_str(ppc));
1883 return (r_ctr(ppc));
1885 return (r_epp_A(ppc));
1887 return (r_epp_D(ppc));
1889 return (r_ecr(ppc));
1891 return (r_fifo(ppc));
1914 panic("%s: unknown I/O operation", __func__);
1918 return (0); /* not significative */
1922 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1924 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1927 case PPC_IVAR_EPP_PROTO:
1928 PPC_ASSERT_LOCKED(ppc);
1929 *val = (u_long)ppc->ppc_epp;
1932 *val = (uintptr_t)&ppc->ppc_lock;
1942 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1944 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1947 case PPC_IVAR_INTR_HANDLER:
1948 PPC_ASSERT_LOCKED(ppc);
1949 if (dev != ppc->ppbus)
1952 ppc->ppc_intr_hook = NULL;
1955 if (ppc->ppc_intr_hook != NULL)
1957 ppc->ppc_intr_hook = (void *)val;
1958 ppc->ppc_intr_arg = device_get_softc(dev);
1968 * We allow child devices to allocate an IRQ resource at rid 0 for their
1969 * interrupt handlers.
1972 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1973 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1975 struct ppc_data *ppc = DEVTOSOFTC(bus);
1980 return (ppc->res_irq);
1987 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1991 struct ppc_data *ppc = DEVTOSOFTC(bus);
1997 KASSERT(r == ppc->res_irq,
1998 ("ppc child IRQ resource mismatch"));
2006 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);