2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/interrupt.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
51 #include <machine/vmparam.h>
54 #include <dev/ppbus/ppbconf.h>
55 #include <dev/ppbus/ppb_msq.h>
57 #include <dev/ppc/ppcvar.h>
58 #include <dev/ppc/ppcreg.h>
62 static void ppcintr(void *arg);
64 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
65 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
67 #define LOG_PPC(function, ppc, string) \
68 if (bootverbose) printf("%s: %s\n", function, string)
70 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
73 * We use critical enter/exit for the simple config locking needed to
74 * detect the devices. We just want to make sure that both of our writes
75 * happen without someone else also writing to those config registers. Since
76 * we just do this at startup, Giant keeps multiple threads from executing,
77 * and critical_enter() then is all that's needed to keep us from being preempted
78 * during the critical sequences with the hardware.
80 * Note: this doesn't prevent multiple threads from putting the chips into
81 * config mode, but since we only do that to detect the type at startup the
82 * extra overhead isn't needed since Giant protects us from multiple entry
83 * and no other code changes these registers.
85 #define PPC_CONFIG_LOCK(ppc) critical_enter()
86 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
88 devclass_t ppc_devclass;
89 const char ppc_driver_name[] = "ppc";
91 static char *ppc_models[] = {
92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
93 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
94 "SMC FDC37C935", "PC87303", 0
97 /* list of available modes */
98 static char *ppc_avms[] = {
99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
101 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
102 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
105 /* list of current executing modes
106 * Note that few modes do not actually exist.
108 static char *ppc_modes[] = {
109 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
110 "EPP", "EPP", "EPP", "ECP",
111 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
112 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
115 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
119 * BIOS printer list - used by BIOS probe.
121 #define BIOS_PPC_PORTS 0x408
122 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
123 #define BIOS_MAX_PPC 4
130 ppc_ecp_sync(device_t dev)
133 struct ppc_data *ppc = DEVTOSOFTC(dev);
135 PPC_ASSERT_LOCKED(ppc);
136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
140 if ((r & 0xe0) != PPC_ECR_EPP)
143 for (i = 0; i < 100; i++) {
150 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
158 * Detect parallel port FIFO
161 ppc_detect_fifo(struct ppc_data *ppc)
164 char ctr_sav, ctr, cc;
168 ecr_sav = r_ecr(ppc);
169 ctr_sav = r_ctr(ppc);
171 /* enter ECP configuration mode, no interrupt, no DMA */
174 /* read PWord size - transfers in FIFO mode must be PWord aligned */
175 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
177 /* XXX 16 and 32 bits implementations not supported */
178 if (ppc->ppc_pword != PPC_PWORD_8) {
179 LOG_PPC(__func__, ppc, "PWord not supported");
183 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
185 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
187 /* enter ECP test mode, no interrupt, no DMA */
191 for (i=0; i<1024; i++) {
192 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
198 LOG_PPC(__func__, ppc, "can't flush FIFO");
202 /* enable interrupts, no DMA */
205 /* determine readIntrThreshold
206 * fill the FIFO until serviceIntr is set
208 for (i=0; i<1024; i++) {
209 w_fifo(ppc, (char)i);
210 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
211 /* readThreshold reached */
214 if (r_ecr(ppc) & PPC_FIFO_FULL) {
221 LOG_PPC(__func__, ppc, "can't fill FIFO");
225 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
226 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
227 w_ecr(ppc, 0xd0); /* enable interrupts */
229 /* determine writeIntrThreshold
230 * empty the FIFO until serviceIntr is set
232 for (i=ppc->ppc_fifo; i>0; i--) {
233 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
234 LOG_PPC(__func__, ppc, "invalid data in FIFO");
237 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
238 /* writeIntrThreshold reached */
239 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
241 /* if FIFO empty before the last byte, error */
242 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
243 LOG_PPC(__func__, ppc, "data lost in FIFO");
248 /* FIFO must be empty after the last byte */
249 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
250 LOG_PPC(__func__, ppc, "can't empty the FIFO");
267 ppc_detect_port(struct ppc_data *ppc)
270 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
272 if (r_dtr(ppc) != 0xaa)
279 * EPP timeout, according to the PC87332 manual
280 * Semantics of clearing EPP timeout bit.
281 * PC87332 - reading SPP_STR does it...
282 * SMC - write 1 to EPP timeout bit XXX
283 * Others - (?) write 0 to EPP timeout bit
286 ppc_reset_epp_timeout(struct ppc_data *ppc)
292 w_str(ppc, r & 0xfe);
298 ppc_check_epp_timeout(struct ppc_data *ppc)
300 ppc_reset_epp_timeout(ppc);
302 return (!(r_str(ppc) & TIMEOUT));
306 * Configure current operating mode
309 ppc_generic_setmode(struct ppc_data *ppc, int mode)
313 /* check if mode is available */
314 if (mode && !(ppc->ppc_avm & mode))
317 /* if ECP mode, configure ecr register */
318 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
319 /* return to byte mode (keeping direction bit),
320 * no interrupt, no DMA to be able to change to
323 w_ecr(ppc, PPC_ECR_RESET);
324 ecr = PPC_DISABLE_INTR;
328 else if (mode & PPB_ECP)
329 /* select ECP mode */
331 else if (mode & PPB_PS2)
332 /* select PS2 mode with ECP */
335 /* select COMPATIBLE/NIBBLE mode */
341 ppc->ppc_mode = mode;
347 * The ppc driver is free to choose options like FIFO or DMA
348 * if ECP mode is available.
350 * The 'RAW' option allows the upper drivers to force the ppc mode
351 * even with FIFO, DMA available.
354 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
358 /* check if mode is available */
359 if (mode && !(ppc->ppc_avm & mode))
362 /* if ECP mode, configure ecr register */
363 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
364 /* return to byte mode (keeping direction bit),
365 * no interrupt, no DMA to be able to change to
368 w_ecr(ppc, PPC_ECR_RESET);
369 ecr = PPC_DISABLE_INTR;
372 /* select EPP mode */
374 else if (mode & PPB_ECP)
375 /* select ECP mode */
377 else if (mode & PPB_PS2)
378 /* select PS2 mode with ECP */
381 /* select COMPATIBLE/NIBBLE mode */
387 ppc->ppc_mode = mode;
392 #ifdef PPC_PROBE_CHIPSET
396 * Probe for a Natsemi PC873xx-family part.
398 * References in this function are to the National Semiconductor
399 * PC87332 datasheet TL/C/11930, May 1995 revision.
401 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
402 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
403 static int pc873xx_irqtab[] = {5, 7, 5, 0};
405 static int pc873xx_regstab[] = {
406 PC873_FER, PC873_FAR, PC873_PTR,
407 PC873_FCR, PC873_PCR, PC873_PMC,
408 PC873_TUP, PC873_SID, PC873_PNP0,
409 PC873_PNP1, PC873_LPTBA, -1
412 static char *pc873xx_rnametab[] = {
413 "FER", "FAR", "PTR", "FCR", "PCR",
414 "PMC", "TUP", "SID", "PNP0", "PNP1",
419 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
421 static int index = 0;
423 int ptr, pcr, val, i;
425 while ((idport = pc873xx_basetab[index++])) {
427 /* XXX should check first to see if this location is already claimed */
430 * Pull the 873xx through the power-on ID cycle (2.2,1.).
431 * We can't use this to locate the chip as it may already have
432 * been used by the BIOS.
434 (void)inb(idport); (void)inb(idport);
435 (void)inb(idport); (void)inb(idport);
438 * Read the SID byte. Possible values are :
445 outb(idport, PC873_SID);
446 val = inb(idport + 1);
447 if ((val & 0xf0) == 0x10) {
448 ppc->ppc_model = NS_PC87332;
449 } else if ((val & 0xf8) == 0x70) {
450 ppc->ppc_model = NS_PC87306;
451 } else if ((val & 0xf8) == 0x50) {
452 ppc->ppc_model = NS_PC87334;
453 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
454 documentation, but probing
456 ppc->ppc_model = NS_PC87303;
458 if (bootverbose && (val != 0xff))
459 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
460 continue ; /* not recognised */
463 /* print registers */
466 for (i=0; pc873xx_regstab[i] != -1; i++) {
467 outb(idport, pc873xx_regstab[i]);
468 printf(" %s=0x%x", pc873xx_rnametab[i],
469 inb(idport + 1) & 0xff);
475 * We think we have one. Is it enabled and where we want it to be?
477 outb(idport, PC873_FER);
478 val = inb(idport + 1);
479 if (!(val & PC873_PPENABLE)) {
481 printf("PC873xx parallel port disabled\n");
484 outb(idport, PC873_FAR);
485 val = inb(idport + 1);
486 /* XXX we should create a driver instance for every port found */
487 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
489 /* First try to change the port address to that requested... */
491 switch (ppc->ppc_base) {
509 outb(idport, PC873_FAR);
510 outb(idport + 1, val);
511 outb(idport + 1, val);
513 /* Check for success by reading back the value we supposedly
514 wrote and comparing...*/
516 outb(idport, PC873_FAR);
517 val = inb(idport + 1) & 0x3;
519 /* If we fail, report the failure... */
521 if (pc873xx_porttab[val] != ppc->ppc_base) {
523 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
524 pc873xx_porttab[val], ppc->ppc_base);
529 outb(idport, PC873_PTR);
530 ptr = inb(idport + 1);
532 /* get irq settings */
533 if (ppc->ppc_base == 0x378)
534 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
536 irq = pc873xx_irqtab[val];
539 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
542 * Check if irq settings are correct
544 if (irq != ppc->ppc_irq) {
546 * If the chipset is not locked and base address is 0x378,
547 * we have another chance
549 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
550 if (ppc->ppc_irq == 7) {
551 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
552 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
554 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
555 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
558 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
561 printf("PC873xx sorry, can't change irq setting\n");
565 printf("PC873xx irq settings are correct\n");
568 outb(idport, PC873_PCR);
569 pcr = inb(idport + 1);
571 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
573 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
575 ppc->ppc_avm |= PPB_NIBBLE;
579 if (pcr & PC873_EPPEN) {
580 ppc->ppc_avm |= PPB_EPP;
585 if (pcr & PC873_EPP19)
586 ppc->ppc_epp = EPP_1_9;
588 ppc->ppc_epp = EPP_1_7;
590 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
591 outb(idport, PC873_PTR);
592 ptr = inb(idport + 1);
593 if (ptr & PC873_EPPRDIR)
594 printf(", Regular mode");
596 printf(", Automatic mode");
598 } else if (pcr & PC873_ECPEN) {
599 ppc->ppc_avm |= PPB_ECP;
603 if (pcr & PC873_ECPCLK) { /* XXX */
604 ppc->ppc_avm |= PPB_PS2;
609 outb(idport, PC873_PTR);
610 ptr = inb(idport + 1);
611 if (ptr & PC873_EXTENDED) {
612 ppc->ppc_avm |= PPB_SPP;
619 printf("PC873xx unlocked");
621 if (chipset_mode & PPB_ECP) {
622 if ((chipset_mode & PPB_EPP) && bootverbose)
623 printf(", ECP+EPP not supported");
626 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
627 outb(idport + 1, pcr);
628 outb(idport + 1, pcr);
633 } else if (chipset_mode & PPB_EPP) {
634 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
635 pcr |= (PC873_EPPEN | PC873_EPP19);
636 outb(idport + 1, pcr);
637 outb(idport + 1, pcr);
639 ppc->ppc_epp = EPP_1_9; /* XXX */
644 /* enable automatic direction turnover */
645 if (ppc->ppc_model == NS_PC87332) {
646 outb(idport, PC873_PTR);
647 ptr = inb(idport + 1);
648 ptr &= ~PC873_EPPRDIR;
649 outb(idport + 1, ptr);
650 outb(idport + 1, ptr);
653 printf(", Automatic mode");
656 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
657 outb(idport + 1, pcr);
658 outb(idport + 1, pcr);
660 /* configure extended bit in PTR */
661 outb(idport, PC873_PTR);
662 ptr = inb(idport + 1);
664 if (chipset_mode & PPB_PS2) {
665 ptr |= PC873_EXTENDED;
671 /* default to NIBBLE mode */
672 ptr &= ~PC873_EXTENDED;
677 outb(idport + 1, ptr);
678 outb(idport + 1, ptr);
681 ppc->ppc_avm = chipset_mode;
687 ppc->ppc_type = PPC_TYPE_GENERIC;
688 ppc_generic_setmode(ppc, chipset_mode);
690 return(chipset_mode);
696 * ppc_smc37c66xgt_detect
698 * SMC FDC37C66xGT configuration.
701 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
706 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
708 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
711 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
714 * Detection: enter configuration mode and read CRD register.
716 PPC_CONFIG_LOCK(ppc);
717 outb(csr, SMC665_iCODE);
718 outb(csr, SMC665_iCODE);
719 PPC_CONFIG_UNLOCK(ppc);
722 if (inb(cio) == 0x65) {
727 for (i = 0; i < 2; i++) {
728 PPC_CONFIG_LOCK(ppc);
729 outb(csr, SMC666_iCODE);
730 outb(csr, SMC666_iCODE);
731 PPC_CONFIG_UNLOCK(ppc);
734 if (inb(cio) == 0x66) {
739 /* Another chance, CSR may be hard-configured to be at 0x370 */
745 * If chipset not found, do not continue.
748 outb(csr, 0xaa); /* end config mode */
755 /* read the port's address: bits 0 and 1 of CR1 */
756 r = inb(cio) & SMC_CR1_ADDR;
757 if (port_address[(int)r] != ppc->ppc_base) {
758 outb(csr, 0xaa); /* end config mode */
762 ppc->ppc_model = type;
765 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
766 * If SPP mode is detected, try to set ECP+EPP mode
771 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
775 printf(" CR4=0x%x", inb(cio) & 0xff);
782 /* autodetect mode */
784 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
785 if (type == SMC_37C666GT) {
786 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
788 printf(" configuration hardwired, supposing " \
792 if ((inb(cio) & SMC_CR1_MODE) == 0) {
793 /* already in extended parallel port mode, read CR4 */
795 r = (inb(cio) & SMC_CR4_EMODE);
799 ppc->ppc_avm |= PPB_SPP;
805 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
811 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
817 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
819 printf(" ECP+EPP SPP");
823 /* not an extended port mode */
824 ppc->ppc_avm |= PPB_SPP;
831 ppc->ppc_avm = chipset_mode;
833 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
834 if (type == SMC_37C666GT)
838 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
839 /* do not use ECP when the mode is not forced to */
840 outb(cio, r | SMC_CR1_MODE);
844 /* an extended mode is selected */
845 outb(cio, r & ~SMC_CR1_MODE);
847 /* read CR4 register and reset mode field */
849 r = inb(cio) & ~SMC_CR4_EMODE;
851 if (chipset_mode & PPB_ECP) {
852 if (chipset_mode & PPB_EPP) {
853 outb(cio, r | SMC_ECPEPP);
857 outb(cio, r | SMC_ECP);
863 outb(cio, r | SMC_EPPSPP);
868 ppc->ppc_avm = chipset_mode;
871 /* set FIFO threshold to 16 */
872 if (ppc->ppc_avm & PPB_ECP) {
883 if (ppc->ppc_avm & PPB_EPP) {
889 * Set the EPP protocol...
890 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
892 if (ppc->ppc_epp == EPP_1_9)
893 outb(cio, (r & ~SMC_CR4_EPPTYPE));
895 outb(cio, (r | SMC_CR4_EPPTYPE));
898 outb(csr, 0xaa); /* end config mode */
900 ppc->ppc_type = PPC_TYPE_SMCLIKE;
901 ppc_smclike_setmode(ppc, chipset_mode);
903 return (chipset_mode);
907 * SMC FDC37C935 configuration
908 * Found on many Alpha machines
911 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
915 PPC_CONFIG_LOCK(ppc);
916 outb(SMC935_CFG, 0x55); /* enter config mode */
917 outb(SMC935_CFG, 0x55);
918 PPC_CONFIG_UNLOCK(ppc);
920 outb(SMC935_IND, SMC935_ID); /* check device id */
921 if (inb(SMC935_DAT) == 0x2)
925 outb(SMC935_CFG, 0xaa); /* exit config mode */
929 ppc->ppc_model = type;
931 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
932 outb(SMC935_DAT, 3); /* which is logical device 3 */
934 /* set io port base */
935 outb(SMC935_IND, SMC935_PORTHI);
936 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
937 outb(SMC935_IND, SMC935_PORTLO);
938 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
941 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
943 ppc->ppc_avm = chipset_mode;
944 outb(SMC935_IND, SMC935_PPMODE);
945 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
947 /* SPP + EPP or just plain SPP */
948 if (chipset_mode & (PPB_SPP)) {
949 if (chipset_mode & PPB_EPP) {
950 if (ppc->ppc_epp == EPP_1_9) {
951 outb(SMC935_IND, SMC935_PPMODE);
952 outb(SMC935_DAT, SMC935_EPP19SPP);
954 if (ppc->ppc_epp == EPP_1_7) {
955 outb(SMC935_IND, SMC935_PPMODE);
956 outb(SMC935_DAT, SMC935_EPP17SPP);
959 outb(SMC935_IND, SMC935_PPMODE);
960 outb(SMC935_DAT, SMC935_SPP);
964 /* ECP + EPP or just plain ECP */
965 if (chipset_mode & PPB_ECP) {
966 if (chipset_mode & PPB_EPP) {
967 if (ppc->ppc_epp == EPP_1_9) {
968 outb(SMC935_IND, SMC935_PPMODE);
969 outb(SMC935_DAT, SMC935_ECPEPP19);
971 if (ppc->ppc_epp == EPP_1_7) {
972 outb(SMC935_IND, SMC935_PPMODE);
973 outb(SMC935_DAT, SMC935_ECPEPP17);
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_ECP);
982 outb(SMC935_CFG, 0xaa); /* exit config mode */
984 ppc->ppc_type = PPC_TYPE_SMCLIKE;
985 ppc_smclike_setmode(ppc, chipset_mode);
987 return (chipset_mode);
991 * Winbond W83877F stuff
993 * EFER: extended function enable register
994 * EFIR: extended function index register
995 * EFDR: extended function data register
997 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
998 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1000 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1001 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1002 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1003 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1006 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1009 unsigned char r, hefere, hefras;
1011 for (i = 0; i < 4; i ++) {
1012 /* first try to enable configuration registers */
1013 efer = w83877f_efers[i];
1015 /* write the key to the EFER */
1016 for (j = 0; j < w83877f_keyiter[i]; j ++)
1017 outb (efer, w83877f_keys[i]);
1019 /* then check HEFERE and HEFRAS bits */
1021 hefere = inb(efdr) & WINB_HEFERE;
1024 hefras = inb(efdr) & WINB_HEFRAS;
1028 * 0 1 write 89h to 250h (power-on default)
1029 * 1 0 write 86h twice to 3f0h
1030 * 1 1 write 87h twice to 3f0h
1031 * 0 0 write 88h to 250h
1033 if ((hefere | hefras) == w83877f_hefs[i])
1037 return (-1); /* failed */
1040 /* check base port address - read from CR23 */
1042 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1045 /* read CHIP ID from CR9/bits0-3 */
1048 switch (inb(efdr) & WINB_CHIPID) {
1049 case WINB_W83877F_ID:
1050 ppc->ppc_model = WINB_W83877F;
1053 case WINB_W83877AF_ID:
1054 ppc->ppc_model = WINB_W83877AF;
1058 ppc->ppc_model = WINB_UNKNOWN;
1062 /* dump of registers */
1063 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1064 for (i = 0; i <= 0xd; i ++) {
1066 printf("0x%x ", inb(efdr));
1068 for (i = 0x10; i <= 0x17; i ++) {
1070 printf("0x%x ", inb(efdr));
1073 printf("0x%x ", inb(efdr));
1074 for (i = 0x20; i <= 0x29; i ++) {
1076 printf("0x%x ", inb(efdr));
1081 ppc->ppc_type = PPC_TYPE_GENERIC;
1083 if (!chipset_mode) {
1084 /* autodetect mode */
1088 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1092 r |= (inb(efdr) & WINB_PRTMODS2);
1097 device_printf(ppc->ppc_dev,
1098 "W83757 compatible mode\n");
1099 return (-1); /* generic or SMC-like */
1106 device_printf(ppc->ppc_dev,
1107 "not in parallel port mode\n");
1110 case (WINB_PARALLEL | WINB_EPP_SPP):
1111 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1113 device_printf(ppc->ppc_dev, "EPP SPP\n");
1116 case (WINB_PARALLEL | WINB_ECP):
1117 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1119 device_printf(ppc->ppc_dev, "ECP SPP\n");
1122 case (WINB_PARALLEL | WINB_ECP_EPP):
1123 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1124 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1127 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1130 printf("%s: unknown case (0x%x)!\n", __func__, r);
1136 /* select CR9 and set PRTMODS2 bit */
1138 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1140 /* select CR0 and reset PRTMODSx bits */
1142 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1144 if (chipset_mode & PPB_ECP) {
1145 if (chipset_mode & PPB_EPP) {
1146 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1148 device_printf(ppc->ppc_dev,
1151 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1154 outb(efdr, inb(efdr) | WINB_ECP);
1156 device_printf(ppc->ppc_dev, "ECP\n");
1159 /* select EPP_SPP otherwise */
1160 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1162 device_printf(ppc->ppc_dev, "EPP SPP\n");
1164 ppc->ppc_avm = chipset_mode;
1167 /* exit configuration mode */
1170 switch (ppc->ppc_type) {
1171 case PPC_TYPE_SMCLIKE:
1172 ppc_smclike_setmode(ppc, chipset_mode);
1175 ppc_generic_setmode(ppc, chipset_mode);
1179 return (chipset_mode);
1184 * ppc_generic_detect
1187 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1189 /* default to generic */
1190 ppc->ppc_type = PPC_TYPE_GENERIC;
1193 device_printf(ppc->ppc_dev, "SPP");
1195 /* first, check for ECP */
1196 w_ecr(ppc, PPC_ECR_PS2);
1197 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1198 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1202 /* search for SMC style ECP+EPP mode */
1203 w_ecr(ppc, PPC_ECR_EPP);
1206 /* try to reset EPP timeout bit */
1207 if (ppc_check_epp_timeout(ppc)) {
1208 ppc->ppc_dtm |= PPB_EPP;
1210 if (ppc->ppc_dtm & PPB_ECP) {
1211 /* SMC like chipset found */
1212 ppc->ppc_model = SMC_LIKE;
1213 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1222 /* restore to standard mode */
1223 w_ecr(ppc, PPC_ECR_STD);
1226 /* XXX try to detect NIBBLE and PS2 modes */
1227 ppc->ppc_dtm |= PPB_NIBBLE;
1230 ppc->ppc_avm = chipset_mode;
1232 ppc->ppc_avm = ppc->ppc_dtm;
1237 switch (ppc->ppc_type) {
1238 case PPC_TYPE_SMCLIKE:
1239 ppc_smclike_setmode(ppc, chipset_mode);
1242 ppc_generic_setmode(ppc, chipset_mode);
1246 return (chipset_mode);
1252 * mode is the mode suggested at boot
1255 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1257 #ifdef PPC_PROBE_CHIPSET
1260 /* list of supported chipsets */
1261 int (*chipset_detect[])(struct ppc_data *, int) = {
1263 ppc_smc37c66xgt_detect,
1265 ppc_smc37c935_detect,
1271 /* if can't find the port and mode not forced return error */
1272 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1273 return (EIO); /* failed, port not present */
1275 /* assume centronics compatible mode is supported */
1276 ppc->ppc_avm = PPB_COMPATIBLE;
1278 #ifdef PPC_PROBE_CHIPSET
1279 /* we have to differenciate available chipset modes,
1280 * chipset running modes and IEEE-1284 operating modes
1282 * after detection, the port must support running in compatible mode
1284 if (ppc->ppc_flags & 0x40) {
1286 printf("ppc: chipset forced to generic\n");
1289 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1291 #ifdef PPC_PROBE_CHIPSET
1293 for (i=0; chipset_detect[i] != NULL; i++) {
1294 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1295 ppc->ppc_mode = mode;
1302 /* configure/detect ECP FIFO */
1303 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1304 ppc_detect_fifo(ppc);
1310 * ppc_exec_microseq()
1312 * Execute a microsequence.
1313 * Microsequence mechanism is supposed to handle fast I/O operations.
1316 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1318 struct ppc_data *ppc = DEVTOSOFTC(dev);
1319 struct ppb_microseq *mi;
1329 struct ppb_microseq *stack = NULL;
1331 /* microsequence registers are equivalent to PC-like port registers */
1333 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1334 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1336 #define INCR_PC (mi ++) /* increment program counter */
1338 PPC_ASSERT_LOCKED(ppc);
1341 switch (mi->opcode) {
1343 cc = r_reg(mi->arg[0].i, ppc);
1344 cc &= (char)mi->arg[2].i; /* clear mask */
1345 cc |= (char)mi->arg[1].i; /* assert mask */
1346 w_reg(mi->arg[0].i, ppc, cc);
1350 case MS_OP_RASSERT_P:
1354 if ((len = mi->arg[0].i) == MS_ACCUM) {
1355 accum = ppc->ppc_accum;
1356 for (; accum; accum--)
1357 w_reg(reg, ppc, *ptr++);
1358 ppc->ppc_accum = accum;
1360 for (i=0; i<len; i++)
1361 w_reg(reg, ppc, *ptr++);
1367 case MS_OP_RFETCH_P:
1369 mask = (char)mi->arg[2].i;
1372 if ((len = mi->arg[0].i) == MS_ACCUM) {
1373 accum = ppc->ppc_accum;
1374 for (; accum; accum--)
1375 *ptr++ = r_reg(reg, ppc) & mask;
1376 ppc->ppc_accum = accum;
1378 for (i=0; i<len; i++)
1379 *ptr++ = r_reg(reg, ppc) & mask;
1386 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1394 /* let's suppose the next instr. is the same */
1396 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1397 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1399 if (mi->opcode == MS_OP_DELAY) {
1400 DELAY(mi->arg[0].i);
1409 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1417 iter = mi->arg[1].i;
1418 p = (char *)mi->arg[2].p;
1420 /* XXX delay limited to 255 us */
1421 for (i=0; i<iter; i++) {
1422 w_reg(reg, ppc, *p++);
1423 DELAY((unsigned char)*p++);
1429 ppc->ppc_accum = mi->arg[0].i;
1434 if (--ppc->ppc_accum > 0)
1441 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1448 if ((cc & (char)mi->arg[0].i) == 0)
1455 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1463 * If the C call returns !0 then end the microseq.
1464 * The current state of ptr is passed to the C function
1466 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1473 ppc->ppc_ptr = (char *)mi->arg[0].p;
1479 panic("%s: too much calls", __func__);
1482 /* store the state of the actual
1487 /* jump to the new microsequence */
1488 mi = (struct ppb_microseq *)mi->arg[0].p;
1495 /* retrieve microseq and pc state before the call */
1498 /* reset the stack */
1501 /* XXX return code */
1509 /* can't return to ppb level during the execution
1510 * of a submicrosequence */
1512 panic("%s: can't return to ppb level",
1515 /* update pc for ppb level of execution */
1518 /* return to ppb level of execution */
1522 panic("%s: unknown microsequence opcode 0x%x",
1523 __func__, mi->opcode);
1533 struct ppc_data *ppc = arg;
1534 u_char ctr, ecr, str;
1537 * If we have any child interrupt handlers registered, let
1538 * them handle this interrupt.
1540 * XXX: If DMA is in progress should we just complete that w/o
1544 if (ppc->ppc_intr_hook != NULL &&
1545 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1554 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1555 printf("![%x/%x/%x]", ctr, ecr, str);
1558 /* don't use ecp mode with IRQENABLE set */
1559 if (ctr & IRQENABLE) {
1564 /* interrupts are generated by nFault signal
1565 * only in ECP mode */
1566 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1567 /* check if ppc driver has programmed the
1568 * nFault interrupt */
1569 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1571 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1572 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1574 /* shall be handled by underlying layers XXX */
1580 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1581 /* disable interrupts (should be done by hardware though) */
1582 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1583 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1586 /* check if DMA completed */
1587 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1592 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1595 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1599 ppc->ppc_dmadone(ppc);
1600 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1602 /* wakeup the waiting process */
1606 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1608 /* classic interrupt I/O */
1609 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1617 ppc_read(device_t dev, char *buf, int len, int mode)
1623 ppc_write(device_t dev, char *buf, int len, int how)
1629 ppc_reset_epp(device_t dev)
1631 struct ppc_data *ppc = DEVTOSOFTC(dev);
1633 PPC_ASSERT_LOCKED(ppc);
1634 ppc_reset_epp_timeout(ppc);
1640 ppc_setmode(device_t dev, int mode)
1642 struct ppc_data *ppc = DEVTOSOFTC(dev);
1644 PPC_ASSERT_LOCKED(ppc);
1645 switch (ppc->ppc_type) {
1646 case PPC_TYPE_SMCLIKE:
1647 return (ppc_smclike_setmode(ppc, mode));
1650 case PPC_TYPE_GENERIC:
1652 return (ppc_generic_setmode(ppc, mode));
1661 ppc_probe(device_t dev, int rid)
1664 static short next_bios_ppc = 0;
1666 struct ppc_data *ppc;
1671 * Allocate the ppc_data structure.
1673 ppc = DEVTOSOFTC(dev);
1674 bzero(ppc, sizeof(struct ppc_data));
1676 ppc->rid_ioport = rid;
1678 /* retrieve ISA parameters */
1679 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1683 * If port not specified, use bios list.
1686 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1687 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1688 port = *(BIOS_PORTS + next_bios_ppc++);
1691 "parallel port found at 0x%jx\n", port);
1693 device_printf(dev, "parallel port not found.\n");
1696 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1697 IO_LPTSIZE_EXTENDED);
1701 /* IO port is mandatory */
1703 /* Try "extended" IO port range...*/
1704 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1706 IO_LPTSIZE_EXTENDED,
1709 if (ppc->res_ioport != 0) {
1711 device_printf(dev, "using extended I/O port range\n");
1713 /* Failed? If so, then try the "normal" IO port range... */
1714 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1719 if (ppc->res_ioport != 0) {
1721 device_printf(dev, "using normal I/O port range\n");
1724 device_printf(dev, "cannot reserve I/O port range\n");
1729 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1731 ppc->ppc_flags = device_get_flags(dev);
1733 if (!(ppc->ppc_flags & 0x20)) {
1734 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1737 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1743 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1745 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1748 ppc->ppc_model = GENERIC;
1750 ppc->ppc_mode = PPB_COMPATIBLE;
1751 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1753 ppc->ppc_type = PPC_TYPE_GENERIC;
1756 * Try to detect the chipset and its mode.
1758 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1764 if (ppc->res_irq != 0) {
1765 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1768 if (ppc->res_ioport != 0) {
1769 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1772 if (ppc->res_drq != 0) {
1773 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1780 ppc_attach(device_t dev)
1782 struct ppc_data *ppc = DEVTOSOFTC(dev);
1785 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1787 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1788 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1789 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1790 ppc_epp_protocol[ppc->ppc_epp] : "");
1793 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1794 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1797 /* default to the tty mask for registration */ /* XXX */
1798 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1799 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1802 "failed to register interrupt handler: %d\n",
1804 mtx_destroy(&ppc->ppc_lock);
1809 /* add ppbus as a child of this isa to parallel bridge */
1810 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1813 * Probe the ppbus and attach devices found.
1815 device_probe_and_attach(ppc->ppbus);
1821 ppc_detach(device_t dev)
1823 struct ppc_data *ppc = DEVTOSOFTC(dev);
1825 if (ppc->res_irq == 0) {
1829 /* detach & delete all children */
1830 device_delete_children(dev);
1832 if (ppc->res_irq != 0) {
1833 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1834 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1837 if (ppc->res_ioport != 0) {
1838 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1841 if (ppc->res_drq != 0) {
1842 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1846 mtx_destroy(&ppc->ppc_lock);
1852 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1854 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1856 PPC_ASSERT_LOCKED(ppc);
1859 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1862 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1865 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1868 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1871 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1874 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1877 return (r_dtr(ppc));
1879 return (r_str(ppc));
1881 return (r_ctr(ppc));
1883 return (r_epp_A(ppc));
1885 return (r_epp_D(ppc));
1887 return (r_ecr(ppc));
1889 return (r_fifo(ppc));
1912 panic("%s: unknown I/O operation", __func__);
1916 return (0); /* not significative */
1920 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1922 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1925 case PPC_IVAR_EPP_PROTO:
1926 PPC_ASSERT_LOCKED(ppc);
1927 *val = (u_long)ppc->ppc_epp;
1930 *val = (uintptr_t)&ppc->ppc_lock;
1940 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1942 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1945 case PPC_IVAR_INTR_HANDLER:
1946 PPC_ASSERT_LOCKED(ppc);
1947 if (dev != ppc->ppbus)
1950 ppc->ppc_intr_hook = NULL;
1953 if (ppc->ppc_intr_hook != NULL)
1955 ppc->ppc_intr_hook = (void *)val;
1956 ppc->ppc_intr_arg = device_get_softc(dev);
1966 * We allow child devices to allocate an IRQ resource at rid 0 for their
1967 * interrupt handlers.
1970 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1971 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1973 struct ppc_data *ppc = DEVTOSOFTC(bus);
1978 return (ppc->res_irq);
1985 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1989 struct ppc_data *ppc = DEVTOSOFTC(bus);
1995 KASSERT(r == ppc->res_irq,
1996 ("ppc child IRQ resource mismatch"));
2004 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);