2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/mutex.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
53 #include <machine/vmparam.h>
54 #include <machine/pc/bios.h>
57 #include <dev/ppbus/ppbconf.h>
58 #include <dev/ppbus/ppb_msq.h>
60 #include <dev/ppc/ppcvar.h>
61 #include <dev/ppc/ppcreg.h>
65 static void ppcintr(void *arg);
67 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
68 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
70 #define LOG_PPC(function, ppc, string) \
71 if (bootverbose) printf("%s: %s\n", function, string)
73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
76 * We use critical enter/exit for the simple config locking needed to
77 * detect the devices. We just want to make sure that both of our writes
78 * happen without someone else also writing to those config registers. Since
79 * we just do this at startup, Giant keeps multiple threads from executing,
80 * and critical_enter() then is all that's needed to keep us from being preempted
81 * during the critical sequences with the hardware.
83 * Note: this doesn't prevent multiple threads from putting the chips into
84 * config mode, but since we only do that to detect the type at startup the
85 * extra overhead isn't needed since Giant protects us from multiple entry
86 * and no other code changes these registers.
88 #define PPC_CONFIG_LOCK(ppc) critical_enter()
89 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
91 devclass_t ppc_devclass;
92 const char ppc_driver_name[] = "ppc";
94 static char *ppc_models[] = {
95 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
96 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
97 "SMC FDC37C935", "PC87303", 0
100 /* list of available modes */
101 static char *ppc_avms[] = {
102 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
103 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
104 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
105 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
108 /* list of current executing modes
109 * Note that few modes do not actually exist.
111 static char *ppc_modes[] = {
112 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
113 "EPP", "EPP", "EPP", "ECP",
114 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
115 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
118 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
122 * BIOS printer list - used by BIOS probe.
124 #define BIOS_PPC_PORTS 0x408
125 #define BIOS_PORTS ((short *)BIOS_PADDRTOVADDR(BIOS_PPC_PORTS))
126 #define BIOS_MAX_PPC 4
133 ppc_ecp_sync(device_t dev)
136 struct ppc_data *ppc = DEVTOSOFTC(dev);
138 PPC_ASSERT_LOCKED(ppc);
139 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
143 if ((r & 0xe0) != PPC_ECR_EPP)
146 for (i = 0; i < 100; i++) {
153 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
161 * Detect parallel port FIFO
164 ppc_detect_fifo(struct ppc_data *ppc)
167 char ctr_sav, ctr, cc;
171 ecr_sav = r_ecr(ppc);
172 ctr_sav = r_ctr(ppc);
174 /* enter ECP configuration mode, no interrupt, no DMA */
177 /* read PWord size - transfers in FIFO mode must be PWord aligned */
178 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
180 /* XXX 16 and 32 bits implementations not supported */
181 if (ppc->ppc_pword != PPC_PWORD_8) {
182 LOG_PPC(__func__, ppc, "PWord not supported");
186 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
188 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
190 /* enter ECP test mode, no interrupt, no DMA */
194 for (i=0; i<1024; i++) {
195 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
201 LOG_PPC(__func__, ppc, "can't flush FIFO");
205 /* enable interrupts, no DMA */
208 /* determine readIntrThreshold
209 * fill the FIFO until serviceIntr is set
211 for (i=0; i<1024; i++) {
212 w_fifo(ppc, (char)i);
213 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
214 /* readThreshold reached */
217 if (r_ecr(ppc) & PPC_FIFO_FULL) {
224 LOG_PPC(__func__, ppc, "can't fill FIFO");
228 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
229 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
230 w_ecr(ppc, 0xd0); /* enable interrupts */
232 /* determine writeIntrThreshold
233 * empty the FIFO until serviceIntr is set
235 for (i=ppc->ppc_fifo; i>0; i--) {
236 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
237 LOG_PPC(__func__, ppc, "invalid data in FIFO");
240 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
241 /* writeIntrThreshold reached */
242 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
244 /* if FIFO empty before the last byte, error */
245 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
246 LOG_PPC(__func__, ppc, "data lost in FIFO");
251 /* FIFO must be empty after the last byte */
252 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
253 LOG_PPC(__func__, ppc, "can't empty the FIFO");
270 ppc_detect_port(struct ppc_data *ppc)
273 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
275 if (r_dtr(ppc) != 0xaa)
282 * EPP timeout, according to the PC87332 manual
283 * Semantics of clearing EPP timeout bit.
284 * PC87332 - reading SPP_STR does it...
285 * SMC - write 1 to EPP timeout bit XXX
286 * Others - (?) write 0 to EPP timeout bit
289 ppc_reset_epp_timeout(struct ppc_data *ppc)
295 w_str(ppc, r & 0xfe);
301 ppc_check_epp_timeout(struct ppc_data *ppc)
303 ppc_reset_epp_timeout(ppc);
305 return (!(r_str(ppc) & TIMEOUT));
309 * Configure current operating mode
312 ppc_generic_setmode(struct ppc_data *ppc, int mode)
316 /* check if mode is available */
317 if (mode && !(ppc->ppc_avm & mode))
320 /* if ECP mode, configure ecr register */
321 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
322 /* return to byte mode (keeping direction bit),
323 * no interrupt, no DMA to be able to change to
326 w_ecr(ppc, PPC_ECR_RESET);
327 ecr = PPC_DISABLE_INTR;
331 else if (mode & PPB_ECP)
332 /* select ECP mode */
334 else if (mode & PPB_PS2)
335 /* select PS2 mode with ECP */
338 /* select COMPATIBLE/NIBBLE mode */
344 ppc->ppc_mode = mode;
350 * The ppc driver is free to choose options like FIFO or DMA
351 * if ECP mode is available.
353 * The 'RAW' option allows the upper drivers to force the ppc mode
354 * even with FIFO, DMA available.
357 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
361 /* check if mode is available */
362 if (mode && !(ppc->ppc_avm & mode))
365 /* if ECP mode, configure ecr register */
366 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
367 /* return to byte mode (keeping direction bit),
368 * no interrupt, no DMA to be able to change to
371 w_ecr(ppc, PPC_ECR_RESET);
372 ecr = PPC_DISABLE_INTR;
375 /* select EPP mode */
377 else if (mode & PPB_ECP)
378 /* select ECP mode */
380 else if (mode & PPB_PS2)
381 /* select PS2 mode with ECP */
384 /* select COMPATIBLE/NIBBLE mode */
390 ppc->ppc_mode = mode;
395 #ifdef PPC_PROBE_CHIPSET
399 * Probe for a Natsemi PC873xx-family part.
401 * References in this function are to the National Semiconductor
402 * PC87332 datasheet TL/C/11930, May 1995 revision.
404 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
405 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
406 static int pc873xx_irqtab[] = {5, 7, 5, 0};
408 static int pc873xx_regstab[] = {
409 PC873_FER, PC873_FAR, PC873_PTR,
410 PC873_FCR, PC873_PCR, PC873_PMC,
411 PC873_TUP, PC873_SID, PC873_PNP0,
412 PC873_PNP1, PC873_LPTBA, -1
415 static char *pc873xx_rnametab[] = {
416 "FER", "FAR", "PTR", "FCR", "PCR",
417 "PMC", "TUP", "SID", "PNP0", "PNP1",
422 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
424 static int index = 0;
426 int ptr, pcr, val, i;
428 while ((idport = pc873xx_basetab[index++])) {
430 /* XXX should check first to see if this location is already claimed */
433 * Pull the 873xx through the power-on ID cycle (2.2,1.).
434 * We can't use this to locate the chip as it may already have
435 * been used by the BIOS.
437 (void)inb(idport); (void)inb(idport);
438 (void)inb(idport); (void)inb(idport);
441 * Read the SID byte. Possible values are :
448 outb(idport, PC873_SID);
449 val = inb(idport + 1);
450 if ((val & 0xf0) == 0x10) {
451 ppc->ppc_model = NS_PC87332;
452 } else if ((val & 0xf8) == 0x70) {
453 ppc->ppc_model = NS_PC87306;
454 } else if ((val & 0xf8) == 0x50) {
455 ppc->ppc_model = NS_PC87334;
456 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
457 documentation, but probing
459 ppc->ppc_model = NS_PC87303;
461 if (bootverbose && (val != 0xff))
462 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
463 continue ; /* not recognised */
466 /* print registers */
469 for (i=0; pc873xx_regstab[i] != -1; i++) {
470 outb(idport, pc873xx_regstab[i]);
471 printf(" %s=0x%x", pc873xx_rnametab[i],
472 inb(idport + 1) & 0xff);
478 * We think we have one. Is it enabled and where we want it to be?
480 outb(idport, PC873_FER);
481 val = inb(idport + 1);
482 if (!(val & PC873_PPENABLE)) {
484 printf("PC873xx parallel port disabled\n");
487 outb(idport, PC873_FAR);
488 val = inb(idport + 1);
489 /* XXX we should create a driver instance for every port found */
490 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
492 /* First try to change the port address to that requested... */
494 switch (ppc->ppc_base) {
512 outb(idport, PC873_FAR);
513 outb(idport + 1, val);
514 outb(idport + 1, val);
516 /* Check for success by reading back the value we supposedly
517 wrote and comparing...*/
519 outb(idport, PC873_FAR);
520 val = inb(idport + 1) & 0x3;
522 /* If we fail, report the failure... */
524 if (pc873xx_porttab[val] != ppc->ppc_base) {
526 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
527 pc873xx_porttab[val], ppc->ppc_base);
532 outb(idport, PC873_PTR);
533 ptr = inb(idport + 1);
535 /* get irq settings */
536 if (ppc->ppc_base == 0x378)
537 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
539 irq = pc873xx_irqtab[val];
542 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
545 * Check if irq settings are correct
547 if (irq != ppc->ppc_irq) {
549 * If the chipset is not locked and base address is 0x378,
550 * we have another chance
552 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
553 if (ppc->ppc_irq == 7) {
554 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
555 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
557 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
558 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
561 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
564 printf("PC873xx sorry, can't change irq setting\n");
568 printf("PC873xx irq settings are correct\n");
571 outb(idport, PC873_PCR);
572 pcr = inb(idport + 1);
574 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
576 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
578 ppc->ppc_avm |= PPB_NIBBLE;
582 if (pcr & PC873_EPPEN) {
583 ppc->ppc_avm |= PPB_EPP;
588 if (pcr & PC873_EPP19)
589 ppc->ppc_epp = EPP_1_9;
591 ppc->ppc_epp = EPP_1_7;
593 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
594 outb(idport, PC873_PTR);
595 ptr = inb(idport + 1);
596 if (ptr & PC873_EPPRDIR)
597 printf(", Regular mode");
599 printf(", Automatic mode");
601 } else if (pcr & PC873_ECPEN) {
602 ppc->ppc_avm |= PPB_ECP;
606 if (pcr & PC873_ECPCLK) { /* XXX */
607 ppc->ppc_avm |= PPB_PS2;
612 outb(idport, PC873_PTR);
613 ptr = inb(idport + 1);
614 if (ptr & PC873_EXTENDED) {
615 ppc->ppc_avm |= PPB_SPP;
622 printf("PC873xx unlocked");
624 if (chipset_mode & PPB_ECP) {
625 if ((chipset_mode & PPB_EPP) && bootverbose)
626 printf(", ECP+EPP not supported");
629 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
630 outb(idport + 1, pcr);
631 outb(idport + 1, pcr);
636 } else if (chipset_mode & PPB_EPP) {
637 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
638 pcr |= (PC873_EPPEN | PC873_EPP19);
639 outb(idport + 1, pcr);
640 outb(idport + 1, pcr);
642 ppc->ppc_epp = EPP_1_9; /* XXX */
647 /* enable automatic direction turnover */
648 if (ppc->ppc_model == NS_PC87332) {
649 outb(idport, PC873_PTR);
650 ptr = inb(idport + 1);
651 ptr &= ~PC873_EPPRDIR;
652 outb(idport + 1, ptr);
653 outb(idport + 1, ptr);
656 printf(", Automatic mode");
659 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
660 outb(idport + 1, pcr);
661 outb(idport + 1, pcr);
663 /* configure extended bit in PTR */
664 outb(idport, PC873_PTR);
665 ptr = inb(idport + 1);
667 if (chipset_mode & PPB_PS2) {
668 ptr |= PC873_EXTENDED;
674 /* default to NIBBLE mode */
675 ptr &= ~PC873_EXTENDED;
680 outb(idport + 1, ptr);
681 outb(idport + 1, ptr);
684 ppc->ppc_avm = chipset_mode;
690 ppc->ppc_type = PPC_TYPE_GENERIC;
691 ppc_generic_setmode(ppc, chipset_mode);
693 return(chipset_mode);
699 * ppc_smc37c66xgt_detect
701 * SMC FDC37C66xGT configuration.
704 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
709 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
711 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
714 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
717 * Detection: enter configuration mode and read CRD register.
719 PPC_CONFIG_LOCK(ppc);
720 outb(csr, SMC665_iCODE);
721 outb(csr, SMC665_iCODE);
722 PPC_CONFIG_UNLOCK(ppc);
725 if (inb(cio) == 0x65) {
730 for (i = 0; i < 2; i++) {
731 PPC_CONFIG_LOCK(ppc);
732 outb(csr, SMC666_iCODE);
733 outb(csr, SMC666_iCODE);
734 PPC_CONFIG_UNLOCK(ppc);
737 if (inb(cio) == 0x66) {
742 /* Another chance, CSR may be hard-configured to be at 0x370 */
748 * If chipset not found, do not continue.
751 outb(csr, 0xaa); /* end config mode */
758 /* read the port's address: bits 0 and 1 of CR1 */
759 r = inb(cio) & SMC_CR1_ADDR;
760 if (port_address[(int)r] != ppc->ppc_base) {
761 outb(csr, 0xaa); /* end config mode */
765 ppc->ppc_model = type;
768 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
769 * If SPP mode is detected, try to set ECP+EPP mode
774 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
778 printf(" CR4=0x%x", inb(cio) & 0xff);
785 /* autodetect mode */
787 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
788 if (type == SMC_37C666GT) {
789 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
791 printf(" configuration hardwired, supposing " \
795 if ((inb(cio) & SMC_CR1_MODE) == 0) {
796 /* already in extended parallel port mode, read CR4 */
798 r = (inb(cio) & SMC_CR4_EMODE);
802 ppc->ppc_avm |= PPB_SPP;
808 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
814 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
820 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
822 printf(" ECP+EPP SPP");
826 /* not an extended port mode */
827 ppc->ppc_avm |= PPB_SPP;
834 ppc->ppc_avm = chipset_mode;
836 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
837 if (type == SMC_37C666GT)
841 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
842 /* do not use ECP when the mode is not forced to */
843 outb(cio, r | SMC_CR1_MODE);
847 /* an extended mode is selected */
848 outb(cio, r & ~SMC_CR1_MODE);
850 /* read CR4 register and reset mode field */
852 r = inb(cio) & ~SMC_CR4_EMODE;
854 if (chipset_mode & PPB_ECP) {
855 if (chipset_mode & PPB_EPP) {
856 outb(cio, r | SMC_ECPEPP);
860 outb(cio, r | SMC_ECP);
866 outb(cio, r | SMC_EPPSPP);
871 ppc->ppc_avm = chipset_mode;
874 /* set FIFO threshold to 16 */
875 if (ppc->ppc_avm & PPB_ECP) {
886 if (ppc->ppc_avm & PPB_EPP) {
892 * Set the EPP protocol...
893 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
895 if (ppc->ppc_epp == EPP_1_9)
896 outb(cio, (r & ~SMC_CR4_EPPTYPE));
898 outb(cio, (r | SMC_CR4_EPPTYPE));
901 outb(csr, 0xaa); /* end config mode */
903 ppc->ppc_type = PPC_TYPE_SMCLIKE;
904 ppc_smclike_setmode(ppc, chipset_mode);
906 return (chipset_mode);
910 * SMC FDC37C935 configuration
911 * Found on many Alpha machines
914 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
918 PPC_CONFIG_LOCK(ppc);
919 outb(SMC935_CFG, 0x55); /* enter config mode */
920 outb(SMC935_CFG, 0x55);
921 PPC_CONFIG_UNLOCK(ppc);
923 outb(SMC935_IND, SMC935_ID); /* check device id */
924 if (inb(SMC935_DAT) == 0x2)
928 outb(SMC935_CFG, 0xaa); /* exit config mode */
932 ppc->ppc_model = type;
934 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
935 outb(SMC935_DAT, 3); /* which is logical device 3 */
937 /* set io port base */
938 outb(SMC935_IND, SMC935_PORTHI);
939 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
940 outb(SMC935_IND, SMC935_PORTLO);
941 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
944 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
946 ppc->ppc_avm = chipset_mode;
947 outb(SMC935_IND, SMC935_PPMODE);
948 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
950 /* SPP + EPP or just plain SPP */
951 if (chipset_mode & (PPB_SPP)) {
952 if (chipset_mode & PPB_EPP) {
953 if (ppc->ppc_epp == EPP_1_9) {
954 outb(SMC935_IND, SMC935_PPMODE);
955 outb(SMC935_DAT, SMC935_EPP19SPP);
957 if (ppc->ppc_epp == EPP_1_7) {
958 outb(SMC935_IND, SMC935_PPMODE);
959 outb(SMC935_DAT, SMC935_EPP17SPP);
962 outb(SMC935_IND, SMC935_PPMODE);
963 outb(SMC935_DAT, SMC935_SPP);
967 /* ECP + EPP or just plain ECP */
968 if (chipset_mode & PPB_ECP) {
969 if (chipset_mode & PPB_EPP) {
970 if (ppc->ppc_epp == EPP_1_9) {
971 outb(SMC935_IND, SMC935_PPMODE);
972 outb(SMC935_DAT, SMC935_ECPEPP19);
974 if (ppc->ppc_epp == EPP_1_7) {
975 outb(SMC935_IND, SMC935_PPMODE);
976 outb(SMC935_DAT, SMC935_ECPEPP17);
979 outb(SMC935_IND, SMC935_PPMODE);
980 outb(SMC935_DAT, SMC935_ECP);
985 outb(SMC935_CFG, 0xaa); /* exit config mode */
987 ppc->ppc_type = PPC_TYPE_SMCLIKE;
988 ppc_smclike_setmode(ppc, chipset_mode);
990 return (chipset_mode);
994 * Winbond W83877F stuff
996 * EFER: extended function enable register
997 * EFIR: extended function index register
998 * EFDR: extended function data register
1000 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1001 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1003 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1004 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1005 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1006 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1009 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1012 unsigned char r, hefere, hefras;
1014 for (i = 0; i < 4; i ++) {
1015 /* first try to enable configuration registers */
1016 efer = w83877f_efers[i];
1018 /* write the key to the EFER */
1019 for (j = 0; j < w83877f_keyiter[i]; j ++)
1020 outb (efer, w83877f_keys[i]);
1022 /* then check HEFERE and HEFRAS bits */
1024 hefere = inb(efdr) & WINB_HEFERE;
1027 hefras = inb(efdr) & WINB_HEFRAS;
1031 * 0 1 write 89h to 250h (power-on default)
1032 * 1 0 write 86h twice to 3f0h
1033 * 1 1 write 87h twice to 3f0h
1034 * 0 0 write 88h to 250h
1036 if ((hefere | hefras) == w83877f_hefs[i])
1040 return (-1); /* failed */
1043 /* check base port address - read from CR23 */
1045 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1048 /* read CHIP ID from CR9/bits0-3 */
1051 switch (inb(efdr) & WINB_CHIPID) {
1052 case WINB_W83877F_ID:
1053 ppc->ppc_model = WINB_W83877F;
1056 case WINB_W83877AF_ID:
1057 ppc->ppc_model = WINB_W83877AF;
1061 ppc->ppc_model = WINB_UNKNOWN;
1065 /* dump of registers */
1066 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1067 for (i = 0; i <= 0xd; i ++) {
1069 printf("0x%x ", inb(efdr));
1071 for (i = 0x10; i <= 0x17; i ++) {
1073 printf("0x%x ", inb(efdr));
1076 printf("0x%x ", inb(efdr));
1077 for (i = 0x20; i <= 0x29; i ++) {
1079 printf("0x%x ", inb(efdr));
1084 ppc->ppc_type = PPC_TYPE_GENERIC;
1086 if (!chipset_mode) {
1087 /* autodetect mode */
1091 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1095 r |= (inb(efdr) & WINB_PRTMODS2);
1100 device_printf(ppc->ppc_dev,
1101 "W83757 compatible mode\n");
1102 return (-1); /* generic or SMC-like */
1109 device_printf(ppc->ppc_dev,
1110 "not in parallel port mode\n");
1113 case (WINB_PARALLEL | WINB_EPP_SPP):
1114 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1116 device_printf(ppc->ppc_dev, "EPP SPP\n");
1119 case (WINB_PARALLEL | WINB_ECP):
1120 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1122 device_printf(ppc->ppc_dev, "ECP SPP\n");
1125 case (WINB_PARALLEL | WINB_ECP_EPP):
1126 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1127 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1130 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1133 printf("%s: unknown case (0x%x)!\n", __func__, r);
1139 /* select CR9 and set PRTMODS2 bit */
1141 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1143 /* select CR0 and reset PRTMODSx bits */
1145 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1147 if (chipset_mode & PPB_ECP) {
1148 if (chipset_mode & PPB_EPP) {
1149 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1151 device_printf(ppc->ppc_dev,
1154 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1157 outb(efdr, inb(efdr) | WINB_ECP);
1159 device_printf(ppc->ppc_dev, "ECP\n");
1162 /* select EPP_SPP otherwise */
1163 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1165 device_printf(ppc->ppc_dev, "EPP SPP\n");
1167 ppc->ppc_avm = chipset_mode;
1170 /* exit configuration mode */
1173 switch (ppc->ppc_type) {
1174 case PPC_TYPE_SMCLIKE:
1175 ppc_smclike_setmode(ppc, chipset_mode);
1178 ppc_generic_setmode(ppc, chipset_mode);
1182 return (chipset_mode);
1187 * ppc_generic_detect
1190 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1192 /* default to generic */
1193 ppc->ppc_type = PPC_TYPE_GENERIC;
1196 device_printf(ppc->ppc_dev, "SPP");
1198 /* first, check for ECP */
1199 w_ecr(ppc, PPC_ECR_PS2);
1200 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1201 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1205 /* search for SMC style ECP+EPP mode */
1206 w_ecr(ppc, PPC_ECR_EPP);
1209 /* try to reset EPP timeout bit */
1210 if (ppc_check_epp_timeout(ppc)) {
1211 ppc->ppc_dtm |= PPB_EPP;
1213 if (ppc->ppc_dtm & PPB_ECP) {
1214 /* SMC like chipset found */
1215 ppc->ppc_model = SMC_LIKE;
1216 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1225 /* restore to standard mode */
1226 w_ecr(ppc, PPC_ECR_STD);
1229 /* XXX try to detect NIBBLE and PS2 modes */
1230 ppc->ppc_dtm |= PPB_NIBBLE;
1233 ppc->ppc_avm = chipset_mode;
1235 ppc->ppc_avm = ppc->ppc_dtm;
1240 switch (ppc->ppc_type) {
1241 case PPC_TYPE_SMCLIKE:
1242 ppc_smclike_setmode(ppc, chipset_mode);
1245 ppc_generic_setmode(ppc, chipset_mode);
1249 return (chipset_mode);
1255 * mode is the mode suggested at boot
1258 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1260 #ifdef PPC_PROBE_CHIPSET
1263 /* list of supported chipsets */
1264 int (*chipset_detect[])(struct ppc_data *, int) = {
1266 ppc_smc37c66xgt_detect,
1268 ppc_smc37c935_detect,
1274 /* if can't find the port and mode not forced return error */
1275 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1276 return (EIO); /* failed, port not present */
1278 /* assume centronics compatible mode is supported */
1279 ppc->ppc_avm = PPB_COMPATIBLE;
1281 #ifdef PPC_PROBE_CHIPSET
1282 /* we have to differenciate available chipset modes,
1283 * chipset running modes and IEEE-1284 operating modes
1285 * after detection, the port must support running in compatible mode
1287 if (ppc->ppc_flags & 0x40) {
1289 printf("ppc: chipset forced to generic\n");
1292 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1294 #ifdef PPC_PROBE_CHIPSET
1296 for (i=0; chipset_detect[i] != NULL; i++) {
1297 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1298 ppc->ppc_mode = mode;
1305 /* configure/detect ECP FIFO */
1306 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1307 ppc_detect_fifo(ppc);
1313 * ppc_exec_microseq()
1315 * Execute a microsequence.
1316 * Microsequence mechanism is supposed to handle fast I/O operations.
1319 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1321 struct ppc_data *ppc = DEVTOSOFTC(dev);
1322 struct ppb_microseq *mi;
1332 struct ppb_microseq *stack = NULL;
1334 /* microsequence registers are equivalent to PC-like port registers */
1336 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1337 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1339 #define INCR_PC (mi ++) /* increment program counter */
1341 PPC_ASSERT_LOCKED(ppc);
1344 switch (mi->opcode) {
1346 cc = r_reg(mi->arg[0].i, ppc);
1347 cc &= (char)mi->arg[2].i; /* clear mask */
1348 cc |= (char)mi->arg[1].i; /* assert mask */
1349 w_reg(mi->arg[0].i, ppc, cc);
1353 case MS_OP_RASSERT_P:
1357 if ((len = mi->arg[0].i) == MS_ACCUM) {
1358 accum = ppc->ppc_accum;
1359 for (; accum; accum--)
1360 w_reg(reg, ppc, *ptr++);
1361 ppc->ppc_accum = accum;
1363 for (i=0; i<len; i++)
1364 w_reg(reg, ppc, *ptr++);
1370 case MS_OP_RFETCH_P:
1372 mask = (char)mi->arg[2].i;
1375 if ((len = mi->arg[0].i) == MS_ACCUM) {
1376 accum = ppc->ppc_accum;
1377 for (; accum; accum--)
1378 *ptr++ = r_reg(reg, ppc) & mask;
1379 ppc->ppc_accum = accum;
1381 for (i=0; i<len; i++)
1382 *ptr++ = r_reg(reg, ppc) & mask;
1389 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1397 /* let's suppose the next instr. is the same */
1399 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1400 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1402 if (mi->opcode == MS_OP_DELAY) {
1403 DELAY(mi->arg[0].i);
1412 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1420 iter = mi->arg[1].i;
1421 p = (char *)mi->arg[2].p;
1423 /* XXX delay limited to 255 us */
1424 for (i=0; i<iter; i++) {
1425 w_reg(reg, ppc, *p++);
1426 DELAY((unsigned char)*p++);
1432 ppc->ppc_accum = mi->arg[0].i;
1437 if (--ppc->ppc_accum > 0)
1444 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1451 if ((cc & (char)mi->arg[0].i) == 0)
1458 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1466 * If the C call returns !0 then end the microseq.
1467 * The current state of ptr is passed to the C function
1469 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1476 ppc->ppc_ptr = (char *)mi->arg[0].p;
1482 panic("%s: too much calls", __func__);
1485 /* store the state of the actual
1490 /* jump to the new microsequence */
1491 mi = (struct ppb_microseq *)mi->arg[0].p;
1498 /* retrieve microseq and pc state before the call */
1501 /* reset the stack */
1504 /* XXX return code */
1512 /* can't return to ppb level during the execution
1513 * of a submicrosequence */
1515 panic("%s: can't return to ppb level",
1518 /* update pc for ppb level of execution */
1521 /* return to ppb level of execution */
1525 panic("%s: unknown microsequence opcode 0x%x",
1526 __func__, mi->opcode);
1536 struct ppc_data *ppc = arg;
1537 u_char ctr, ecr, str;
1540 * If we have any child interrupt handlers registered, let
1541 * them handle this interrupt.
1543 * XXX: If DMA is in progress should we just complete that w/o
1547 if (ppc->ppc_intr_hook != NULL &&
1548 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1557 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1558 printf("![%x/%x/%x]", ctr, ecr, str);
1561 /* don't use ecp mode with IRQENABLE set */
1562 if (ctr & IRQENABLE) {
1567 /* interrupts are generated by nFault signal
1568 * only in ECP mode */
1569 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1570 /* check if ppc driver has programmed the
1571 * nFault interrupt */
1572 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1574 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1575 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1577 /* shall be handled by underlying layers XXX */
1583 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1584 /* disable interrupts (should be done by hardware though) */
1585 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1586 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1589 /* check if DMA completed */
1590 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1595 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1598 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1602 ppc->ppc_dmadone(ppc);
1603 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1605 /* wakeup the waiting process */
1609 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1611 /* classic interrupt I/O */
1612 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1620 ppc_read(device_t dev, char *buf, int len, int mode)
1626 ppc_write(device_t dev, char *buf, int len, int how)
1632 ppc_reset_epp(device_t dev)
1634 struct ppc_data *ppc = DEVTOSOFTC(dev);
1636 PPC_ASSERT_LOCKED(ppc);
1637 ppc_reset_epp_timeout(ppc);
1643 ppc_setmode(device_t dev, int mode)
1645 struct ppc_data *ppc = DEVTOSOFTC(dev);
1647 PPC_ASSERT_LOCKED(ppc);
1648 switch (ppc->ppc_type) {
1649 case PPC_TYPE_SMCLIKE:
1650 return (ppc_smclike_setmode(ppc, mode));
1653 case PPC_TYPE_GENERIC:
1655 return (ppc_generic_setmode(ppc, mode));
1664 ppc_probe(device_t dev, int rid)
1667 static short next_bios_ppc = 0;
1669 struct ppc_data *ppc;
1674 * Allocate the ppc_data structure.
1676 ppc = DEVTOSOFTC(dev);
1677 bzero(ppc, sizeof(struct ppc_data));
1679 ppc->rid_ioport = rid;
1681 /* retrieve ISA parameters */
1682 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1686 * If port not specified, use bios list.
1689 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1690 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1691 port = *(BIOS_PORTS + next_bios_ppc++);
1694 "parallel port found at 0x%jx\n", port);
1696 device_printf(dev, "parallel port not found.\n");
1699 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1700 IO_LPTSIZE_EXTENDED);
1704 /* IO port is mandatory */
1706 /* Try "extended" IO port range...*/
1707 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1709 IO_LPTSIZE_EXTENDED,
1712 if (ppc->res_ioport != 0) {
1714 device_printf(dev, "using extended I/O port range\n");
1716 /* Failed? If so, then try the "normal" IO port range... */
1717 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1722 if (ppc->res_ioport != 0) {
1724 device_printf(dev, "using normal I/O port range\n");
1727 device_printf(dev, "cannot reserve I/O port range\n");
1732 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1734 ppc->ppc_flags = device_get_flags(dev);
1736 if (!(ppc->ppc_flags & 0x20)) {
1737 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1740 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1746 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1748 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1751 ppc->ppc_model = GENERIC;
1753 ppc->ppc_mode = PPB_COMPATIBLE;
1754 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1756 ppc->ppc_type = PPC_TYPE_GENERIC;
1759 * Try to detect the chipset and its mode.
1761 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1767 if (ppc->res_irq != 0) {
1768 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1771 if (ppc->res_ioport != 0) {
1772 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1775 if (ppc->res_drq != 0) {
1776 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1783 ppc_attach(device_t dev)
1785 struct ppc_data *ppc = DEVTOSOFTC(dev);
1788 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1790 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1791 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1792 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1793 ppc_epp_protocol[ppc->ppc_epp] : "");
1796 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1797 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1800 /* default to the tty mask for registration */ /* XXX */
1801 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1802 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1805 "failed to register interrupt handler: %d\n",
1807 mtx_destroy(&ppc->ppc_lock);
1812 /* add ppbus as a child of this isa to parallel bridge */
1813 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1816 * Probe the ppbus and attach devices found.
1818 device_probe_and_attach(ppc->ppbus);
1824 ppc_detach(device_t dev)
1826 struct ppc_data *ppc = DEVTOSOFTC(dev);
1828 if (ppc->res_irq == 0) {
1832 /* detach & delete all children */
1833 device_delete_children(dev);
1835 if (ppc->res_irq != 0) {
1836 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1837 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1840 if (ppc->res_ioport != 0) {
1841 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1844 if (ppc->res_drq != 0) {
1845 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1849 mtx_destroy(&ppc->ppc_lock);
1855 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1857 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1859 PPC_ASSERT_LOCKED(ppc);
1862 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1865 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1868 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1871 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1874 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1877 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1880 return (r_dtr(ppc));
1882 return (r_str(ppc));
1884 return (r_ctr(ppc));
1886 return (r_epp_A(ppc));
1888 return (r_epp_D(ppc));
1890 return (r_ecr(ppc));
1892 return (r_fifo(ppc));
1915 panic("%s: unknown I/O operation", __func__);
1919 return (0); /* not significative */
1923 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1925 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1928 case PPC_IVAR_EPP_PROTO:
1929 PPC_ASSERT_LOCKED(ppc);
1930 *val = (u_long)ppc->ppc_epp;
1933 *val = (uintptr_t)&ppc->ppc_lock;
1943 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1945 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1948 case PPC_IVAR_INTR_HANDLER:
1949 PPC_ASSERT_LOCKED(ppc);
1950 if (dev != ppc->ppbus)
1953 ppc->ppc_intr_hook = NULL;
1956 if (ppc->ppc_intr_hook != NULL)
1958 ppc->ppc_intr_hook = (void *)val;
1959 ppc->ppc_intr_arg = device_get_softc(dev);
1969 * We allow child devices to allocate an IRQ resource at rid 0 for their
1970 * interrupt handlers.
1973 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1974 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1976 struct ppc_data *ppc = DEVTOSOFTC(bus);
1981 return (ppc->res_irq);
1988 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1992 struct ppc_data *ppc = DEVTOSOFTC(bus);
1998 KASSERT(r == ppc->res_irq,
1999 ("ppc child IRQ resource mismatch"));
2007 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);