2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/_lock.h>
33 #include <sys/_mutex.h>
36 * Parallel Port Chipset type.
39 #define SMC_37C665GT 1
40 #define SMC_37C666GT 2
43 #define INTEL_820191AA 5 /* XXX not implemented */
45 #define WINB_W83877F 7
46 #define WINB_W83877AF 8
47 #define WINB_UNKNOWN 9
53 * Parallel Port Chipset Type. SMC versus GENERIC (others)
55 #define PPC_TYPE_SMCLIKE 0
56 #define PPC_TYPE_GENERIC 1
59 * Generic structure to hold parallel port chipset info.
63 int ppc_model; /* chipset model if detected */
64 int ppc_type; /* generic or smclike chipset type */
66 int ppc_mode; /* chipset current mode */
67 int ppc_avm; /* chipset available modes */
68 int ppc_dtm; /* chipset detected modes */
70 #define PPC_IRQ_NONE 0x0
71 #define PPC_IRQ_nACK 0x1
72 #define PPC_IRQ_DMA 0x2
73 #define PPC_IRQ_FIFO 0x4
74 #define PPC_IRQ_nFAULT 0x8
75 int ppc_irqstat; /* remind irq settings */
77 #define PPC_DMA_INIT 0x01
78 #define PPC_DMA_STARTED 0x02
79 #define PPC_DMA_COMPLETE 0x03
80 #define PPC_DMA_INTERRUPTED 0x04
81 #define PPC_DMA_ERROR 0x05
82 int ppc_dmastat; /* dma state */
83 int ppc_dmachan; /* dma channel */
84 int ppc_dmaflags; /* dma transfer flags */
85 caddr_t ppc_dmaddr; /* buffer address */
86 u_int ppc_dmacnt; /* count of bytes sent with dma */
87 void (*ppc_dmadone)(struct ppc_data*);
89 #define PPC_PWORD_MASK 0x30
90 #define PPC_PWORD_16 0x00
91 #define PPC_PWORD_8 0x10
92 #define PPC_PWORD_32 0x20
93 char ppc_pword; /* PWord size */
94 short ppc_fifo; /* FIFO threshold */
96 short ppc_wthr; /* writeIntrThresold */
97 short ppc_rthr; /* readIntrThresold */
99 char *ppc_ptr; /* microseq current pointer */
100 int ppc_accum; /* microseq accumulator */
101 int ppc_base; /* parallel port base address */
102 int ppc_epp; /* EPP mode (1.7 or 1.9) */
105 unsigned char ppc_flags;
107 device_t ppbus; /* parallel port chipset corresponding ppbus */
109 int rid_irq, rid_drq, rid_ioport;
110 struct resource *res_irq, *res_drq, *res_ioport;
114 ppc_intr_handler ppc_intr_hook;
120 #define PPC_LOCK(data) mtx_lock(&(data)->ppc_lock)
121 #define PPC_UNLOCK(data) mtx_unlock(&(data)->ppc_lock)
122 #define PPC_ASSERT_LOCKED(data) mtx_assert(&(data)->ppc_lock, MA_OWNED)
125 * Parallel Port Chipset registers.
127 #define PPC_SPP_DTR 0 /* SPP data register */
128 #define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */
129 #define PPC_SPP_STR 1 /* SPP status register */
130 #define PPC_SPP_CTR 2 /* SPP control register */
131 #define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */
132 #define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
133 #if defined(__i386__) && defined(PC98)
134 #define PPC_1284_ENABLE 0x09 /* IEEE STD 1284 Enable register */
135 #define PPC_ECP_D_FIFO 0x0c /* ECP Data fifo register */
136 #define PPC_ECP_CNFGA 0x0c /* Configuration register A */
137 #define PPC_ECP_CNFGB 0x0d /* Configuration register B */
138 #define PPC_ECP_ECR 0x0e /* ECP extended control register */
140 #define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
141 #define PPC_ECP_CNFGA 0x400 /* Configuration register A */
142 #define PPC_ECP_CNFGB 0x401 /* Configuration register B */
143 #define PPC_ECP_ECR 0x402 /* ECP extended control register */
146 #define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
147 #define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
148 #define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
149 #define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
150 #define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
151 #define PPC_ECR_STD 0x0
152 #define PPC_ECR_PS2 0x20
153 #define PPC_ECR_FIFO 0x40
154 #define PPC_ECR_ECP 0x60
155 #define PPC_ECR_EPP 0x80
157 #define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR)
158 #define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR)
160 #define r_dtr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_DTR))
161 #define r_str(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_STR))
162 #define r_ctr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_CTR))
164 #define r_epp_A(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_ADDR))
165 #define r_epp_D(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_DATA))
166 #define r_cnfgA(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGA))
167 #define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB))
168 #define r_ecr(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_ECR))
169 #define r_fifo(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_D_FIFO))
171 #define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte))
172 #define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte))
173 #define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte))
175 #define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte))
176 #define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte))
177 #define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte))
178 #define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte))
181 * Register defines for the PC873xx parts
184 #define PC873_FER 0x00
185 #define PC873_PPENABLE (1<<0)
186 #define PC873_FAR 0x01
187 #define PC873_PTR 0x02
188 #define PC873_CFGLOCK (1<<6)
189 #define PC873_EPPRDIR (1<<7)
190 #define PC873_EXTENDED (1<<7)
191 #define PC873_LPTBIRQ7 (1<<3)
192 #define PC873_FCR 0x03
193 #define PC873_ZWS (1<<5)
194 #define PC873_ZWSPWDN (1<<6)
195 #define PC873_PCR 0x04
196 #define PC873_EPPEN (1<<0)
197 #define PC873_EPP19 (1<<1)
198 #define PC873_ECPEN (1<<2)
199 #define PC873_ECPCLK (1<<3)
200 #define PC873_PMC 0x06
201 #define PC873_TUP 0x07
202 #define PC873_SID 0x08
203 #define PC873_PNP0 0x1b
204 #define PC873_PNP1 0x1c
205 #define PC873_LPTBA 0x19
208 * Register defines for the SMC FDC37C66xGT parts
212 #define SMC665_iCODE 0x55
213 #define SMC666_iCODE 0x44
215 /* Base configuration ports */
216 #define SMC66x_CSR 0x3F0
217 #define SMC666_CSR 0x370 /* hard-configured value for 666 */
220 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
221 #define SMC_CR1_MODE (1<<3) /* bit 3 */
222 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
223 #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
226 #define SMC_SPP 0x0 /* SPP */
227 #define SMC_EPPSPP 0x1 /* EPP and SPP */
228 #define SMC_ECP 0x2 /* ECP */
229 #define SMC_ECPEPP 0x3 /* ECP and EPP */
232 * Register defines for the SMC FDC37C935 parts
235 /* Configuration ports */
236 #define SMC935_CFG 0x370
237 #define SMC935_IND 0x370
238 #define SMC935_DAT 0x371
241 #define SMC935_LOGDEV 0x7
242 #define SMC935_ID 0x20
243 #define SMC935_PORTHI 0x60
244 #define SMC935_PORTLO 0x61
245 #define SMC935_PPMODE 0xf0
247 /* Parallel port modes */
248 #define SMC935_SPP 0x38 + 0
249 #define SMC935_EPP19SPP 0x38 + 1
250 #define SMC935_ECP 0x38 + 2
251 #define SMC935_ECPEPP19 0x38 + 3
252 #define SMC935_CENT 0x38 + 4
253 #define SMC935_EPP17SPP 0x38 + 5
254 #define SMC935_UNUSED 0x38 + 6
255 #define SMC935_ECPEPP17 0x38 + 7
258 * Register defines for the Winbond W83877F parts
261 #define WINB_W83877F_ID 0xa
262 #define WINB_W83877AF_ID 0xb
264 /* Configuration bits */
265 #define WINB_HEFERE (1<<5) /* CROC bit 5 */
266 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
268 #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
269 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */
271 #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
272 #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
273 #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
275 /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
276 #define WINB_W83757 0x0
277 #define WINB_EXTFDC 0x4
278 #define WINB_EXTADP 0x8
279 #define WINB_EXT2FDD 0xc
280 #define WINB_JOYSTICK 0x80
282 #define WINB_PARALLEL 0x80
283 #define WINB_EPP_SPP 0x4
285 #define WINB_ECP_EPP 0xc