2 * Copyright (c) 2006 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/sysctl.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
45 #include <dev/pci/pcivar.h>
47 #include <dev/puc/puc_bus.h>
48 #include <dev/puc/puc_cfg.h>
49 #include <dev/puc/puc_bfe.h>
51 static puc_config_f puc_config_amc;
52 static puc_config_f puc_config_diva;
53 static puc_config_f puc_config_exar;
54 static puc_config_f puc_config_exar_pcie;
55 static puc_config_f puc_config_icbook;
56 static puc_config_f puc_config_moxa;
57 static puc_config_f puc_config_oxford_pci954;
58 static puc_config_f puc_config_oxford_pcie;
59 static puc_config_f puc_config_quatech;
60 static puc_config_f puc_config_syba;
61 static puc_config_f puc_config_siig;
62 static puc_config_f puc_config_sunix;
63 static puc_config_f puc_config_timedia;
64 static puc_config_f puc_config_titan;
66 const struct puc_cfg puc_pci_devices[] = {
68 { 0x0009, 0x7168, 0xffff, 0,
71 PUC_PORT_2S, 0x10, 0, 8,
74 { 0x103c, 0x1048, 0x103c, 0x1049,
75 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
77 PUC_PORT_3S, 0x10, 0, -1,
78 .config_function = puc_config_diva
81 { 0x103c, 0x1048, 0x103c, 0x104a,
82 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
84 PUC_PORT_2S, 0x10, 0, -1,
85 .config_function = puc_config_diva
88 { 0x103c, 0x1048, 0x103c, 0x104b,
89 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
91 PUC_PORT_4S, 0x10, 0, -1,
92 .config_function = puc_config_diva
95 { 0x103c, 0x1048, 0x103c, 0x1223,
96 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
98 PUC_PORT_3S, 0x10, 0, -1,
99 .config_function = puc_config_diva
102 { 0x103c, 0x1048, 0x103c, 0x1226,
103 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
105 PUC_PORT_3S, 0x10, 0, -1,
106 .config_function = puc_config_diva
109 { 0x103c, 0x1048, 0x103c, 0x1282,
110 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
112 PUC_PORT_3S, 0x10, 0, -1,
113 .config_function = puc_config_diva
116 { 0x10b5, 0x1076, 0x10b5, 0x1076,
119 PUC_PORT_8S, 0x18, 0, 8,
122 { 0x10b5, 0x1077, 0x10b5, 0x1077,
125 PUC_PORT_4S, 0x18, 0, 8,
128 { 0x10b5, 0x1103, 0x10b5, 0x1103,
131 PUC_PORT_2S, 0x18, 4, 0,
135 * Boca Research Turbo Serial 658 (8 serial port) card.
136 * Appears to be the same as Chase Research PLC PCI-FAST8
137 * and Perle PCI-FAST8 Multi-Port serial cards.
139 { 0x10b5, 0x9050, 0x12e0, 0x0021,
140 "Boca Research Turbo Serial 658",
142 PUC_PORT_8S, 0x18, 0, 8,
145 { 0x10b5, 0x9050, 0x12e0, 0x0031,
146 "Boca Research Turbo Serial 654",
148 PUC_PORT_4S, 0x18, 0, 8,
152 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
153 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
154 * into the subsystem fields, and claims that it's a
155 * network/misc (0x02/0x80) device.
157 { 0x10b5, 0x9050, 0xd84d, 0x6808,
158 "Dolphin Peripherals 4035",
160 PUC_PORT_2S, 0x18, 4, 0,
164 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
165 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
166 * into the subsystem fields, and claims that it's a
167 * network/misc (0x02/0x80) device.
169 { 0x10b5, 0x9050, 0xd84d, 0x6810,
170 "Dolphin Peripherals 4014",
172 PUC_PORT_2P, 0x20, 4, 0,
175 { 0x10e8, 0x818e, 0xffff, 0,
176 "Applied Micro Circuits 8 Port UART",
178 PUC_PORT_8S, 0x14, -1, -1,
179 .config_function = puc_config_amc
182 { 0x11fe, 0x8010, 0xffff, 0,
183 "Comtrol RocketPort 550/8 RJ11 part A",
185 PUC_PORT_4S, 0x10, 0, 8,
188 { 0x11fe, 0x8011, 0xffff, 0,
189 "Comtrol RocketPort 550/8 RJ11 part B",
191 PUC_PORT_4S, 0x10, 0, 8,
194 { 0x11fe, 0x8012, 0xffff, 0,
195 "Comtrol RocketPort 550/8 Octa part A",
197 PUC_PORT_4S, 0x10, 0, 8,
200 { 0x11fe, 0x8013, 0xffff, 0,
201 "Comtrol RocketPort 550/8 Octa part B",
203 PUC_PORT_4S, 0x10, 0, 8,
206 { 0x11fe, 0x8014, 0xffff, 0,
207 "Comtrol RocketPort 550/4 RJ45",
209 PUC_PORT_4S, 0x10, 0, 8,
212 { 0x11fe, 0x8015, 0xffff, 0,
213 "Comtrol RocketPort 550/Quad",
215 PUC_PORT_4S, 0x10, 0, 8,
218 { 0x11fe, 0x8016, 0xffff, 0,
219 "Comtrol RocketPort 550/16 part A",
221 PUC_PORT_4S, 0x10, 0, 8,
224 { 0x11fe, 0x8017, 0xffff, 0,
225 "Comtrol RocketPort 550/16 part B",
227 PUC_PORT_12S, 0x10, 0, 8,
230 { 0x11fe, 0x8018, 0xffff, 0,
231 "Comtrol RocketPort 550/8 part A",
233 PUC_PORT_4S, 0x10, 0, 8,
236 { 0x11fe, 0x8019, 0xffff, 0,
237 "Comtrol RocketPort 550/8 part B",
239 PUC_PORT_4S, 0x10, 0, 8,
243 * IBM SurePOS 300 Series (481033H) serial ports
244 * Details can be found on the IBM RSS websites
247 { 0x1014, 0x0297, 0xffff, 0,
248 "IBM SurePOS 300 Series (481033H) serial ports",
250 PUC_PORT_4S, 0x10, 4, 0
256 * SIIG provides documentation for their boards at:
257 * <URL:http://www.siig.com/downloads.asp>
260 { 0x131f, 0x1010, 0xffff, 0,
261 "SIIG Cyber I/O PCI 16C550 (10x family)",
263 PUC_PORT_1S1P, 0x18, 4, 0,
266 { 0x131f, 0x1011, 0xffff, 0,
267 "SIIG Cyber I/O PCI 16C650 (10x family)",
269 PUC_PORT_1S1P, 0x18, 4, 0,
272 { 0x131f, 0x1012, 0xffff, 0,
273 "SIIG Cyber I/O PCI 16C850 (10x family)",
275 PUC_PORT_1S1P, 0x18, 4, 0,
278 { 0x131f, 0x1021, 0xffff, 0,
279 "SIIG Cyber Parallel Dual PCI (10x family)",
281 PUC_PORT_2P, 0x18, 8, 0,
284 { 0x131f, 0x1030, 0xffff, 0,
285 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
287 PUC_PORT_2S, 0x18, 4, 0,
290 { 0x131f, 0x1031, 0xffff, 0,
291 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
293 PUC_PORT_2S, 0x18, 4, 0,
296 { 0x131f, 0x1032, 0xffff, 0,
297 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
299 PUC_PORT_2S, 0x18, 4, 0,
302 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
303 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
305 PUC_PORT_2S1P, 0x18, 4, 0,
308 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
309 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
311 PUC_PORT_2S1P, 0x18, 4, 0,
314 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
315 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
317 PUC_PORT_2S1P, 0x18, 4, 0,
320 { 0x131f, 0x1050, 0xffff, 0,
321 "SIIG Cyber 4S PCI 16C550 (10x family)",
323 PUC_PORT_4S, 0x18, 4, 0,
326 { 0x131f, 0x1051, 0xffff, 0,
327 "SIIG Cyber 4S PCI 16C650 (10x family)",
329 PUC_PORT_4S, 0x18, 4, 0,
332 { 0x131f, 0x1052, 0xffff, 0,
333 "SIIG Cyber 4S PCI 16C850 (10x family)",
335 PUC_PORT_4S, 0x18, 4, 0,
338 { 0x131f, 0x2010, 0xffff, 0,
339 "SIIG Cyber I/O PCI 16C550 (20x family)",
341 PUC_PORT_1S1P, 0x10, 4, 0,
344 { 0x131f, 0x2011, 0xffff, 0,
345 "SIIG Cyber I/O PCI 16C650 (20x family)",
347 PUC_PORT_1S1P, 0x10, 4, 0,
350 { 0x131f, 0x2012, 0xffff, 0,
351 "SIIG Cyber I/O PCI 16C850 (20x family)",
353 PUC_PORT_1S1P, 0x10, 4, 0,
356 { 0x131f, 0x2021, 0xffff, 0,
357 "SIIG Cyber Parallel Dual PCI (20x family)",
359 PUC_PORT_2P, 0x10, 8, 0,
362 { 0x131f, 0x2030, 0xffff, 0,
363 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
365 PUC_PORT_2S, 0x10, 4, 0,
368 { 0x131f, 0x2031, 0xffff, 0,
369 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
371 PUC_PORT_2S, 0x10, 4, 0,
374 { 0x131f, 0x2032, 0xffff, 0,
375 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
377 PUC_PORT_2S, 0x10, 4, 0,
380 { 0x131f, 0x2040, 0xffff, 0,
381 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
383 PUC_PORT_1S2P, 0x10, -1, 0,
384 .config_function = puc_config_siig
387 { 0x131f, 0x2041, 0xffff, 0,
388 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
390 PUC_PORT_1S2P, 0x10, -1, 0,
391 .config_function = puc_config_siig
394 { 0x131f, 0x2042, 0xffff, 0,
395 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
397 PUC_PORT_1S2P, 0x10, -1, 0,
398 .config_function = puc_config_siig
401 { 0x131f, 0x2050, 0xffff, 0,
402 "SIIG Cyber 4S PCI 16C550 (20x family)",
404 PUC_PORT_4S, 0x10, 4, 0,
407 { 0x131f, 0x2051, 0xffff, 0,
408 "SIIG Cyber 4S PCI 16C650 (20x family)",
410 PUC_PORT_4S, 0x10, 4, 0,
413 { 0x131f, 0x2052, 0xffff, 0,
414 "SIIG Cyber 4S PCI 16C850 (20x family)",
416 PUC_PORT_4S, 0x10, 4, 0,
419 { 0x131f, 0x2060, 0xffff, 0,
420 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
422 PUC_PORT_2S1P, 0x10, 4, 0,
425 { 0x131f, 0x2061, 0xffff, 0,
426 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
428 PUC_PORT_2S1P, 0x10, 4, 0,
431 { 0x131f, 0x2062, 0xffff, 0,
432 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
434 PUC_PORT_2S1P, 0x10, 4, 0,
437 { 0x131f, 0x2081, 0xffff, 0,
438 "SIIG PS8000 8S PCI 16C650 (20x family)",
440 PUC_PORT_8S, 0x10, -1, -1,
441 .config_function = puc_config_siig
444 { 0x135c, 0x0010, 0xffff, 0,
446 -3, /* max 8x clock rate */
447 PUC_PORT_4S, 0x14, 0, 8,
448 .config_function = puc_config_quatech
451 { 0x135c, 0x0020, 0xffff, 0,
453 -1, /* max 2x clock rate */
454 PUC_PORT_2S, 0x14, 0, 8,
455 .config_function = puc_config_quatech
458 { 0x135c, 0x0030, 0xffff, 0,
459 "Quatech DSC-200/300",
460 -1, /* max 2x clock rate */
461 PUC_PORT_2S, 0x14, 0, 8,
462 .config_function = puc_config_quatech
465 { 0x135c, 0x0040, 0xffff, 0,
466 "Quatech QSC-200/300",
467 -3, /* max 8x clock rate */
468 PUC_PORT_4S, 0x14, 0, 8,
469 .config_function = puc_config_quatech
472 { 0x135c, 0x0050, 0xffff, 0,
474 -3, /* max 8x clock rate */
475 PUC_PORT_8S, 0x14, 0, 8,
476 .config_function = puc_config_quatech
479 { 0x135c, 0x0060, 0xffff, 0,
481 -3, /* max 8x clock rate */
482 PUC_PORT_8S, 0x14, 0, 8,
483 .config_function = puc_config_quatech
486 { 0x135c, 0x0170, 0xffff, 0,
488 -1, /* max 2x clock rate */
489 PUC_PORT_4S, 0x18, 0, 8,
490 .config_function = puc_config_quatech
493 { 0x135c, 0x0180, 0xffff, 0,
495 -1, /* max 3x clock rate */
496 PUC_PORT_2S, 0x18, 0, 8,
497 .config_function = puc_config_quatech
500 { 0x135c, 0x01b0, 0xffff, 0,
501 "Quatech DSCLP-200/300",
502 -1, /* max 2x clock rate */
503 PUC_PORT_2S, 0x18, 0, 8,
504 .config_function = puc_config_quatech
507 { 0x135c, 0x01e0, 0xffff, 0,
509 -3, /* max 8x clock rate */
510 PUC_PORT_8S, 0x10, 0, 8,
511 .config_function = puc_config_quatech
514 { 0x1393, 0x1024, 0xffff, 0,
515 "Moxa Technologies, Smartio CP-102E/PCIe",
517 PUC_PORT_2S, 0x14, 0, -1,
518 .config_function = puc_config_moxa
521 { 0x1393, 0x1025, 0xffff, 0,
522 "Moxa Technologies, Smartio CP-102EL/PCIe",
524 PUC_PORT_2S, 0x14, 0, -1,
525 .config_function = puc_config_moxa
528 { 0x1393, 0x1040, 0xffff, 0,
529 "Moxa Technologies, Smartio C104H/PCI",
531 PUC_PORT_4S, 0x18, 0, 8,
534 { 0x1393, 0x1041, 0xffff, 0,
535 "Moxa Technologies, Smartio CP-104UL/PCI",
537 PUC_PORT_4S, 0x18, 0, 8,
540 { 0x1393, 0x1042, 0xffff, 0,
541 "Moxa Technologies, Smartio CP-104JU/PCI",
543 PUC_PORT_4S, 0x18, 0, 8,
546 { 0x1393, 0x1043, 0xffff, 0,
547 "Moxa Technologies, Smartio CP-104EL/PCIe",
549 PUC_PORT_4S, 0x18, 0, 8,
552 { 0x1393, 0x1045, 0xffff, 0,
553 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
555 PUC_PORT_4S, 0x14, 0, -1,
556 .config_function = puc_config_moxa
559 { 0x1393, 0x1120, 0xffff, 0,
560 "Moxa Technologies, CP-112UL",
562 PUC_PORT_2S, 0x18, 0, 8,
565 { 0x1393, 0x1141, 0xffff, 0,
566 "Moxa Technologies, Industio CP-114",
568 PUC_PORT_4S, 0x18, 0, 8,
571 { 0x1393, 0x1144, 0xffff, 0,
572 "Moxa Technologies, Smartio CP-114EL/PCIe",
574 PUC_PORT_4S, 0x14, 0, -1,
575 .config_function = puc_config_moxa
578 { 0x1393, 0x1182, 0xffff, 0,
579 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
581 PUC_PORT_8S, 0x14, 0, -1,
582 .config_function = puc_config_moxa
585 { 0x1393, 0x1680, 0xffff, 0,
586 "Moxa Technologies, C168H/PCI",
588 PUC_PORT_8S, 0x18, 0, 8,
591 { 0x1393, 0x1681, 0xffff, 0,
592 "Moxa Technologies, C168U/PCI",
594 PUC_PORT_8S, 0x18, 0, 8,
597 { 0x1393, 0x1682, 0xffff, 0,
598 "Moxa Technologies, CP-168EL/PCIe",
600 PUC_PORT_8S, 0x18, 0, 8,
603 { 0x1393, 0x1683, 0xffff, 0,
604 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
606 PUC_PORT_8S, 0x14, 0, -1,
607 .config_function = puc_config_moxa
610 { 0x13a8, 0x0152, 0xffff, 0,
613 PUC_PORT_2S, 0x10, 0, -1,
614 .config_function = puc_config_exar
617 { 0x13a8, 0x0154, 0xffff, 0,
620 PUC_PORT_4S, 0x10, 0, -1,
621 .config_function = puc_config_exar
624 { 0x13a8, 0x0158, 0xffff, 0,
627 PUC_PORT_8S, 0x10, 0, -1,
628 .config_function = puc_config_exar
631 { 0x13a8, 0x0258, 0xffff, 0,
634 PUC_PORT_8S, 0x10, 0, -1,
635 .config_function = puc_config_exar
638 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
639 { 0x13a8, 0x0358, 0xffff, 0,
642 PUC_PORT_8S, 0x10, 0, -1,
643 .config_function = puc_config_exar_pcie
646 { 0x13fe, 0x1600, 0x1602, 0x0002,
647 "Advantech PCI-1602",
649 PUC_PORT_2S, 0x10, 0, 8,
652 { 0x1407, 0x0100, 0xffff, 0,
653 "Lava Computers Dual Serial",
655 PUC_PORT_2S, 0x10, 4, 0,
658 { 0x1407, 0x0101, 0xffff, 0,
659 "Lava Computers Quatro A",
661 PUC_PORT_2S, 0x10, 4, 0,
664 { 0x1407, 0x0102, 0xffff, 0,
665 "Lava Computers Quatro B",
667 PUC_PORT_2S, 0x10, 4, 0,
670 { 0x1407, 0x0120, 0xffff, 0,
671 "Lava Computers Quattro-PCI A",
673 PUC_PORT_2S, 0x10, 4, 0,
676 { 0x1407, 0x0121, 0xffff, 0,
677 "Lava Computers Quattro-PCI B",
679 PUC_PORT_2S, 0x10, 4, 0,
682 { 0x1407, 0x0180, 0xffff, 0,
683 "Lava Computers Octo A",
685 PUC_PORT_4S, 0x10, 4, 0,
688 { 0x1407, 0x0181, 0xffff, 0,
689 "Lava Computers Octo B",
691 PUC_PORT_4S, 0x10, 4, 0,
694 { 0x1409, 0x7268, 0xffff, 0,
697 PUC_PORT_2P, 0x10, 0, 8,
700 { 0x1409, 0x7168, 0xffff, 0,
703 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
704 .config_function = puc_config_timedia
708 * Boards with an Oxford Semiconductor chip.
710 * Oxford Semiconductor provides documentation for their chip at:
711 * <URL:http://www.plxtech.com/products/uart/>
713 * As sold by Kouwell <URL:http://www.kouwell.com/>.
714 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
717 0x1415, 0x9501, 0x10fc, 0xc070,
718 "I-O DATA RSA-PCI2/R",
720 PUC_PORT_2S, 0x10, 0, 8,
723 { 0x1415, 0x9501, 0x131f, 0x2050,
724 "SIIG Cyber 4 PCI 16550",
726 PUC_PORT_4S, 0x10, 0, 8,
729 { 0x1415, 0x9501, 0x131f, 0x2051,
730 "SIIG Cyber 4S PCI 16C650 (20x family)",
732 PUC_PORT_4S, 0x10, 0, 8,
735 { 0x1415, 0x9501, 0x131f, 0x2052,
736 "SIIG Quartet Serial 850",
738 PUC_PORT_4S, 0x10, 0, 8,
741 { 0x1415, 0x9501, 0x14db, 0x2150,
742 "Kuroutoshikou SERIAL4P-LPPCI2",
744 PUC_PORT_4S, 0x10, 0, 8,
747 { 0x1415, 0x9501, 0xffff, 0,
748 "Oxford Semiconductor OX16PCI954 UARTs",
750 PUC_PORT_4S, 0x10, 0, 8,
751 .config_function = puc_config_oxford_pci954
754 { 0x1415, 0x950a, 0x131f, 0x2030,
755 "SIIG Cyber 2S PCIe",
757 PUC_PORT_2S, 0x10, 0, 8,
760 { 0x1415, 0x950a, 0x131f, 0x2032,
761 "SIIG Cyber Serial Dual PCI 16C850",
763 PUC_PORT_4S, 0x10, 0, 8,
766 { 0x1415, 0x950a, 0xffff, 0,
767 "Oxford Semiconductor OX16PCI954 UARTs",
769 PUC_PORT_4S, 0x10, 0, 8,
772 { 0x1415, 0x9511, 0xffff, 0,
773 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
775 PUC_PORT_4S, 0x10, 0, 8,
778 { 0x1415, 0x9521, 0xffff, 0,
779 "Oxford Semiconductor OX16PCI952 UARTs",
781 PUC_PORT_2S, 0x10, 4, 0,
784 { 0x1415, 0x9538, 0xffff, 0,
785 "Oxford Semiconductor OX16PCI958 UARTs",
787 PUC_PORT_8S, 0x18, 0, 8,
791 * Perle boards use Oxford Semiconductor chips, but they store the
792 * Oxford Semiconductor device ID as a subvendor device ID and use
793 * their own device IDs.
796 { 0x155f, 0x0331, 0xffff, 0,
797 "Perle Ultraport4 Express",
799 PUC_PORT_4S, 0x10, 0, 8,
802 { 0x155f, 0xB012, 0xffff, 0,
805 PUC_PORT_2S, 0x10, 0, 8,
808 { 0x155f, 0xB022, 0xffff, 0,
811 PUC_PORT_2S, 0x10, 0, 8,
814 { 0x155f, 0xB004, 0xffff, 0,
817 PUC_PORT_4S, 0x10, 0, 8,
820 { 0x155f, 0xB008, 0xffff, 0,
823 PUC_PORT_8S, 0x10, 0, 8,
828 * Oxford Semiconductor PCI Express Expresso family
830 * Found in many 'native' PCI Express serial boards such as:
832 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
833 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
835 * Lindy 51189 (4 port)
836 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
838 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
839 * <URL:http://www.startech.com>
842 { 0x1415, 0xc11b, 0xffff, 0,
843 "Oxford Semiconductor OXPCIe952 1S1P",
845 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
846 .config_function = puc_config_oxford_pcie
849 { 0x1415, 0xc138, 0xffff, 0,
850 "Oxford Semiconductor OXPCIe952 UARTs",
852 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
853 .config_function = puc_config_oxford_pcie
856 { 0x1415, 0xc158, 0xffff, 0,
857 "Oxford Semiconductor OXPCIe952 UARTs",
859 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
860 .config_function = puc_config_oxford_pcie
863 { 0x1415, 0xc15d, 0xffff, 0,
864 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
866 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
867 .config_function = puc_config_oxford_pcie
870 { 0x1415, 0xc208, 0xffff, 0,
871 "Oxford Semiconductor OXPCIe954 UARTs",
873 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
874 .config_function = puc_config_oxford_pcie
877 { 0x1415, 0xc20d, 0xffff, 0,
878 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
880 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
881 .config_function = puc_config_oxford_pcie
884 { 0x1415, 0xc308, 0xffff, 0,
885 "Oxford Semiconductor OXPCIe958 UARTs",
887 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
888 .config_function = puc_config_oxford_pcie
891 { 0x1415, 0xc30d, 0xffff, 0,
892 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
894 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
895 .config_function = puc_config_oxford_pcie
898 { 0x14d2, 0x8010, 0xffff, 0,
901 PUC_PORT_1S, 0x14, 0, 0,
904 { 0x14d2, 0x8020, 0xffff, 0,
907 PUC_PORT_2S, 0x14, 4, 0,
910 { 0x14d2, 0x8028, 0xffff, 0,
913 PUC_PORT_2S, 0x20, 0, 8,
917 * VScom (Titan?) PCI-800L. More modern variant of the
918 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
919 * two of them obviously implemented as macro cells in
920 * the ASIC. This causes the weird port access pattern
921 * below, where two of the IO port ranges each access
922 * one of the ASIC UARTs, and a block of IO addresses
923 * access the external UARTs.
925 { 0x14d2, 0x8080, 0xffff, 0,
926 "Titan VScom PCI-800L",
928 PUC_PORT_8S, 0x14, -1, -1,
929 .config_function = puc_config_titan
933 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
934 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
935 * device ID 3 and PCI device 1 device ID 4.
937 { 0x14d2, 0xa003, 0xffff, 0,
940 PUC_PORT_4S, 0x10, 0, 8,
943 { 0x14d2, 0xa004, 0xffff, 0,
946 PUC_PORT_4S, 0x10, 0, 8,
949 { 0x14d2, 0xa005, 0xffff, 0,
952 PUC_PORT_2S, 0x10, 0, 8,
955 { 0x14d2, 0xe020, 0xffff, 0,
956 "Titan VScom PCI-200HV2",
958 PUC_PORT_2S, 0x10, 4, 0,
961 { 0x14d2, 0xa007, 0xffff, 0,
962 "Titan VScom PCIex-800H",
964 PUC_PORT_4S, 0x10, 0, 8,
967 { 0x14d2, 0xa008, 0xffff, 0,
968 "Titan VScom PCIex-800H",
970 PUC_PORT_4S, 0x10, 0, 8,
973 { 0x14db, 0x2130, 0xffff, 0,
974 "Avlab Technology, PCI IO 2S",
976 PUC_PORT_2S, 0x10, 4, 0,
979 { 0x14db, 0x2150, 0xffff, 0,
980 "Avlab Low Profile PCI 4 Serial",
982 PUC_PORT_4S, 0x10, 4, 0,
985 { 0x14db, 0x2152, 0xffff, 0,
986 "Avlab Low Profile PCI 4 Serial",
988 PUC_PORT_4S, 0x10, 4, 0,
991 { 0x1592, 0x0781, 0xffff, 0,
992 "Syba Tech Ltd. PCI-4S2P-550-ECP",
994 PUC_PORT_4S1P, 0x10, 0, -1,
995 .config_function = puc_config_syba
998 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
999 "Sunix SER5xxxx 2-port serial",
1001 PUC_PORT_2S, 0x10, 0, 8,
1004 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1005 "Sunix SER5xxxx 4-port serial",
1007 PUC_PORT_4S, 0x10, 0, 8,
1010 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1011 "Sunix SER5xxxx 8-port serial",
1013 PUC_PORT_8S, -1, -1, -1,
1014 .config_function = puc_config_sunix
1017 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1018 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1020 PUC_PORT_1S1P, -1, -1, -1,
1021 .config_function = puc_config_sunix
1024 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1025 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1027 PUC_PORT_2S1P, -1, -1, -1,
1028 .config_function = puc_config_sunix
1031 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1032 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1034 PUC_PORT_4S1P, -1, -1, -1,
1035 .config_function = puc_config_sunix
1038 { 0x5372, 0x6872, 0xffff, 0,
1039 "Feasso PCI FPP-02 2S1P",
1041 PUC_PORT_2S1P, 0x10, 4, 0,
1044 { 0x5372, 0x6873, 0xffff, 0,
1045 "Sun 1040 PCI Quad Serial",
1047 PUC_PORT_4S, 0x10, 4, 0,
1050 { 0x6666, 0x0001, 0xffff, 0,
1051 "Decision Computer Inc, PCCOM 4-port serial",
1053 PUC_PORT_4S, 0x1c, 0, 8,
1056 { 0x6666, 0x0002, 0xffff, 0,
1057 "Decision Computer Inc, PCCOM 8-port serial",
1059 PUC_PORT_8S, 0x1c, 0, 8,
1062 { 0x6666, 0x0004, 0xffff, 0,
1063 "PCCOM dual port RS232/422/485",
1065 PUC_PORT_2S, 0x1c, 0, 8,
1068 { 0x9710, 0x9815, 0xffff, 0,
1069 "NetMos NM9815 Dual 1284 Printer port",
1071 PUC_PORT_2P, 0x10, 8, 0,
1075 * This is more specific than the generic NM9835 entry, and is placed
1076 * here to _prevent_ puc(4) from claiming this single port card.
1078 * uart(4) will claim this device.
1080 { 0x9710, 0x9835, 0x1000, 1,
1081 "NetMos NM9835 based 1-port serial",
1083 PUC_PORT_1S, 0x10, 4, 0,
1086 { 0x9710, 0x9835, 0x1000, 2,
1087 "NetMos NM9835 based 2-port serial",
1089 PUC_PORT_2S, 0x10, 4, 0,
1092 { 0x9710, 0x9835, 0xffff, 0,
1093 "NetMos NM9835 Dual UART and 1284 Printer port",
1095 PUC_PORT_2S1P, 0x10, 4, 0,
1098 { 0x9710, 0x9845, 0x1000, 0x0006,
1099 "NetMos NM9845 6 Port UART",
1101 PUC_PORT_6S, 0x10, 4, 0,
1104 { 0x9710, 0x9845, 0xffff, 0,
1105 "NetMos NM9845 Quad UART and 1284 Printer port",
1107 PUC_PORT_4S1P, 0x10, 4, 0,
1110 { 0x9710, 0x9865, 0xa000, 0x3002,
1111 "NetMos NM9865 Dual UART",
1113 PUC_PORT_2S, 0x10, 4, 0,
1116 { 0x9710, 0x9865, 0xa000, 0x3003,
1117 "NetMos NM9865 Triple UART",
1119 PUC_PORT_3S, 0x10, 4, 0,
1122 { 0x9710, 0x9865, 0xa000, 0x3004,
1123 "NetMos NM9865 Quad UART",
1125 PUC_PORT_4S, 0x10, 4, 0,
1128 { 0x9710, 0x9865, 0xa000, 0x3011,
1129 "NetMos NM9865 Single UART and 1284 Printer port",
1131 PUC_PORT_1S1P, 0x10, 4, 0,
1134 { 0x9710, 0x9865, 0xa000, 0x3012,
1135 "NetMos NM9865 Dual UART and 1284 Printer port",
1137 PUC_PORT_2S1P, 0x10, 4, 0,
1140 { 0x9710, 0x9865, 0xa000, 0x3020,
1141 "NetMos NM9865 Dual 1284 Printer port",
1143 PUC_PORT_2P, 0x10, 4, 0,
1146 { 0xb00c, 0x021c, 0xffff, 0,
1147 "IC Book Labs Gunboat x4 Lite",
1149 PUC_PORT_4S, 0x10, 0, 8,
1150 .config_function = puc_config_icbook
1153 { 0xb00c, 0x031c, 0xffff, 0,
1154 "IC Book Labs Gunboat x4 Pro",
1156 PUC_PORT_4S, 0x10, 0, 8,
1157 .config_function = puc_config_icbook
1160 { 0xb00c, 0x041c, 0xffff, 0,
1161 "IC Book Labs Ironclad x8 Lite",
1163 PUC_PORT_8S, 0x10, 0, 8,
1164 .config_function = puc_config_icbook
1167 { 0xb00c, 0x051c, 0xffff, 0,
1168 "IC Book Labs Ironclad x8 Pro",
1170 PUC_PORT_8S, 0x10, 0, 8,
1171 .config_function = puc_config_icbook
1174 { 0xb00c, 0x081c, 0xffff, 0,
1175 "IC Book Labs Dreadnought x16 Pro",
1177 PUC_PORT_16S, 0x10, 0, 8,
1178 .config_function = puc_config_icbook
1181 { 0xb00c, 0x091c, 0xffff, 0,
1182 "IC Book Labs Dreadnought x16 Lite",
1184 PUC_PORT_16S, 0x10, 0, 8,
1185 .config_function = puc_config_icbook
1188 { 0xb00c, 0x0a1c, 0xffff, 0,
1189 "IC Book Labs Gunboat x2 Low Profile",
1191 PUC_PORT_2S, 0x10, 0, 8,
1194 { 0xb00c, 0x0b1c, 0xffff, 0,
1195 "IC Book Labs Gunboat x4 Low Profile",
1197 PUC_PORT_4S, 0x10, 0, 8,
1198 .config_function = puc_config_icbook
1201 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1205 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1209 case PUC_CFG_GET_OFS:
1210 *res = 8 * (port & 1);
1212 case PUC_CFG_GET_RID:
1213 *res = 0x14 + (port >> 1) * 4;
1222 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1225 const struct puc_cfg *cfg = sc->sc_cfg;
1227 if (cmd == PUC_CFG_GET_OFS) {
1228 if (cfg->subdevice == 0x1282) /* Everest SP */
1230 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1231 port = (port == 3) ? 4 : port;
1232 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1239 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1242 if (cmd == PUC_CFG_GET_OFS) {
1243 *res = port * 0x200;
1250 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1253 if (cmd == PUC_CFG_GET_OFS) {
1254 *res = port * 0x400;
1261 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1264 if (cmd == PUC_CFG_GET_ILR) {
1265 *res = PUC_ILR_DIGI;
1272 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1275 if (cmd == PUC_CFG_GET_OFS) {
1276 const struct puc_cfg *cfg = sc->sc_cfg;
1278 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
1280 *res = port * 0x200;
1288 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1291 const struct puc_cfg *cfg = sc->sc_cfg;
1292 struct puc_bar *bar;
1298 * Check if the scratchpad register is enabled or if the
1299 * interrupt status and options registers are active.
1301 bar = puc_get_bar(sc, cfg->rid);
1304 /* Set DLAB in the LCR register of UART 0. */
1305 bus_write_1(bar->b_res, 3, 0x80);
1306 /* Write 0 to the SPR register of UART 0. */
1307 bus_write_1(bar->b_res, 7, 0);
1308 /* Read back the contents of the SPR register of UART 0. */
1309 v0 = bus_read_1(bar->b_res, 7);
1310 /* Write a specific value to the SPR register of UART 0. */
1311 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1312 /* Read back the contents of the SPR register of UART 0. */
1313 v1 = bus_read_1(bar->b_res, 7);
1314 /* Clear DLAB in the LCR register of UART 0. */
1315 bus_write_1(bar->b_res, 3, 0);
1316 /* Save the two values read-back from the SPR register. */
1317 sc->sc_cfg_data = (v0 << 8) | v1;
1318 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1320 * The SPR register echoed the two values written
1321 * by us. This means that the SPAD jumper is set.
1323 device_printf(sc->sc_dev, "warning: extra features "
1324 "not usable -- SPAD compatibility enabled\n");
1329 * The first value doesn't match. This can only mean
1330 * that the SPAD jumper is not set and that a non-
1331 * standard fixed clock multiplier jumper is set.
1334 device_printf(sc->sc_dev, "fixed clock rate "
1335 "multiplier of %d\n", 1 << v0);
1336 if (v0 < -cfg->clock)
1337 device_printf(sc->sc_dev, "warning: "
1338 "suboptimal fixed clock rate multiplier "
1343 * The first value matched, but the second didn't. We know
1344 * that the SPAD jumper is not set. We also know that the
1345 * clock rate multiplier is software controlled *and* that
1346 * we just programmed it to the maximum allowed.
1349 device_printf(sc->sc_dev, "clock rate multiplier of "
1350 "%d selected\n", 1 << -cfg->clock);
1352 case PUC_CFG_GET_CLOCK:
1353 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1354 v1 = sc->sc_cfg_data & 0xff;
1355 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1357 * XXX With the SPAD jumper applied, there's no
1358 * easy way of knowing if there's also a clock
1359 * rate multiplier jumper installed. Let's hope
1362 *res = DEFAULT_RCLK;
1363 } else if (v0 == 0) {
1365 * No clock rate multiplier jumper installed,
1366 * so we programmed the board with the maximum
1367 * multiplier allowed as given to us in the
1368 * clock field of the config record (negated).
1370 *res = DEFAULT_RCLK << -cfg->clock;
1372 *res = DEFAULT_RCLK << v0;
1374 case PUC_CFG_GET_ILR:
1375 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1376 v1 = sc->sc_cfg_data & 0xff;
1377 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1378 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1387 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1390 static int base[] = { 0x251, 0x3f0, 0 };
1391 const struct puc_cfg *cfg = sc->sc_cfg;
1392 struct puc_bar *bar;
1398 bar = puc_get_bar(sc, cfg->rid);
1402 /* configure both W83877TFs */
1403 bus_write_1(bar->b_res, 0x250, 0x89);
1404 bus_write_1(bar->b_res, 0x3f0, 0x87);
1405 bus_write_1(bar->b_res, 0x3f0, 0x87);
1407 while (base[idx] != 0) {
1409 bus_write_1(bar->b_res, efir, 0x09);
1410 v = bus_read_1(bar->b_res, efir + 1);
1411 if ((v & 0x0f) != 0x0c)
1413 bus_write_1(bar->b_res, efir, 0x16);
1414 v = bus_read_1(bar->b_res, efir + 1);
1415 bus_write_1(bar->b_res, efir, 0x16);
1416 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1417 bus_write_1(bar->b_res, efir, 0x16);
1418 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1419 ofs = base[idx] & 0x300;
1420 bus_write_1(bar->b_res, efir, 0x23);
1421 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1422 bus_write_1(bar->b_res, efir, 0x24);
1423 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1424 bus_write_1(bar->b_res, efir, 0x25);
1425 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1426 bus_write_1(bar->b_res, efir, 0x17);
1427 bus_write_1(bar->b_res, efir + 1, 0x03);
1428 bus_write_1(bar->b_res, efir, 0x28);
1429 bus_write_1(bar->b_res, efir + 1, 0x43);
1432 bus_write_1(bar->b_res, 0x250, 0xaa);
1433 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1435 case PUC_CFG_GET_OFS:
1461 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1464 const struct puc_cfg *cfg = sc->sc_cfg;
1467 case PUC_CFG_GET_OFS:
1468 if (cfg->ports == PUC_PORT_8S) {
1469 *res = (port > 4) ? 8 * (port - 4) : 0;
1473 case PUC_CFG_GET_RID:
1474 if (cfg->ports == PUC_PORT_8S) {
1475 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1478 if (cfg->ports == PUC_PORT_2S1P) {
1480 case 0: *res = 0x10; return (0);
1481 case 1: *res = 0x14; return (0);
1482 case 2: *res = 0x1c; return (0);
1493 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1496 static const uint16_t dual[] = {
1497 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1498 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1499 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1500 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1503 static const uint16_t quad[] = {
1504 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1505 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1506 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1509 static const uint16_t octa[] = {
1510 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1511 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1513 static const struct {
1515 const uint16_t *ids;
1522 static char desc[64];
1527 case PUC_CFG_GET_CLOCK:
1529 *res = DEFAULT_RCLK * 8;
1531 *res = DEFAULT_RCLK;
1533 case PUC_CFG_GET_DESC:
1534 snprintf(desc, sizeof(desc),
1535 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1536 *res = (intptr_t)desc;
1538 case PUC_CFG_GET_NPORTS:
1539 subdev = pci_get_subdevice(sc->sc_dev);
1541 while (subdevs[dev].ports != 0) {
1543 while (subdevs[dev].ids[id] != 0) {
1544 if (subdev == subdevs[dev].ids[id]) {
1545 sc->sc_cfg_data = subdevs[dev].ports;
1546 *res = sc->sc_cfg_data;
1554 case PUC_CFG_GET_OFS:
1555 *res = (port == 1 || port == 3) ? 8 : 0;
1557 case PUC_CFG_GET_RID:
1558 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1560 case PUC_CFG_GET_TYPE:
1561 *res = PUC_TYPE_SERIAL;
1570 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1571 int port __unused, intptr_t *res)
1575 case PUC_CFG_GET_CLOCK:
1577 * OXu16PCI954 use a 14.7456 MHz clock by default while
1578 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1580 if (pci_get_revid(sc->sc_dev) == 1)
1581 *res = DEFAULT_RCLK * 8;
1583 *res = DEFAULT_RCLK;
1592 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1595 const struct puc_cfg *cfg = sc->sc_cfg;
1597 struct puc_bar *bar;
1602 device_printf(sc->sc_dev, "%d UARTs detected\n",
1605 /* Set UARTs to enhanced mode */
1606 bar = puc_get_bar(sc, cfg->rid);
1609 for (idx = 0; idx < sc->sc_nports; idx++) {
1610 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1612 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1616 case PUC_CFG_GET_LEN:
1619 case PUC_CFG_GET_NPORTS:
1621 * Check if we are being called from puc_bfe_attach()
1622 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1623 * puc_get_bar(), so we return a value of 16. This has cosmetic
1624 * side-effects at worst; in PUC_CFG_GET_DESC,
1625 * (int)sc->sc_cfg_data will not contain the true number of
1626 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1627 * call for this device family anyway.
1629 * The check is for initialisation of sc->sc_bar[idx], which is
1630 * only done in puc_bfe_attach().
1634 if (sc->sc_bar[idx++].b_rid != -1) {
1635 sc->sc_cfg_data = 16;
1636 *res = sc->sc_cfg_data;
1639 } while (idx < PUC_PCI_BARS);
1641 bar = puc_get_bar(sc, cfg->rid);
1645 value = bus_read_1(bar->b_res, 0x04);
1649 sc->sc_cfg_data = value;
1650 *res = sc->sc_cfg_data;
1652 case PUC_CFG_GET_OFS:
1653 *res = 0x1000 + (port << 9);
1655 case PUC_CFG_GET_TYPE:
1656 *res = PUC_TYPE_SERIAL;
1665 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1671 case PUC_CFG_GET_OFS:
1672 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1675 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1677 case PUC_CFG_GET_RID:
1678 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1681 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1690 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1694 case PUC_CFG_GET_OFS:
1695 *res = (port < 3) ? 0 : (port - 2) << 3;
1697 case PUC_CFG_GET_RID:
1698 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);