2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * PCI "universal" communications card driver configuration data (used to
34 * match/attach the cards).
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
47 #include <dev/ic/ns16550.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
52 #include <dev/puc/puc_bus.h>
53 #include <dev/puc/puc_cfg.h>
54 #include <dev/puc/puc_bfe.h>
56 static puc_config_f puc_config_advantech;
57 static puc_config_f puc_config_amc;
58 static puc_config_f puc_config_diva;
59 static puc_config_f puc_config_exar;
60 static puc_config_f puc_config_exar_pcie;
61 static puc_config_f puc_config_icbook;
62 static puc_config_f puc_config_moxa;
63 static puc_config_f puc_config_oxford_pci954;
64 static puc_config_f puc_config_oxford_pcie;
65 static puc_config_f puc_config_quatech;
66 static puc_config_f puc_config_syba;
67 static puc_config_f puc_config_siig;
68 static puc_config_f puc_config_sunix;
69 static puc_config_f puc_config_timedia;
70 static puc_config_f puc_config_titan;
72 const struct puc_cfg puc_pci_devices[] = {
73 { 0x0009, 0x7168, 0xffff, 0,
76 PUC_PORT_2S, 0x10, 0, 8,
79 { 0x103c, 0x1048, 0x103c, 0x1049,
80 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
82 PUC_PORT_3S, 0x10, 0, -1,
83 .config_function = puc_config_diva
86 { 0x103c, 0x1048, 0x103c, 0x104a,
87 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
89 PUC_PORT_2S, 0x10, 0, -1,
90 .config_function = puc_config_diva
93 { 0x103c, 0x1048, 0x103c, 0x104b,
94 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
96 PUC_PORT_4S, 0x10, 0, -1,
97 .config_function = puc_config_diva
100 { 0x103c, 0x1048, 0x103c, 0x1223,
101 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
103 PUC_PORT_3S, 0x10, 0, -1,
104 .config_function = puc_config_diva
107 { 0x103c, 0x1048, 0x103c, 0x1226,
108 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
110 PUC_PORT_3S, 0x10, 0, -1,
111 .config_function = puc_config_diva
114 { 0x103c, 0x1048, 0x103c, 0x1282,
115 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
117 PUC_PORT_3S, 0x10, 0, -1,
118 .config_function = puc_config_diva
121 { 0x10b5, 0x1076, 0x10b5, 0x1076,
124 PUC_PORT_8S, 0x18, 0, 8,
127 { 0x10b5, 0x1077, 0x10b5, 0x1077,
130 PUC_PORT_4S, 0x18, 0, 8,
133 { 0x10b5, 0x1103, 0x10b5, 0x1103,
136 PUC_PORT_2S, 0x18, 4, 0,
140 * Boca Research Turbo Serial 658 (8 serial port) card.
141 * Appears to be the same as Chase Research PLC PCI-FAST8
142 * and Perle PCI-FAST8 Multi-Port serial cards.
144 { 0x10b5, 0x9050, 0x12e0, 0x0021,
145 "Boca Research Turbo Serial 658",
147 PUC_PORT_8S, 0x18, 0, 8,
150 { 0x10b5, 0x9050, 0x12e0, 0x0031,
151 "Boca Research Turbo Serial 654",
153 PUC_PORT_4S, 0x18, 0, 8,
157 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
158 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
159 * into the subsystem fields, and claims that it's a
160 * network/misc (0x02/0x80) device.
162 { 0x10b5, 0x9050, 0xd84d, 0x6808,
163 "Dolphin Peripherals 4035",
165 PUC_PORT_2S, 0x18, 4, 0,
169 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
170 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
171 * into the subsystem fields, and claims that it's a
172 * network/misc (0x02/0x80) device.
174 { 0x10b5, 0x9050, 0xd84d, 0x6810,
175 "Dolphin Peripherals 4014",
177 PUC_PORT_2P, 0x20, 4, 0,
180 { 0x10e8, 0x818e, 0xffff, 0,
181 "Applied Micro Circuits 8 Port UART",
183 PUC_PORT_8S, 0x14, -1, -1,
184 .config_function = puc_config_amc
188 * The following members of the Digi International Neo series are
189 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
190 * Accordingly, the PCIe versions of these cards incorporate a PLX
194 { 0x114f, 0x00b0, 0xffff, 0,
195 "Digi Neo PCI 4 Port",
197 PUC_PORT_4S, 0x10, 0, -1,
198 .config_function = puc_config_exar
201 { 0x114f, 0x00b1, 0xffff, 0,
202 "Digi Neo PCI 8 Port",
204 PUC_PORT_8S, 0x10, 0, -1,
205 .config_function = puc_config_exar
208 { 0x114f, 0x00f0, 0xffff, 0,
209 "Digi Neo PCIe 8 Port",
211 PUC_PORT_8S, 0x10, 0, -1,
212 .config_function = puc_config_exar
215 { 0x114f, 0x00f1, 0xffff, 0,
216 "Digi Neo PCIe 4 Port",
218 PUC_PORT_4S, 0x10, 0, -1,
219 .config_function = puc_config_exar
222 { 0x114f, 0x00f2, 0xffff, 0,
223 "Digi Neo PCIe 4 Port RJ45",
225 PUC_PORT_4S, 0x10, 0, -1,
226 .config_function = puc_config_exar
229 { 0x114f, 0x00f3, 0xffff, 0,
230 "Digi Neo PCIe 8 Port RJ45",
232 PUC_PORT_8S, 0x10, 0, -1,
233 .config_function = puc_config_exar
236 { 0x11fe, 0x8010, 0xffff, 0,
237 "Comtrol RocketPort 550/8 RJ11 part A",
239 PUC_PORT_4S, 0x10, 0, 8,
242 { 0x11fe, 0x8011, 0xffff, 0,
243 "Comtrol RocketPort 550/8 RJ11 part B",
245 PUC_PORT_4S, 0x10, 0, 8,
248 { 0x11fe, 0x8012, 0xffff, 0,
249 "Comtrol RocketPort 550/8 Octa part A",
251 PUC_PORT_4S, 0x10, 0, 8,
254 { 0x11fe, 0x8013, 0xffff, 0,
255 "Comtrol RocketPort 550/8 Octa part B",
257 PUC_PORT_4S, 0x10, 0, 8,
260 { 0x11fe, 0x8014, 0xffff, 0,
261 "Comtrol RocketPort 550/4 RJ45",
263 PUC_PORT_4S, 0x10, 0, 8,
266 { 0x11fe, 0x8015, 0xffff, 0,
267 "Comtrol RocketPort 550/Quad",
269 PUC_PORT_4S, 0x10, 0, 8,
272 { 0x11fe, 0x8016, 0xffff, 0,
273 "Comtrol RocketPort 550/16 part A",
275 PUC_PORT_4S, 0x10, 0, 8,
278 { 0x11fe, 0x8017, 0xffff, 0,
279 "Comtrol RocketPort 550/16 part B",
281 PUC_PORT_12S, 0x10, 0, 8,
284 { 0x11fe, 0x8018, 0xffff, 0,
285 "Comtrol RocketPort 550/8 part A",
287 PUC_PORT_4S, 0x10, 0, 8,
290 { 0x11fe, 0x8019, 0xffff, 0,
291 "Comtrol RocketPort 550/8 part B",
293 PUC_PORT_4S, 0x10, 0, 8,
297 * IBM SurePOS 300 Series (481033H) serial ports
298 * Details can be found on the IBM RSS websites
301 { 0x1014, 0x0297, 0xffff, 0,
302 "IBM SurePOS 300 Series (481033H) serial ports",
304 PUC_PORT_4S, 0x10, 4, 0
310 * SIIG provides documentation for their boards at:
311 * <URL:http://www.siig.com/downloads.asp>
314 { 0x131f, 0x1010, 0xffff, 0,
315 "SIIG Cyber I/O PCI 16C550 (10x family)",
317 PUC_PORT_1S1P, 0x18, 4, 0,
320 { 0x131f, 0x1011, 0xffff, 0,
321 "SIIG Cyber I/O PCI 16C650 (10x family)",
323 PUC_PORT_1S1P, 0x18, 4, 0,
326 { 0x131f, 0x1012, 0xffff, 0,
327 "SIIG Cyber I/O PCI 16C850 (10x family)",
329 PUC_PORT_1S1P, 0x18, 4, 0,
332 { 0x131f, 0x1021, 0xffff, 0,
333 "SIIG Cyber Parallel Dual PCI (10x family)",
335 PUC_PORT_2P, 0x18, 8, 0,
338 { 0x131f, 0x1030, 0xffff, 0,
339 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
341 PUC_PORT_2S, 0x18, 4, 0,
344 { 0x131f, 0x1031, 0xffff, 0,
345 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
347 PUC_PORT_2S, 0x18, 4, 0,
350 { 0x131f, 0x1032, 0xffff, 0,
351 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
353 PUC_PORT_2S, 0x18, 4, 0,
356 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
357 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
359 PUC_PORT_2S1P, 0x18, 4, 0,
362 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
363 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
365 PUC_PORT_2S1P, 0x18, 4, 0,
368 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
369 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
371 PUC_PORT_2S1P, 0x18, 4, 0,
374 { 0x131f, 0x1050, 0xffff, 0,
375 "SIIG Cyber 4S PCI 16C550 (10x family)",
377 PUC_PORT_4S, 0x18, 4, 0,
380 { 0x131f, 0x1051, 0xffff, 0,
381 "SIIG Cyber 4S PCI 16C650 (10x family)",
383 PUC_PORT_4S, 0x18, 4, 0,
386 { 0x131f, 0x1052, 0xffff, 0,
387 "SIIG Cyber 4S PCI 16C850 (10x family)",
389 PUC_PORT_4S, 0x18, 4, 0,
392 { 0x131f, 0x2010, 0xffff, 0,
393 "SIIG Cyber I/O PCI 16C550 (20x family)",
395 PUC_PORT_1S1P, 0x10, 4, 0,
398 { 0x131f, 0x2011, 0xffff, 0,
399 "SIIG Cyber I/O PCI 16C650 (20x family)",
401 PUC_PORT_1S1P, 0x10, 4, 0,
404 { 0x131f, 0x2012, 0xffff, 0,
405 "SIIG Cyber I/O PCI 16C850 (20x family)",
407 PUC_PORT_1S1P, 0x10, 4, 0,
410 { 0x131f, 0x2021, 0xffff, 0,
411 "SIIG Cyber Parallel Dual PCI (20x family)",
413 PUC_PORT_2P, 0x10, 8, 0,
416 { 0x131f, 0x2030, 0xffff, 0,
417 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
419 PUC_PORT_2S, 0x10, 4, 0,
422 { 0x131f, 0x2031, 0xffff, 0,
423 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
425 PUC_PORT_2S, 0x10, 4, 0,
428 { 0x131f, 0x2032, 0xffff, 0,
429 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
431 PUC_PORT_2S, 0x10, 4, 0,
434 { 0x131f, 0x2040, 0xffff, 0,
435 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
437 PUC_PORT_1S2P, 0x10, -1, 0,
438 .config_function = puc_config_siig
441 { 0x131f, 0x2041, 0xffff, 0,
442 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
444 PUC_PORT_1S2P, 0x10, -1, 0,
445 .config_function = puc_config_siig
448 { 0x131f, 0x2042, 0xffff, 0,
449 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
451 PUC_PORT_1S2P, 0x10, -1, 0,
452 .config_function = puc_config_siig
455 { 0x131f, 0x2050, 0xffff, 0,
456 "SIIG Cyber 4S PCI 16C550 (20x family)",
458 PUC_PORT_4S, 0x10, 4, 0,
461 { 0x131f, 0x2051, 0xffff, 0,
462 "SIIG Cyber 4S PCI 16C650 (20x family)",
464 PUC_PORT_4S, 0x10, 4, 0,
467 { 0x131f, 0x2052, 0xffff, 0,
468 "SIIG Cyber 4S PCI 16C850 (20x family)",
470 PUC_PORT_4S, 0x10, 4, 0,
473 { 0x131f, 0x2060, 0xffff, 0,
474 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
476 PUC_PORT_2S1P, 0x10, 4, 0,
479 { 0x131f, 0x2061, 0xffff, 0,
480 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
482 PUC_PORT_2S1P, 0x10, 4, 0,
485 { 0x131f, 0x2062, 0xffff, 0,
486 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
488 PUC_PORT_2S1P, 0x10, 4, 0,
491 { 0x131f, 0x2081, 0xffff, 0,
492 "SIIG PS8000 8S PCI 16C650 (20x family)",
494 PUC_PORT_8S, 0x10, -1, -1,
495 .config_function = puc_config_siig
498 { 0x135c, 0x0010, 0xffff, 0,
500 -3, /* max 8x clock rate */
501 PUC_PORT_4S, 0x14, 0, 8,
502 .config_function = puc_config_quatech
505 { 0x135c, 0x0020, 0xffff, 0,
507 -1, /* max 2x clock rate */
508 PUC_PORT_2S, 0x14, 0, 8,
509 .config_function = puc_config_quatech
512 { 0x135c, 0x0030, 0xffff, 0,
513 "Quatech DSC-200/300",
514 -1, /* max 2x clock rate */
515 PUC_PORT_2S, 0x14, 0, 8,
516 .config_function = puc_config_quatech
519 { 0x135c, 0x0040, 0xffff, 0,
520 "Quatech QSC-200/300",
521 -3, /* max 8x clock rate */
522 PUC_PORT_4S, 0x14, 0, 8,
523 .config_function = puc_config_quatech
526 { 0x135c, 0x0050, 0xffff, 0,
528 -3, /* max 8x clock rate */
529 PUC_PORT_8S, 0x14, 0, 8,
530 .config_function = puc_config_quatech
533 { 0x135c, 0x0060, 0xffff, 0,
535 -3, /* max 8x clock rate */
536 PUC_PORT_8S, 0x14, 0, 8,
537 .config_function = puc_config_quatech
540 { 0x135c, 0x0170, 0xffff, 0,
542 -1, /* max 2x clock rate */
543 PUC_PORT_4S, 0x18, 0, 8,
544 .config_function = puc_config_quatech
547 { 0x135c, 0x0180, 0xffff, 0,
549 -1, /* max 3x clock rate */
550 PUC_PORT_2S, 0x18, 0, 8,
551 .config_function = puc_config_quatech
554 { 0x135c, 0x01b0, 0xffff, 0,
555 "Quatech DSCLP-200/300",
556 -1, /* max 2x clock rate */
557 PUC_PORT_2S, 0x18, 0, 8,
558 .config_function = puc_config_quatech
561 { 0x135c, 0x01e0, 0xffff, 0,
563 -3, /* max 8x clock rate */
564 PUC_PORT_8S, 0x10, 0, 8,
565 .config_function = puc_config_quatech
568 { 0x1393, 0x1024, 0xffff, 0,
569 "Moxa Technologies, Smartio CP-102E/PCIe",
571 PUC_PORT_2S, 0x14, 0, -1,
572 .config_function = puc_config_moxa
575 { 0x1393, 0x1025, 0xffff, 0,
576 "Moxa Technologies, Smartio CP-102EL/PCIe",
578 PUC_PORT_2S, 0x14, 0, -1,
579 .config_function = puc_config_moxa
582 { 0x1393, 0x1040, 0xffff, 0,
583 "Moxa Technologies, Smartio C104H/PCI",
585 PUC_PORT_4S, 0x18, 0, 8,
588 { 0x1393, 0x1041, 0xffff, 0,
589 "Moxa Technologies, Smartio CP-104UL/PCI",
591 PUC_PORT_4S, 0x18, 0, 8,
594 { 0x1393, 0x1042, 0xffff, 0,
595 "Moxa Technologies, Smartio CP-104JU/PCI",
597 PUC_PORT_4S, 0x18, 0, 8,
600 { 0x1393, 0x1043, 0xffff, 0,
601 "Moxa Technologies, Smartio CP-104EL/PCIe",
603 PUC_PORT_4S, 0x18, 0, 8,
606 { 0x1393, 0x1045, 0xffff, 0,
607 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
609 PUC_PORT_4S, 0x14, 0, -1,
610 .config_function = puc_config_moxa
613 { 0x1393, 0x1120, 0xffff, 0,
614 "Moxa Technologies, CP-112UL",
616 PUC_PORT_2S, 0x18, 0, 8,
619 { 0x1393, 0x1141, 0xffff, 0,
620 "Moxa Technologies, Industio CP-114",
622 PUC_PORT_4S, 0x18, 0, 8,
625 { 0x1393, 0x1144, 0xffff, 0,
626 "Moxa Technologies, Smartio CP-114EL/PCIe",
628 PUC_PORT_4S, 0x14, 0, -1,
629 .config_function = puc_config_moxa
632 { 0x1393, 0x1182, 0xffff, 0,
633 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
635 PUC_PORT_8S, 0x14, 0, -1,
636 .config_function = puc_config_moxa
639 { 0x1393, 0x1680, 0xffff, 0,
640 "Moxa Technologies, C168H/PCI",
642 PUC_PORT_8S, 0x18, 0, 8,
645 { 0x1393, 0x1681, 0xffff, 0,
646 "Moxa Technologies, C168U/PCI",
648 PUC_PORT_8S, 0x18, 0, 8,
651 { 0x1393, 0x1682, 0xffff, 0,
652 "Moxa Technologies, CP-168EL/PCIe",
654 PUC_PORT_8S, 0x18, 0, 8,
657 { 0x1393, 0x1683, 0xffff, 0,
658 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
660 PUC_PORT_8S, 0x14, 0, -1,
661 .config_function = puc_config_moxa
664 { 0x13a8, 0x0152, 0xffff, 0,
667 PUC_PORT_2S, 0x10, 0, -1,
668 .config_function = puc_config_exar
671 { 0x13a8, 0x0154, 0xffff, 0,
674 PUC_PORT_4S, 0x10, 0, -1,
675 .config_function = puc_config_exar
678 { 0x13a8, 0x0158, 0xffff, 0,
681 PUC_PORT_8S, 0x10, 0, -1,
682 .config_function = puc_config_exar
685 { 0x13a8, 0x0258, 0xffff, 0,
688 PUC_PORT_8S, 0x10, 0, -1,
689 .config_function = puc_config_exar
692 { 0x13a8, 0x0352, 0xffff, 0,
695 PUC_PORT_2S, 0x10, 0, -1,
696 .config_function = puc_config_exar_pcie
699 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
700 { 0x13a8, 0x0358, 0xffff, 0,
703 PUC_PORT_8S, 0x10, 0, -1,
704 .config_function = puc_config_exar_pcie
708 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
709 * Semiconductor OXuPCI954. Note these boards have a hardware bug in
710 * that they drive the RS-422/485 transmitters after power-on until a
711 * driver initalizes the UARTs.
713 { 0x13fe, 0x1600, 0x1602, 0x0002,
714 "Advantech PCI-1602 Rev. A",
716 PUC_PORT_2S, 0x10, 0, 8,
717 .config_function = puc_config_advantech
720 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
721 { 0x13fe, 0xa102, 0x13fe, 0xa102,
722 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
724 PUC_PORT_2S, 0x10, 4, 0,
725 .config_function = puc_config_advantech
728 { 0x1407, 0x0100, 0xffff, 0,
729 "Lava Computers Dual Serial",
731 PUC_PORT_2S, 0x10, 4, 0,
734 { 0x1407, 0x0101, 0xffff, 0,
735 "Lava Computers Quatro A",
737 PUC_PORT_2S, 0x10, 4, 0,
740 { 0x1407, 0x0102, 0xffff, 0,
741 "Lava Computers Quatro B",
743 PUC_PORT_2S, 0x10, 4, 0,
746 { 0x1407, 0x0120, 0xffff, 0,
747 "Lava Computers Quattro-PCI A",
749 PUC_PORT_2S, 0x10, 4, 0,
752 { 0x1407, 0x0121, 0xffff, 0,
753 "Lava Computers Quattro-PCI B",
755 PUC_PORT_2S, 0x10, 4, 0,
758 { 0x1407, 0x0180, 0xffff, 0,
759 "Lava Computers Octo A",
761 PUC_PORT_4S, 0x10, 4, 0,
764 { 0x1407, 0x0181, 0xffff, 0,
765 "Lava Computers Octo B",
767 PUC_PORT_4S, 0x10, 4, 0,
770 { 0x1409, 0x7268, 0xffff, 0,
773 PUC_PORT_2P, 0x10, 0, 8,
776 { 0x1409, 0x7168, 0xffff, 0,
779 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
780 .config_function = puc_config_timedia
784 * Boards with an Oxford Semiconductor chip.
786 * Oxford Semiconductor provides documentation for their chip at:
787 * <URL:http://www.plxtech.com/products/uart/>
789 * As sold by Kouwell <URL:http://www.kouwell.com/>.
790 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
793 0x1415, 0x9501, 0x10fc, 0xc070,
794 "I-O DATA RSA-PCI2/R",
796 PUC_PORT_2S, 0x10, 0, 8,
799 { 0x1415, 0x9501, 0x131f, 0x2050,
800 "SIIG Cyber 4 PCI 16550",
802 PUC_PORT_4S, 0x10, 0, 8,
805 { 0x1415, 0x9501, 0x131f, 0x2051,
806 "SIIG Cyber 4S PCI 16C650 (20x family)",
808 PUC_PORT_4S, 0x10, 0, 8,
811 { 0x1415, 0x9501, 0x131f, 0x2052,
812 "SIIG Quartet Serial 850",
814 PUC_PORT_4S, 0x10, 0, 8,
817 { 0x1415, 0x9501, 0x14db, 0x2150,
818 "Kuroutoshikou SERIAL4P-LPPCI2",
820 PUC_PORT_4S, 0x10, 0, 8,
823 { 0x1415, 0x9501, 0xffff, 0,
824 "Oxford Semiconductor OX16PCI954 UARTs",
826 PUC_PORT_4S, 0x10, 0, 8,
827 .config_function = puc_config_oxford_pci954
830 { 0x1415, 0x950a, 0x131f, 0x2030,
831 "SIIG Cyber 2S PCIe",
833 PUC_PORT_2S, 0x10, 0, 8,
836 { 0x1415, 0x950a, 0x131f, 0x2032,
837 "SIIG Cyber Serial Dual PCI 16C850",
839 PUC_PORT_4S, 0x10, 0, 8,
842 { 0x1415, 0x950a, 0x131f, 0x2061,
843 "SIIG Cyber 2SP1 PCIe",
845 PUC_PORT_2S, 0x10, 0, 8,
848 { 0x1415, 0x950a, 0xffff, 0,
849 "Oxford Semiconductor OX16PCI954 UARTs",
851 PUC_PORT_4S, 0x10, 0, 8,
854 { 0x1415, 0x9511, 0xffff, 0,
855 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
857 PUC_PORT_4S, 0x10, 0, 8,
860 { 0x1415, 0x9521, 0xffff, 0,
861 "Oxford Semiconductor OX16PCI952 UARTs",
863 PUC_PORT_2S, 0x10, 4, 0,
866 { 0x1415, 0x9538, 0xffff, 0,
867 "Oxford Semiconductor OX16PCI958 UARTs",
869 PUC_PORT_8S, 0x18, 0, 8,
873 * Perle boards use Oxford Semiconductor chips, but they store the
874 * Oxford Semiconductor device ID as a subvendor device ID and use
875 * their own device IDs.
878 { 0x155f, 0x0331, 0xffff, 0,
879 "Perle Ultraport4 Express",
881 PUC_PORT_4S, 0x10, 0, 8,
884 { 0x155f, 0xB012, 0xffff, 0,
887 PUC_PORT_2S, 0x10, 0, 8,
890 { 0x155f, 0xB022, 0xffff, 0,
893 PUC_PORT_2S, 0x10, 0, 8,
896 { 0x155f, 0xB004, 0xffff, 0,
899 PUC_PORT_4S, 0x10, 0, 8,
902 { 0x155f, 0xB008, 0xffff, 0,
905 PUC_PORT_8S, 0x10, 0, 8,
910 * Oxford Semiconductor PCI Express Expresso family
912 * Found in many 'native' PCI Express serial boards such as:
914 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
915 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
917 * Lindy 51189 (4 port)
918 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
920 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
921 * <URL:http://www.startech.com>
924 { 0x1415, 0xc11b, 0xffff, 0,
925 "Oxford Semiconductor OXPCIe952 1S1P",
927 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
928 .config_function = puc_config_oxford_pcie
931 { 0x1415, 0xc138, 0xffff, 0,
932 "Oxford Semiconductor OXPCIe952 UARTs",
934 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
935 .config_function = puc_config_oxford_pcie
938 { 0x1415, 0xc158, 0xffff, 0,
939 "Oxford Semiconductor OXPCIe952 UARTs",
941 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
942 .config_function = puc_config_oxford_pcie
945 { 0x1415, 0xc15d, 0xffff, 0,
946 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
948 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
949 .config_function = puc_config_oxford_pcie
952 { 0x1415, 0xc208, 0xffff, 0,
953 "Oxford Semiconductor OXPCIe954 UARTs",
955 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
956 .config_function = puc_config_oxford_pcie
959 { 0x1415, 0xc20d, 0xffff, 0,
960 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
962 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
963 .config_function = puc_config_oxford_pcie
966 { 0x1415, 0xc308, 0xffff, 0,
967 "Oxford Semiconductor OXPCIe958 UARTs",
969 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
970 .config_function = puc_config_oxford_pcie
973 { 0x1415, 0xc30d, 0xffff, 0,
974 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
976 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
977 .config_function = puc_config_oxford_pcie
980 { 0x14d2, 0x8010, 0xffff, 0,
983 PUC_PORT_1S, 0x14, 0, 0,
986 { 0x14d2, 0x8020, 0xffff, 0,
989 PUC_PORT_2S, 0x14, 4, 0,
992 { 0x14d2, 0x8028, 0xffff, 0,
995 PUC_PORT_2S, 0x20, 0, 8,
999 * VScom (Titan?) PCI-800L. More modern variant of the
1000 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1001 * two of them obviously implemented as macro cells in
1002 * the ASIC. This causes the weird port access pattern
1003 * below, where two of the IO port ranges each access
1004 * one of the ASIC UARTs, and a block of IO addresses
1005 * access the external UARTs.
1007 { 0x14d2, 0x8080, 0xffff, 0,
1008 "Titan VScom PCI-800L",
1010 PUC_PORT_8S, 0x14, -1, -1,
1011 .config_function = puc_config_titan
1015 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1016 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1017 * device ID 3 and PCI device 1 device ID 4.
1019 { 0x14d2, 0xa003, 0xffff, 0,
1022 PUC_PORT_4S, 0x10, 0, 8,
1025 { 0x14d2, 0xa004, 0xffff, 0,
1028 PUC_PORT_4S, 0x10, 0, 8,
1031 { 0x14d2, 0xa005, 0xffff, 0,
1034 PUC_PORT_2S, 0x10, 0, 8,
1037 { 0x14d2, 0xe020, 0xffff, 0,
1038 "Titan VScom PCI-200HV2",
1040 PUC_PORT_2S, 0x10, 4, 0,
1043 { 0x14d2, 0xa007, 0xffff, 0,
1044 "Titan VScom PCIex-800H",
1046 PUC_PORT_4S, 0x10, 0, 8,
1049 { 0x14d2, 0xa008, 0xffff, 0,
1050 "Titan VScom PCIex-800H",
1052 PUC_PORT_4S, 0x10, 0, 8,
1055 { 0x14db, 0x2130, 0xffff, 0,
1056 "Avlab Technology, PCI IO 2S",
1058 PUC_PORT_2S, 0x10, 4, 0,
1061 { 0x14db, 0x2150, 0xffff, 0,
1062 "Avlab Low Profile PCI 4 Serial",
1064 PUC_PORT_4S, 0x10, 4, 0,
1067 { 0x14db, 0x2152, 0xffff, 0,
1068 "Avlab Low Profile PCI 4 Serial",
1070 PUC_PORT_4S, 0x10, 4, 0,
1073 { 0x1592, 0x0781, 0xffff, 0,
1074 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1076 PUC_PORT_4S1P, 0x10, 0, -1,
1077 .config_function = puc_config_syba
1080 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1081 "Sunix SER5xxxx 2-port serial",
1083 PUC_PORT_2S, 0x10, 0, 8,
1086 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1087 "Sunix SER5xxxx 4-port serial",
1089 PUC_PORT_4S, 0x10, 0, 8,
1092 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1093 "Sunix SER5xxxx 8-port serial",
1095 PUC_PORT_8S, -1, -1, -1,
1096 .config_function = puc_config_sunix
1099 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1100 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1102 PUC_PORT_1S1P, -1, -1, -1,
1103 .config_function = puc_config_sunix
1106 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1107 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1109 PUC_PORT_2S1P, -1, -1, -1,
1110 .config_function = puc_config_sunix
1113 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1114 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1116 PUC_PORT_4S1P, -1, -1, -1,
1117 .config_function = puc_config_sunix
1120 { 0x5372, 0x6872, 0xffff, 0,
1121 "Feasso PCI FPP-02 2S1P",
1123 PUC_PORT_2S1P, 0x10, 4, 0,
1126 { 0x5372, 0x6873, 0xffff, 0,
1127 "Sun 1040 PCI Quad Serial",
1129 PUC_PORT_4S, 0x10, 4, 0,
1132 { 0x6666, 0x0001, 0xffff, 0,
1133 "Decision Computer Inc, PCCOM 4-port serial",
1135 PUC_PORT_4S, 0x1c, 0, 8,
1138 { 0x6666, 0x0002, 0xffff, 0,
1139 "Decision Computer Inc, PCCOM 8-port serial",
1141 PUC_PORT_8S, 0x1c, 0, 8,
1144 { 0x6666, 0x0004, 0xffff, 0,
1145 "PCCOM dual port RS232/422/485",
1147 PUC_PORT_2S, 0x1c, 0, 8,
1150 { 0x9710, 0x9815, 0xffff, 0,
1151 "NetMos NM9815 Dual 1284 Printer port",
1153 PUC_PORT_2P, 0x10, 8, 0,
1157 * This is more specific than the generic NM9835 entry, and is placed
1158 * here to _prevent_ puc(4) from claiming this single port card.
1160 * uart(4) will claim this device.
1162 { 0x9710, 0x9835, 0x1000, 1,
1163 "NetMos NM9835 based 1-port serial",
1165 PUC_PORT_1S, 0x10, 4, 0,
1168 { 0x9710, 0x9835, 0x1000, 2,
1169 "NetMos NM9835 based 2-port serial",
1171 PUC_PORT_2S, 0x10, 4, 0,
1174 { 0x9710, 0x9835, 0xffff, 0,
1175 "NetMos NM9835 Dual UART and 1284 Printer port",
1177 PUC_PORT_2S1P, 0x10, 4, 0,
1180 { 0x9710, 0x9845, 0x1000, 0x0006,
1181 "NetMos NM9845 6 Port UART",
1183 PUC_PORT_6S, 0x10, 4, 0,
1186 { 0x9710, 0x9845, 0xffff, 0,
1187 "NetMos NM9845 Quad UART and 1284 Printer port",
1189 PUC_PORT_4S1P, 0x10, 4, 0,
1192 { 0x9710, 0x9865, 0xa000, 0x3002,
1193 "NetMos NM9865 Dual UART",
1195 PUC_PORT_2S, 0x10, 4, 0,
1198 { 0x9710, 0x9865, 0xa000, 0x3003,
1199 "NetMos NM9865 Triple UART",
1201 PUC_PORT_3S, 0x10, 4, 0,
1204 { 0x9710, 0x9865, 0xa000, 0x3004,
1205 "NetMos NM9865 Quad UART",
1207 PUC_PORT_4S, 0x10, 4, 0,
1210 { 0x9710, 0x9865, 0xa000, 0x3011,
1211 "NetMos NM9865 Single UART and 1284 Printer port",
1213 PUC_PORT_1S1P, 0x10, 4, 0,
1216 { 0x9710, 0x9865, 0xa000, 0x3012,
1217 "NetMos NM9865 Dual UART and 1284 Printer port",
1219 PUC_PORT_2S1P, 0x10, 4, 0,
1222 { 0x9710, 0x9865, 0xa000, 0x3020,
1223 "NetMos NM9865 Dual 1284 Printer port",
1225 PUC_PORT_2P, 0x10, 4, 0,
1228 { 0xb00c, 0x021c, 0xffff, 0,
1229 "IC Book Labs Gunboat x4 Lite",
1231 PUC_PORT_4S, 0x10, 0, 8,
1232 .config_function = puc_config_icbook
1235 { 0xb00c, 0x031c, 0xffff, 0,
1236 "IC Book Labs Gunboat x4 Pro",
1238 PUC_PORT_4S, 0x10, 0, 8,
1239 .config_function = puc_config_icbook
1242 { 0xb00c, 0x041c, 0xffff, 0,
1243 "IC Book Labs Ironclad x8 Lite",
1245 PUC_PORT_8S, 0x10, 0, 8,
1246 .config_function = puc_config_icbook
1249 { 0xb00c, 0x051c, 0xffff, 0,
1250 "IC Book Labs Ironclad x8 Pro",
1252 PUC_PORT_8S, 0x10, 0, 8,
1253 .config_function = puc_config_icbook
1256 { 0xb00c, 0x081c, 0xffff, 0,
1257 "IC Book Labs Dreadnought x16 Pro",
1259 PUC_PORT_16S, 0x10, 0, 8,
1260 .config_function = puc_config_icbook
1263 { 0xb00c, 0x091c, 0xffff, 0,
1264 "IC Book Labs Dreadnought x16 Lite",
1266 PUC_PORT_16S, 0x10, 0, 8,
1267 .config_function = puc_config_icbook
1270 { 0xb00c, 0x0a1c, 0xffff, 0,
1271 "IC Book Labs Gunboat x2 Low Profile",
1273 PUC_PORT_2S, 0x10, 0, 8,
1276 { 0xb00c, 0x0b1c, 0xffff, 0,
1277 "IC Book Labs Gunboat x4 Low Profile",
1279 PUC_PORT_4S, 0x10, 0, 8,
1280 .config_function = puc_config_icbook
1283 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1287 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1288 intptr_t *res __unused)
1290 const struct puc_cfg *cfg;
1291 struct resource *cres;
1292 struct puc_bar *bar;
1295 int base, crtype, fixed, high, i, oxpcie;
1296 uint8_t acr, func, mask;
1298 if (cmd != PUC_CFG_SETUP)
1301 base = fixed = oxpcie = 0;
1302 crtype = SYS_RES_IOPORT;
1308 switch (cfg->subvendor) {
1310 switch (cfg->device) {
1324 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1325 pci_get_slot(dev), func);
1327 device_printf(dev, "could not find config function\n");
1332 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE);
1334 device_printf(dev, "could not allocate config resource\n");
1339 mask = bus_read_1(cres, off);
1340 if (pci_get_function(dev) == 1)
1345 for (i = 0; i < sc->sc_nports; ++i) {
1346 device_printf(dev, "port %d: ", i);
1347 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);
1349 printf("could not get BAR\n");
1354 if ((mask & (1 << (base + i))) == 0) {
1358 acr = (high == 1 ? 0x18 : 0x10);
1359 printf("RS-422/RS-485, active-%s auto-DTR\n",
1360 high == 1 ? "high" : "low");
1364 bus_write_1(bar->b_res, REG_SPR, REG_ACR);
1365 bus_write_1(bar->b_res, REG_ICR, acr);
1368 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres);
1373 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port,
1378 case PUC_CFG_GET_OFS:
1379 *res = 8 * (port & 1);
1381 case PUC_CFG_GET_RID:
1382 *res = 0x14 + (port >> 1) * 4;
1391 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1394 const struct puc_cfg *cfg = sc->sc_cfg;
1396 if (cmd == PUC_CFG_GET_OFS) {
1397 if (cfg->subdevice == 0x1282) /* Everest SP */
1399 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1400 port = (port == 3) ? 4 : port;
1401 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1408 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1409 int port, intptr_t *res)
1412 if (cmd == PUC_CFG_GET_OFS) {
1413 *res = port * 0x200;
1420 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1421 int port, intptr_t *res)
1424 if (cmd == PUC_CFG_GET_OFS) {
1425 *res = port * 0x400;
1432 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1433 int port __unused, intptr_t *res)
1436 if (cmd == PUC_CFG_GET_ILR) {
1437 *res = PUC_ILR_DIGI;
1444 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1447 const struct puc_cfg *cfg = sc->sc_cfg;
1449 if (cmd == PUC_CFG_GET_OFS) {
1450 if (port == 3 && (cfg->device == 0x1045 ||
1451 cfg->device == 0x1144))
1453 *res = port * 0x200;
1461 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1462 int port __unused, intptr_t *res)
1464 const struct puc_cfg *cfg = sc->sc_cfg;
1465 struct puc_bar *bar;
1471 * Check if the scratchpad register is enabled or if the
1472 * interrupt status and options registers are active.
1474 bar = puc_get_bar(sc, cfg->rid);
1477 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);
1478 bus_write_1(bar->b_res, REG_SPR, 0);
1479 v0 = bus_read_1(bar->b_res, REG_SPR);
1480 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);
1481 v1 = bus_read_1(bar->b_res, REG_SPR);
1482 bus_write_1(bar->b_res, REG_LCR, 0);
1483 sc->sc_cfg_data = (v0 << 8) | v1;
1484 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1486 * The SPR register echoed the two values written
1487 * by us. This means that the SPAD jumper is set.
1489 device_printf(sc->sc_dev, "warning: extra features "
1490 "not usable -- SPAD compatibility enabled\n");
1495 * The first value doesn't match. This can only mean
1496 * that the SPAD jumper is not set and that a non-
1497 * standard fixed clock multiplier jumper is set.
1500 device_printf(sc->sc_dev, "fixed clock rate "
1501 "multiplier of %d\n", 1 << v0);
1502 if (v0 < -cfg->clock)
1503 device_printf(sc->sc_dev, "warning: "
1504 "suboptimal fixed clock rate multiplier "
1509 * The first value matched, but the second didn't. We know
1510 * that the SPAD jumper is not set. We also know that the
1511 * clock rate multiplier is software controlled *and* that
1512 * we just programmed it to the maximum allowed.
1515 device_printf(sc->sc_dev, "clock rate multiplier of "
1516 "%d selected\n", 1 << -cfg->clock);
1518 case PUC_CFG_GET_CLOCK:
1519 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1520 v1 = sc->sc_cfg_data & 0xff;
1521 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1523 * XXX With the SPAD jumper applied, there's no
1524 * easy way of knowing if there's also a clock
1525 * rate multiplier jumper installed. Let's hope
1528 *res = DEFAULT_RCLK;
1529 } else if (v0 == 0) {
1531 * No clock rate multiplier jumper installed,
1532 * so we programmed the board with the maximum
1533 * multiplier allowed as given to us in the
1534 * clock field of the config record (negated).
1536 *res = DEFAULT_RCLK << -cfg->clock;
1538 *res = DEFAULT_RCLK << v0;
1540 case PUC_CFG_GET_ILR:
1541 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1542 v1 = sc->sc_cfg_data & 0xff;
1543 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ?
1544 PUC_ILR_NONE : PUC_ILR_QUATECH;
1553 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1556 static int base[] = { 0x251, 0x3f0, 0 };
1557 const struct puc_cfg *cfg = sc->sc_cfg;
1558 struct puc_bar *bar;
1564 bar = puc_get_bar(sc, cfg->rid);
1568 /* configure both W83877TFs */
1569 bus_write_1(bar->b_res, 0x250, 0x89);
1570 bus_write_1(bar->b_res, 0x3f0, 0x87);
1571 bus_write_1(bar->b_res, 0x3f0, 0x87);
1573 while (base[idx] != 0) {
1575 bus_write_1(bar->b_res, efir, 0x09);
1576 v = bus_read_1(bar->b_res, efir + 1);
1577 if ((v & 0x0f) != 0x0c)
1579 bus_write_1(bar->b_res, efir, 0x16);
1580 v = bus_read_1(bar->b_res, efir + 1);
1581 bus_write_1(bar->b_res, efir, 0x16);
1582 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1583 bus_write_1(bar->b_res, efir, 0x16);
1584 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1585 ofs = base[idx] & 0x300;
1586 bus_write_1(bar->b_res, efir, 0x23);
1587 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1588 bus_write_1(bar->b_res, efir, 0x24);
1589 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1590 bus_write_1(bar->b_res, efir, 0x25);
1591 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1592 bus_write_1(bar->b_res, efir, 0x17);
1593 bus_write_1(bar->b_res, efir + 1, 0x03);
1594 bus_write_1(bar->b_res, efir, 0x28);
1595 bus_write_1(bar->b_res, efir + 1, 0x43);
1598 bus_write_1(bar->b_res, 0x250, 0xaa);
1599 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1601 case PUC_CFG_GET_OFS:
1627 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1630 const struct puc_cfg *cfg = sc->sc_cfg;
1633 case PUC_CFG_GET_OFS:
1634 if (cfg->ports == PUC_PORT_8S) {
1635 *res = (port > 4) ? 8 * (port - 4) : 0;
1639 case PUC_CFG_GET_RID:
1640 if (cfg->ports == PUC_PORT_8S) {
1641 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1644 if (cfg->ports == PUC_PORT_2S1P) {
1646 case 0: *res = 0x10; return (0);
1647 case 1: *res = 0x14; return (0);
1648 case 2: *res = 0x1c; return (0);
1659 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1662 static const uint16_t dual[] = {
1663 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1664 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1665 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1666 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1669 static const uint16_t quad[] = {
1670 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1671 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1672 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1675 static const uint16_t octa[] = {
1676 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1677 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1679 static const struct {
1681 const uint16_t *ids;
1688 static char desc[64];
1693 case PUC_CFG_GET_CLOCK:
1695 *res = DEFAULT_RCLK * 8;
1697 *res = DEFAULT_RCLK;
1699 case PUC_CFG_GET_DESC:
1700 snprintf(desc, sizeof(desc),
1701 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1702 *res = (intptr_t)desc;
1704 case PUC_CFG_GET_NPORTS:
1705 subdev = pci_get_subdevice(sc->sc_dev);
1707 while (subdevs[dev].ports != 0) {
1709 while (subdevs[dev].ids[id] != 0) {
1710 if (subdev == subdevs[dev].ids[id]) {
1711 sc->sc_cfg_data = subdevs[dev].ports;
1712 *res = sc->sc_cfg_data;
1720 case PUC_CFG_GET_OFS:
1721 *res = (port == 1 || port == 3) ? 8 : 0;
1723 case PUC_CFG_GET_RID:
1724 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1726 case PUC_CFG_GET_TYPE:
1727 *res = PUC_TYPE_SERIAL;
1736 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1737 int port __unused, intptr_t *res)
1741 case PUC_CFG_GET_CLOCK:
1743 * OXu16PCI954 use a 14.7456 MHz clock by default while
1744 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1746 if (pci_get_revid(sc->sc_dev) == 1)
1747 *res = DEFAULT_RCLK * 8;
1749 *res = DEFAULT_RCLK;
1758 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1761 const struct puc_cfg *cfg = sc->sc_cfg;
1763 struct puc_bar *bar;
1768 device_printf(sc->sc_dev, "%d UARTs detected\n",
1771 /* Set UARTs to enhanced mode */
1772 bar = puc_get_bar(sc, cfg->rid);
1775 for (idx = 0; idx < sc->sc_nports; idx++) {
1776 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1778 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1782 case PUC_CFG_GET_LEN:
1785 case PUC_CFG_GET_NPORTS:
1787 * Check if we are being called from puc_bfe_attach()
1788 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1789 * puc_get_bar(), so we return a value of 16. This has
1790 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC,
1791 * sc->sc_cfg_data will not contain the true number of
1792 * ports in PUC_CFG_GET_DESC, but we are not implementing
1793 * that call for this device family anyway.
1795 * The check is for initialization of sc->sc_bar[idx],
1796 * which is only done in puc_bfe_attach().
1800 if (sc->sc_bar[idx++].b_rid != -1) {
1801 sc->sc_cfg_data = 16;
1802 *res = sc->sc_cfg_data;
1805 } while (idx < PUC_PCI_BARS);
1807 bar = puc_get_bar(sc, cfg->rid);
1811 value = bus_read_1(bar->b_res, 0x04);
1815 sc->sc_cfg_data = value;
1816 *res = sc->sc_cfg_data;
1818 case PUC_CFG_GET_OFS:
1819 *res = 0x1000 + (port << 9);
1821 case PUC_CFG_GET_TYPE:
1822 *res = PUC_TYPE_SERIAL;
1831 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1837 case PUC_CFG_GET_OFS:
1838 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1841 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1843 case PUC_CFG_GET_RID:
1844 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1847 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1856 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1857 int port, intptr_t *res)
1861 case PUC_CFG_GET_OFS:
1862 *res = (port < 3) ? 0 : (port - 2) << 3;
1864 case PUC_CFG_GET_RID:
1865 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);