2 * Copyright (c) 2006 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
46 #include <dev/puc/puc_bus.h>
47 #include <dev/puc/puc_cfg.h>
48 #include <dev/puc/puc_bfe.h>
50 static puc_config_f puc_config_amc;
51 static puc_config_f puc_config_cronyx;
52 static puc_config_f puc_config_diva;
53 static puc_config_f puc_config_icbook;
54 static puc_config_f puc_config_quatech;
55 static puc_config_f puc_config_syba;
56 static puc_config_f puc_config_siig;
57 static puc_config_f puc_config_timedia;
58 static puc_config_f puc_config_titan;
60 const struct puc_cfg puc_pci_devices[] = {
62 { 0x0009, 0x7168, 0xffff, 0,
65 PUC_PORT_2S, 0x10, 0, 8,
68 { 0x103c, 0x1048, 0x103c, 0x1049,
69 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
71 PUC_PORT_3S, 0x10, 0, -1,
72 .config_function = puc_config_diva
75 { 0x103c, 0x1048, 0x103c, 0x104a,
76 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
78 PUC_PORT_2S, 0x10, 0, -1,
79 .config_function = puc_config_diva
82 { 0x103c, 0x1048, 0x103c, 0x104b,
83 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
85 PUC_PORT_4S, 0x10, 0, -1,
86 .config_function = puc_config_diva
89 { 0x103c, 0x1048, 0x103c, 0x1223,
90 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
92 PUC_PORT_3S, 0x10, 0, -1,
93 .config_function = puc_config_diva
96 { 0x103c, 0x1048, 0x103c, 0x1226,
97 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
99 PUC_PORT_3S, 0x10, 0, -1,
100 .config_function = puc_config_diva
103 { 0x103c, 0x1048, 0x103c, 0x1282,
104 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
106 PUC_PORT_3S, 0x10, 0, -1,
107 .config_function = puc_config_diva
110 { 0x10b5, 0x1076, 0x10b5, 0x1076,
113 PUC_PORT_8S, 0x18, 0, 8,
116 { 0x10b5, 0x1077, 0x10b5, 0x1077,
119 PUC_PORT_4S, 0x18, 0, 8,
122 { 0x10b5, 0x1103, 0x10b5, 0x1103,
125 PUC_PORT_2S, 0x18, 4, 0,
129 * Boca Research Turbo Serial 658 (8 serial port) card.
130 * Appears to be the same as Chase Research PLC PCI-FAST8
131 * and Perle PCI-FAST8 Multi-Port serial cards.
133 { 0x10b5, 0x9050, 0x12e0, 0x0021,
134 "Boca Research Turbo Serial 658",
136 PUC_PORT_8S, 0x18, 0, 8,
139 { 0x10b5, 0x9050, 0x12e0, 0x0031,
140 "Boca Research Turbo Serial 654",
142 PUC_PORT_4S, 0x18, 0, 8,
146 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
147 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
148 * into the subsystem fields, and claims that it's a
149 * network/misc (0x02/0x80) device.
151 { 0x10b5, 0x9050, 0xd84d, 0x6808,
152 "Dolphin Peripherals 4035",
154 PUC_PORT_2S, 0x18, 4, 0,
158 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
159 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
160 * into the subsystem fields, and claims that it's a
161 * network/misc (0x02/0x80) device.
163 { 0x10b5, 0x9050, 0xd84d, 0x6810,
164 "Dolphin Peripherals 4014",
166 PUC_PORT_2P, 0x20, 4, 0,
169 { 0x10e8, 0x818e, 0xffff, 0,
170 "Applied Micro Circuits 8 Port UART",
172 PUC_PORT_8S, 0x14, -1, -1,
173 .config_function = puc_config_amc
176 { 0x11fe, 0x8010, 0xffff, 0,
177 "Comtrol RocketPort 550/8 RJ11 part A",
179 PUC_PORT_4S, 0x10, 0, 8,
182 { 0x11fe, 0x8011, 0xffff, 0,
183 "Comtrol RocketPort 550/8 RJ11 part B",
185 PUC_PORT_4S, 0x10, 0, 8,
188 { 0x11fe, 0x8012, 0xffff, 0,
189 "Comtrol RocketPort 550/8 Octa part A",
191 PUC_PORT_4S, 0x10, 0, 8,
194 { 0x11fe, 0x8013, 0xffff, 0,
195 "Comtrol RocketPort 550/8 Octa part B",
197 PUC_PORT_4S, 0x10, 0, 8,
200 { 0x11fe, 0x8014, 0xffff, 0,
201 "Comtrol RocketPort 550/4 RJ45",
203 PUC_PORT_4S, 0x10, 0, 8,
206 { 0x11fe, 0x8015, 0xffff, 0,
207 "Comtrol RocketPort 550/Quad",
209 PUC_PORT_4S, 0x10, 0, 8,
212 { 0x11fe, 0x8016, 0xffff, 0,
213 "Comtrol RocketPort 550/16 part A",
215 PUC_PORT_4S, 0x10, 0, 8,
218 { 0x11fe, 0x8017, 0xffff, 0,
219 "Comtrol RocketPort 550/16 part B",
221 PUC_PORT_12S, 0x10, 0, 8,
224 { 0x11fe, 0x8018, 0xffff, 0,
225 "Comtrol RocketPort 550/8 part A",
227 PUC_PORT_4S, 0x10, 0, 8,
230 { 0x11fe, 0x8019, 0xffff, 0,
231 "Comtrol RocketPort 550/8 part B",
233 PUC_PORT_4S, 0x10, 0, 8,
239 * SIIG provides documentation for their boards at:
240 * <URL:http://www.siig.com/downloads.asp>
243 { 0x131f, 0x1010, 0xffff, 0,
244 "SIIG Cyber I/O PCI 16C550 (10x family)",
246 PUC_PORT_1S1P, 0x18, 4, 0,
249 { 0x131f, 0x1011, 0xffff, 0,
250 "SIIG Cyber I/O PCI 16C650 (10x family)",
252 PUC_PORT_1S1P, 0x18, 4, 0,
255 { 0x131f, 0x1012, 0xffff, 0,
256 "SIIG Cyber I/O PCI 16C850 (10x family)",
258 PUC_PORT_1S1P, 0x18, 4, 0,
261 { 0x131f, 0x1021, 0xffff, 0,
262 "SIIG Cyber Parallel Dual PCI (10x family)",
264 PUC_PORT_2P, 0x18, 8, 0,
267 { 0x131f, 0x1030, 0xffff, 0,
268 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
270 PUC_PORT_2S, 0x18, 4, 0,
273 { 0x131f, 0x1031, 0xffff, 0,
274 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
276 PUC_PORT_2S, 0x18, 4, 0,
279 { 0x131f, 0x1032, 0xffff, 0,
280 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
282 PUC_PORT_2S, 0x18, 4, 0,
285 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
286 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
288 PUC_PORT_2S1P, 0x18, 4, 0,
291 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
292 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
294 PUC_PORT_2S1P, 0x18, 4, 0,
297 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
298 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
300 PUC_PORT_2S1P, 0x18, 4, 0,
303 { 0x131f, 0x1050, 0xffff, 0,
304 "SIIG Cyber 4S PCI 16C550 (10x family)",
306 PUC_PORT_4S, 0x18, 4, 0,
309 { 0x131f, 0x1051, 0xffff, 0,
310 "SIIG Cyber 4S PCI 16C650 (10x family)",
312 PUC_PORT_4S, 0x18, 4, 0,
315 { 0x131f, 0x1052, 0xffff, 0,
316 "SIIG Cyber 4S PCI 16C850 (10x family)",
318 PUC_PORT_4S, 0x18, 4, 0,
321 { 0x131f, 0x2010, 0xffff, 0,
322 "SIIG Cyber I/O PCI 16C550 (20x family)",
324 PUC_PORT_1S1P, 0x10, 4, 0,
327 { 0x131f, 0x2011, 0xffff, 0,
328 "SIIG Cyber I/O PCI 16C650 (20x family)",
330 PUC_PORT_1S1P, 0x10, 4, 0,
333 { 0x131f, 0x2012, 0xffff, 0,
334 "SIIG Cyber I/O PCI 16C850 (20x family)",
336 PUC_PORT_1S1P, 0x10, 4, 0,
339 { 0x131f, 0x2021, 0xffff, 0,
340 "SIIG Cyber Parallel Dual PCI (20x family)",
342 PUC_PORT_2P, 0x10, 8, 0,
345 { 0x131f, 0x2030, 0xffff, 0,
346 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
348 PUC_PORT_2S, 0x10, 4, 0,
351 { 0x131f, 0x2031, 0xffff, 0,
352 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
354 PUC_PORT_2S, 0x10, 4, 0,
357 { 0x131f, 0x2032, 0xffff, 0,
358 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
360 PUC_PORT_2S, 0x10, 4, 0,
363 { 0x131f, 0x2040, 0xffff, 0,
364 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
366 PUC_PORT_1S2P, 0x10, -1, 0,
367 .config_function = puc_config_siig
370 { 0x131f, 0x2041, 0xffff, 0,
371 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
373 PUC_PORT_1S2P, 0x10, -1, 0,
374 .config_function = puc_config_siig
377 { 0x131f, 0x2042, 0xffff, 0,
378 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
380 PUC_PORT_1S2P, 0x10, -1, 0,
381 .config_function = puc_config_siig
384 { 0x131f, 0x2050, 0xffff, 0,
385 "SIIG Cyber 4S PCI 16C550 (20x family)",
387 PUC_PORT_4S, 0x10, 4, 0,
390 { 0x131f, 0x2051, 0xffff, 0,
391 "SIIG Cyber 4S PCI 16C650 (20x family)",
393 PUC_PORT_4S, 0x10, 4, 0,
396 { 0x131f, 0x2052, 0xffff, 0,
397 "SIIG Cyber 4S PCI 16C850 (20x family)",
399 PUC_PORT_4S, 0x10, 4, 0,
402 { 0x131f, 0x2060, 0xffff, 0,
403 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
405 PUC_PORT_2S1P, 0x10, 4, 0,
408 { 0x131f, 0x2061, 0xffff, 0,
409 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
411 PUC_PORT_2S1P, 0x10, 4, 0,
414 { 0x131f, 0x2062, 0xffff, 0,
415 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
417 PUC_PORT_2S1P, 0x10, 4, 0,
420 { 0x131f, 0x2081, 0xffff, 0,
421 "SIIG PS8000 8S PCI 16C650 (20x family)",
423 PUC_PORT_8S, 0x10, -1, -1,
424 .config_function = puc_config_siig
427 { 0x135c, 0x0010, 0xffff, 0,
429 -3, /* max 8x clock rate */
430 PUC_PORT_4S, 0x14, 0, 8,
431 .config_function = puc_config_quatech
434 { 0x135c, 0x0020, 0xffff, 0,
436 -1, /* max 2x clock rate */
437 PUC_PORT_2S, 0x14, 0, 8,
438 .config_function = puc_config_quatech
441 { 0x135c, 0x0030, 0xffff, 0,
442 "Quatech DSC-200/300",
443 -1, /* max 2x clock rate */
444 PUC_PORT_2S, 0x14, 0, 8,
445 .config_function = puc_config_quatech
448 { 0x135c, 0x0040, 0xffff, 0,
449 "Quatech QSC-200/300",
450 -3, /* max 8x clock rate */
451 PUC_PORT_4S, 0x14, 0, 8,
452 .config_function = puc_config_quatech
455 { 0x135c, 0x0050, 0xffff, 0,
457 -3, /* max 8x clock rate */
458 PUC_PORT_8S, 0x14, 0, 8,
459 .config_function = puc_config_quatech
462 { 0x135c, 0x0060, 0xffff, 0,
464 -3, /* max 8x clock rate */
465 PUC_PORT_8S, 0x14, 0, 8,
466 .config_function = puc_config_quatech
469 { 0x135c, 0x0170, 0xffff, 0,
471 -1, /* max 2x clock rate */
472 PUC_PORT_4S, 0x18, 0, 8,
473 .config_function = puc_config_quatech
476 { 0x135c, 0x0180, 0xffff, 0,
478 -1, /* max 3x clock rate */
479 PUC_PORT_2S, 0x18, 0, 8,
480 .config_function = puc_config_quatech
483 { 0x135c, 0x01b0, 0xffff, 0,
484 "Quatech DSCLP-200/300",
485 -1, /* max 2x clock rate */
486 PUC_PORT_2S, 0x18, 0, 8,
487 .config_function = puc_config_quatech
490 { 0x135c, 0x01e0, 0xffff, 0,
492 -3, /* max 8x clock rate */
493 PUC_PORT_8S, 0x10, 0, 8,
494 .config_function = puc_config_quatech
497 { 0x1393, 0x1040, 0xffff, 0,
498 "Moxa Technologies, Smartio C104H/PCI",
500 PUC_PORT_4S, 0x18, 0, 8,
503 { 0x1393, 0x1041, 0xffff, 0,
504 "Moxa Technologies, Smartio CP-104UL/PCI",
506 PUC_PORT_4S, 0x18, 0, 8,
509 { 0x1393, 0x1141, 0xffff, 0,
510 "Moxa Technologies, Industio CP-114",
512 PUC_PORT_4S, 0x18, 0, 8,
515 { 0x1393, 0x1680, 0xffff, 0,
516 "Moxa Technologies, C168H/PCI",
518 PUC_PORT_8S, 0x18, 0, 8,
521 { 0x1393, 0x1681, 0xffff, 0,
522 "Moxa Technologies, C168U/PCI",
524 PUC_PORT_8S, 0x18, 0, 8,
527 { 0x13a8, 0x0158, 0xffff, 0,
530 PUC_PORT_8S, 0x10, 0, -1,
531 .config_function = puc_config_cronyx
534 { 0x1407, 0x0100, 0xffff, 0,
535 "Lava Computers Dual Serial",
537 PUC_PORT_2S, 0x10, 4, 0,
540 { 0x1407, 0x0101, 0xffff, 0,
541 "Lava Computers Quatro A",
543 PUC_PORT_2S, 0x10, 4, 0,
546 { 0x1407, 0x0102, 0xffff, 0,
547 "Lava Computers Quatro B",
549 PUC_PORT_2S, 0x10, 4, 0,
552 { 0x1407, 0x0120, 0xffff, 0,
553 "Lava Computers Quattro-PCI A",
555 PUC_PORT_2S, 0x10, 4, 0,
558 { 0x1407, 0x0121, 0xffff, 0,
559 "Lava Computers Quattro-PCI B",
561 PUC_PORT_2S, 0x10, 4, 0,
564 { 0x1407, 0x0180, 0xffff, 0,
565 "Lava Computers Octo A",
567 PUC_PORT_4S, 0x10, 4, 0,
570 { 0x1407, 0x0181, 0xffff, 0,
571 "Lava Computers Octo B",
573 PUC_PORT_4S, 0x10, 4, 0,
576 { 0x1409, 0x7168, 0xffff, 0,
579 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
580 .config_function = puc_config_timedia
584 * Boards with an Oxford Semiconductor chip.
586 * Oxford Semiconductor provides documentation for their chip at:
587 * <URL:http://www.oxsemi.com/products/uarts/index.html>
589 * As sold by Kouwell <URL:http://www.kouwell.com/>.
590 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
593 { 0x1415, 0x9501, 0x131f, 0x2051,
594 "SIIG Cyber 4S PCI 16C650 (20x family)",
596 PUC_PORT_4S, 0x10, 0, 8,
599 { 0x1415, 0x9501, 0xffff, 0,
600 "Oxford Semiconductor OX16PCI954 UARTs",
602 PUC_PORT_4S, 0x10, 0, 8,
605 { 0x1415, 0x950a, 0xffff, 0,
606 "Oxford Semiconductor OX16PCI954 UARTs",
608 PUC_PORT_4S, 0x10, 0, 8,
611 { 0x1415, 0x9511, 0xffff, 0,
612 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
614 PUC_PORT_4S, 0x10, 0, 8,
617 { 0x1415, 0x9521, 0xffff, 0,
618 "Oxford Semiconductor OX16PCI952 UARTs",
620 PUC_PORT_2S, 0x10, 4, 0,
623 { 0x14d2, 0x8020, 0xffff, 0,
626 PUC_PORT_2S, 0x14, 4, 0,
629 { 0x14d2, 0x8028, 0xffff, 0,
632 PUC_PORT_2S, 0x20, 0, 8,
636 * VScom (Titan?) PCI-800L. More modern variant of the
637 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
638 * two of them obviously implemented as macro cells in
639 * the ASIC. This causes the weird port access pattern
640 * below, where two of the IO port ranges each access
641 * one of the ASIC UARTs, and a block of IO addresses
642 * access the external UARTs.
644 { 0x14d2, 0x8080, 0xffff, 0,
645 "Titan VScom PCI-800L",
647 PUC_PORT_8S, 0x14, -1, -1,
648 .config_function = puc_config_titan
652 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
653 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
654 * device ID 3 and PCI device 1 device ID 4.
656 { 0x14d2, 0xa003, 0xffff, 0,
659 PUC_PORT_4S, 0x10, 0, 8,
661 { 0x14d2, 0xa004, 0xffff, 0,
664 PUC_PORT_4S, 0x10, 0, 8,
667 { 0x14d2, 0xa005, 0xffff, 0,
670 PUC_PORT_2S, 0x10, 0, 8,
673 { 0x14d2, 0xe020, 0xffff, 0,
674 "Titan VScom PCI-200HV2",
676 PUC_PORT_2S, 0x10, 4, 0,
679 { 0x14db, 0x2130, 0xffff, 0,
680 "Avlab Technology, PCI IO 2S",
682 PUC_PORT_2S, 0x10, 4, 0,
685 { 0x14db, 0x2150, 0xffff, 0,
686 "Avlab Low Profile PCI 4 Serial",
688 PUC_PORT_4S, 0x10, 4, 0,
691 { 0x1592, 0x0781, 0xffff, 0,
692 "Syba Tech Ltd. PCI-4S2P-550-ECP",
694 PUC_PORT_4S1P, 0x10, 0, -1,
695 .config_function = puc_config_syba
698 { 0x6666, 0x0001, 0xffff, 0,
699 "Decision Computer Inc, PCCOM 4-port serial",
701 PUC_PORT_4S, 0x1c, 0, 8,
704 { 0x6666, 0x0004, 0xffff, 0,
705 "PCCOM dual port RS232/422/485",
707 PUC_PORT_2S, 0x1c, 0, 8,
710 { 0x9710, 0x9815, 0xffff, 0,
711 "NetMos NM9815 Dual 1284 Printer port",
713 PUC_PORT_2P, 0x10, 8, 0,
716 { 0x9710, 0x9835, 0xffff, 0,
717 "NetMos NM9835 Dual UART and 1284 Printer port",
719 PUC_PORT_2S1P, 0x10, 4, 0,
722 { 0x9710, 0x9845, 0x1000, 0x0006,
723 "NetMos NM9845 6 Port UART",
725 PUC_PORT_6S, 0x10, 4, 0,
728 { 0x9710, 0x9845, 0xffff, 0,
729 "NetMos NM9845 Quad UART and 1284 Printer port",
731 PUC_PORT_4S1P, 0x10, 4, 0,
734 { 0xb00c, 0x021c, 0xffff, 0,
735 "IC Book Labs Gunboat x4 Lite",
737 PUC_PORT_4S, 0x10, 0, 8,
738 .config_function = puc_config_icbook
741 { 0xb00c, 0x031c, 0xffff, 0,
742 "IC Book Labs Gunboat x4 Pro",
744 PUC_PORT_4S, 0x10, 0, 8,
745 .config_function = puc_config_icbook
748 { 0xb00c, 0x041c, 0xffff, 0,
749 "IC Book Labs Ironclad x8 Lite",
751 PUC_PORT_8S, 0x10, 0, 8,
752 .config_function = puc_config_icbook
755 { 0xb00c, 0x051c, 0xffff, 0,
756 "IC Book Labs Ironclad x8 Pro",
758 PUC_PORT_8S, 0x10, 0, 8,
759 .config_function = puc_config_icbook
762 { 0xb00c, 0x081c, 0xffff, 0,
763 "IC Book Labs Dreadnought x16 Pro",
765 PUC_PORT_16S, 0x10, 0, 8,
766 .config_function = puc_config_icbook
769 { 0xb00c, 0x091c, 0xffff, 0,
770 "IC Book Labs Dreadnought x16 Lite",
772 PUC_PORT_16S, 0x10, 0, 8,
773 .config_function = puc_config_icbook
776 { 0xb00c, 0x0a1c, 0xffff, 0,
777 "IC Book Labs Gunboat x2 Low Profile",
779 PUC_PORT_2S, 0x10, 0, 8,
782 { 0xb00c, 0x0b1c, 0xffff, 0,
783 "IC Book Labs Gunboat x4 Low Profile",
785 PUC_PORT_4S, 0x10, 0, 8,
786 .config_function = puc_config_icbook
789 { 0xffff, 0, 0xffff, 0, NULL, 0 }
793 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
797 case PUC_CFG_GET_OFS:
798 *res = 8 * (port & 1);
800 case PUC_CFG_GET_RID:
801 *res = 0x14 + (port >> 1) * 4;
810 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
813 if (cmd == PUC_CFG_GET_OFS) {
821 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
824 const struct puc_cfg *cfg = sc->sc_cfg;
826 if (cmd == PUC_CFG_GET_OFS) {
827 if (cfg->subdevice == 0x1282) /* Everest SP */
829 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
830 port = (port == 3) ? 4 : port;
831 *res = port * 8 + ((port > 2) ? 0x18 : 0);
838 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
841 if (cmd == PUC_CFG_GET_ILR) {
849 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
852 const struct puc_cfg *cfg = sc->sc_cfg;
859 * Check if the scratchpad register is enabled or if the
860 * interrupt status and options registers are active.
862 bar = puc_get_bar(sc, cfg->rid);
865 /* Set DLAB in the LCR register of UART 0. */
866 bus_write_1(bar->b_res, 3, 0x80);
867 /* Write 0 to the SPR register of UART 0. */
868 bus_write_1(bar->b_res, 7, 0);
869 /* Read back the contents of the SPR register of UART 0. */
870 v0 = bus_read_1(bar->b_res, 7);
871 /* Write a specific value to the SPR register of UART 0. */
872 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
873 /* Read back the contents of the SPR register of UART 0. */
874 v1 = bus_read_1(bar->b_res, 7);
875 /* Clear DLAB in the LCR register of UART 0. */
876 bus_write_1(bar->b_res, 3, 0);
877 /* Save the two values read-back from the SPR register. */
878 sc->sc_cfg_data = (v0 << 8) | v1;
879 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
881 * The SPR register echoed the two values written
882 * by us. This means that the SPAD jumper is set.
884 device_printf(sc->sc_dev, "warning: extra features "
885 "not usable -- SPAD compatibility enabled\n");
890 * The first value doesn't match. This can only mean
891 * that the SPAD jumper is not set and that a non-
892 * standard fixed clock multiplier jumper is set.
895 device_printf(sc->sc_dev, "fixed clock rate "
896 "multiplier of %d\n", 1 << v0);
897 if (v0 < -cfg->clock)
898 device_printf(sc->sc_dev, "warning: "
899 "suboptimal fixed clock rate multiplier "
904 * The first value matched, but the second didn't. We know
905 * that the SPAD jumper is not set. We also know that the
906 * clock rate multiplier is software controlled *and* that
907 * we just programmed it to the maximum allowed.
910 device_printf(sc->sc_dev, "clock rate multiplier of "
911 "%d selected\n", 1 << -cfg->clock);
913 case PUC_CFG_GET_CLOCK:
914 v0 = (sc->sc_cfg_data >> 8) & 0xff;
915 v1 = sc->sc_cfg_data & 0xff;
916 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
918 * XXX With the SPAD jumper applied, there's no
919 * easy way of knowing if there's also a clock
920 * rate multiplier jumper installed. Let's hope
924 } else if (v0 == 0) {
926 * No clock rate multiplier jumper installed,
927 * so we programmed the board with the maximum
928 * multiplier allowed as given to us in the
929 * clock field of the config record (negated).
931 *res = DEFAULT_RCLK << -cfg->clock;
933 *res = DEFAULT_RCLK << v0;
935 case PUC_CFG_GET_ILR:
936 v0 = (sc->sc_cfg_data >> 8) & 0xff;
937 v1 = sc->sc_cfg_data & 0xff;
938 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
939 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
948 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
951 static int base[] = { 0x251, 0x3f0, 0 };
952 const struct puc_cfg *cfg = sc->sc_cfg;
959 bar = puc_get_bar(sc, cfg->rid);
963 /* configure both W83877TFs */
964 bus_write_1(bar->b_res, 0x250, 0x89);
965 bus_write_1(bar->b_res, 0x3f0, 0x87);
966 bus_write_1(bar->b_res, 0x3f0, 0x87);
968 while (base[idx] != 0) {
970 bus_write_1(bar->b_res, efir, 0x09);
971 v = bus_read_1(bar->b_res, efir + 1);
972 if ((v & 0x0f) != 0x0c)
974 bus_write_1(bar->b_res, efir, 0x16);
975 v = bus_read_1(bar->b_res, efir + 1);
976 bus_write_1(bar->b_res, efir, 0x16);
977 bus_write_1(bar->b_res, efir + 1, v | 0x04);
978 bus_write_1(bar->b_res, efir, 0x16);
979 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
980 ofs = base[idx] & 0x300;
981 bus_write_1(bar->b_res, efir, 0x23);
982 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
983 bus_write_1(bar->b_res, efir, 0x24);
984 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
985 bus_write_1(bar->b_res, efir, 0x25);
986 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
987 bus_write_1(bar->b_res, efir, 0x17);
988 bus_write_1(bar->b_res, efir + 1, 0x03);
989 bus_write_1(bar->b_res, efir, 0x28);
990 bus_write_1(bar->b_res, efir + 1, 0x43);
993 bus_write_1(bar->b_res, 0x250, 0xaa);
994 bus_write_1(bar->b_res, 0x3f0, 0xaa);
996 case PUC_CFG_GET_OFS:
1022 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1025 const struct puc_cfg *cfg = sc->sc_cfg;
1028 case PUC_CFG_GET_OFS:
1029 if (cfg->ports == PUC_PORT_8S) {
1030 *res = (port > 4) ? 8 * (port - 4) : 0;
1034 case PUC_CFG_GET_RID:
1035 if (cfg->ports == PUC_PORT_8S) {
1036 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1039 if (cfg->ports == PUC_PORT_2S1P) {
1041 case 0: *res = 0x10; return (0);
1042 case 1: *res = 0x14; return (0);
1043 case 2: *res = 0x1c; return (0);
1054 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1057 static uint16_t dual[] = {
1058 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1059 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1060 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1061 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1064 static uint16_t quad[] = {
1065 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1066 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1067 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1070 static uint16_t octa[] = {
1071 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1072 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1083 static char desc[64];
1088 case PUC_CFG_GET_DESC:
1089 snprintf(desc, sizeof(desc),
1090 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1091 *res = (intptr_t)desc;
1093 case PUC_CFG_GET_NPORTS:
1094 subdev = pci_get_subdevice(sc->sc_dev);
1096 while (subdevs[dev].ports != 0) {
1098 while (subdevs[dev].ids[id] != 0) {
1099 if (subdev == subdevs[dev].ids[id]) {
1100 sc->sc_cfg_data = subdevs[dev].ports;
1101 *res = sc->sc_cfg_data;
1109 case PUC_CFG_GET_OFS:
1110 *res = (port == 1 || port == 3) ? 8 : 0;
1112 case PUC_CFG_GET_RID:
1113 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1);
1115 case PUC_CFG_GET_TYPE:
1116 *res = PUC_TYPE_SERIAL;
1125 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1129 case PUC_CFG_GET_OFS:
1130 *res = (port < 3) ? 0 : (port - 2) << 3;
1132 case PUC_CFG_GET_RID:
1133 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);