2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/interrupt.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
47 #include <vm/vm_extern.h>
49 #include <machine/bus.h>
50 #include <machine/cpu.h>
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/fdt/fdt_pinctrl.h>
55 #include <dev/gpio/gpiobusvar.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <dev/extres/clk/clk.h>
60 #include <dev/extres/hwreset/hwreset.h>
62 #include <dev/spibus/spi.h>
63 #include <dev/spibus/spibusvar.h>
64 #include "spibus_if.h"
66 #include <dev/qcom_qup/qcom_spi_var.h>
67 #include <dev/qcom_qup/qcom_qup_reg.h>
68 #include <dev/qcom_qup/qcom_spi_reg.h>
69 #include <dev/qcom_qup/qcom_spi_debug.h>
71 static struct ofw_compat_data compat_data[] = {
72 { "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 },
73 { "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 },
74 { "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 },
79 * Flip the CS GPIO line either active or inactive.
81 * Actually listen to the CS polarity.
84 qcom_spi_set_chipsel(struct qcom_spi_softc *sc, int cs, bool active)
87 bool invert = !! (cs & SPIBUS_CS_HIGH);
89 cs = cs & ~SPIBUS_CS_HIGH;
91 if (sc->cs_pins[cs] == NULL) {
92 device_printf(sc->sc_dev,
93 "%s: cs=%u, active=%u, invert=%u, no gpio?\n",
94 __func__, cs, active, invert);
98 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_CHIPSELECT,
99 "%s: cs=%u active=%u\n", __func__, cs, active);
102 * Default rule here is CS is active low.
110 * Invert the CS line if required.
113 pinactive = !! pinactive;
115 gpio_pin_set_active(sc->cs_pins[cs], pinactive);
116 gpio_pin_is_active(sc->cs_pins[cs], &pinactive);
120 qcom_spi_intr(void *arg)
122 struct qcom_spi_softc *sc = arg;
125 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, "%s: called\n", __func__);
129 ret = qcom_spi_hw_interrupt_handle(sc);
131 device_printf(sc->sc_dev,
132 "ERROR: failed to read intr status\n");
137 * Handle spurious interrupts outside of an actual
140 if (sc->transfer.active == false) {
141 device_printf(sc->sc_dev,
142 "ERROR: spurious interrupt\n");
143 qcom_spi_hw_ack_opmode(sc);
147 /* Now, handle interrupts */
148 if (sc->intr.error) {
149 sc->intr.error = false;
150 device_printf(sc->sc_dev, "ERROR: intr\n");
153 if (sc->intr.do_rx) {
154 sc->intr.do_rx = false;
155 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
156 "%s: PIO_READ\n", __func__);
157 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
158 ret = qcom_spi_hw_read_pio_fifo(sc);
160 ret = qcom_spi_hw_read_pio_block(sc);
162 device_printf(sc->sc_dev,
163 "ERROR: qcom_spi_hw_read failed (%u)\n", ret);
167 if (sc->intr.do_tx) {
168 sc->intr.do_tx = false;
169 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
170 "%s: PIO_WRITE\n", __func__);
172 * For FIFO operations we do not do a write here, we did
173 * it at the beginning of the transfer.
175 * For BLOCK operations yes, we call the routine.
178 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
179 ret = qcom_spi_hw_ack_write_pio_fifo(sc);
181 ret = qcom_spi_hw_write_pio_block(sc);
183 device_printf(sc->sc_dev,
184 "ERROR: qcom_spi_hw_write failed (%u)\n", ret);
190 * Do this last. We may actually have completed the
191 * transfer in the PIO receive path above and it will
192 * set the done flag here.
195 sc->intr.done = false;
196 sc->transfer.done = true;
197 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
198 "%s: transfer done\n", __func__);
203 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
204 "%s: done\n", __func__);
209 qcom_spi_probe(device_t dev)
212 if (!ofw_bus_status_okay(dev))
215 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
218 device_set_desc(dev, "Qualcomm SPI Interface");
219 return (BUS_PROBE_DEFAULT);
223 * Allocate GPIOs if provided in the SPI controller block.
225 * Some devices will use GPIO lines for chip select.
226 * It's also quite annoying because some devices will want to use
227 * the hardware provided CS gating for say, the first chipselect block,
228 * and then use GPIOs for the later ones.
230 * So here we just assume for now that SPI index 0 uses the hardware
231 * lines, and >0 use GPIO lines. Revisit this if better hardware
234 * And finally, iterating over the cs-gpios list to allocate GPIOs
235 * doesn't actually tell us what the polarity is. For that we need
236 * to actually iterate over the list of child nodes and check what
237 * their properties are (and look for "spi-cs-high".)
240 qcom_spi_attach_gpios(struct qcom_spi_softc *sc)
245 /* Allocate gpio pins for configured chip selects. */
246 node = ofw_bus_get_node(sc->sc_dev);
247 for (idx = 0; idx < nitems(sc->cs_pins); idx++) {
248 err = gpio_pin_get_by_ofw_propidx(sc->sc_dev, node,
249 "cs-gpios", idx, &sc->cs_pins[idx]);
251 err = gpio_pin_setflags(sc->cs_pins[idx],
254 device_printf(sc->sc_dev,
255 "error configuring gpio for"
256 " cs %u (%d)\n", idx, err);
259 * We can't set this HIGH right now because
260 * we don't know if it needs to be set to
261 * high for inactive or low for inactive
262 * based on the child SPI device flags.
265 gpio_pin_set_active(sc->cs_pins[idx], 1);
266 gpio_pin_is_active(sc->cs_pins[idx], &tmp);
269 device_printf(sc->sc_dev,
270 "cannot configure gpio for chip select %u\n", idx);
271 sc->cs_pins[idx] = NULL;
277 qcom_spi_sysctl_attach(struct qcom_spi_softc *sc)
279 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
280 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
282 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
283 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
284 "control debugging printfs");
288 qcom_spi_attach(device_t dev)
290 struct qcom_spi_softc *sc = device_get_softc(dev);
291 int rid, ret, i, val;
296 * Hardware version is stored in the ofw_compat_data table.
299 ofw_bus_search_compatible(dev, compat_data)->ocd_data;
301 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
304 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
306 if (!sc->sc_mem_res) {
307 device_printf(dev, "ERROR: Could not map memory\n");
313 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
314 RF_ACTIVE | RF_SHAREABLE);
315 if (!sc->sc_irq_res) {
316 device_printf(dev, "ERROR: Could not map interrupt\n");
321 ret = bus_setup_intr(dev, sc->sc_irq_res,
322 INTR_TYPE_MISC | INTR_MPSAFE,
323 NULL, qcom_spi_intr, sc, &sc->sc_irq_h);
325 device_printf(dev, "ERROR: could not configure interrupt "
331 qcom_spi_attach_gpios(sc);
333 ret = clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core);
335 device_printf(dev, "ERROR: could not get %s clock (%d)\n",
339 ret = clk_get_by_ofw_name(dev, 0, "iface", &sc->clk_iface);
341 device_printf(dev, "ERROR: could not get %s clock (%d)\n",
346 /* Bring up initial clocks if they're off */
347 ret = clk_enable(sc->clk_core);
349 device_printf(dev, "ERROR: couldn't enable core clock (%u)\n",
353 ret = clk_enable(sc->clk_iface);
355 device_printf(dev, "ERROR: couldn't enable iface clock (%u)\n",
361 * Read optional spi-max-frequency
363 if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency",
364 &val, sizeof(val)) > 0)
365 sc->config.max_frequency = val;
367 sc->config.max_frequency = SPI_MAX_RATE;
370 * Read optional cs-select
372 if (OF_getencprop(ofw_bus_get_node(dev), "cs-select",
373 &val, sizeof(val)) > 0)
374 sc->config.cs_select = val;
376 sc->config.cs_select = 0;
379 * Read optional num-cs
381 if (OF_getencprop(ofw_bus_get_node(dev), "num-cs",
382 &val, sizeof(val)) > 0)
383 sc->config.num_cs = val;
385 sc->config.num_cs = SPI_NUM_CHIPSELECTS;
387 ret = fdt_pinctrl_configure_by_name(dev, "default");
390 "ERROR: could not configure default pinmux\n");
394 ret = qcom_spi_hw_read_controller_transfer_sizes(sc);
396 device_printf(dev, "ERROR: Could not read transfer config\n");
401 device_printf(dev, "BLOCK: input=%u bytes, output=%u bytes\n",
402 sc->config.input_block_size,
403 sc->config.output_block_size);
404 device_printf(dev, "FIFO: input=%u bytes, output=%u bytes\n",
405 sc->config.input_fifo_size,
406 sc->config.output_fifo_size);
410 ret = qcom_spi_hw_qup_init_locked(sc);
412 device_printf(dev, "ERROR: QUP init failed (%d)\n", ret);
417 /* Initial SPI config */
418 ret = qcom_spi_hw_spi_init_locked(sc);
420 device_printf(dev, "ERROR: SPI init failed (%d)\n", ret);
426 sc->spibus = device_add_child(dev, "spibus", -1);
428 /* We're done, so shut down the interface clock for now */
429 device_printf(dev, "DONE: shutting down interface clock for now\n");
430 clk_disable(sc->clk_iface);
432 /* Register for debug sysctl */
433 qcom_spi_sysctl_attach(sc);
435 return (bus_generic_attach(dev));
438 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
440 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
442 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
444 clk_disable(sc->clk_core);
445 clk_release(sc->clk_core);
448 clk_disable(sc->clk_iface);
449 clk_release(sc->clk_iface);
451 for (i = 0; i < CS_MAX; i++) {
452 if (sc->cs_pins[i] != NULL)
453 gpio_pin_release(sc->cs_pins[i]);
455 mtx_destroy(&sc->sc_mtx);
462 * Note that right now the TX/RX lens need to match, I'm not doing
463 * dummy reads / dummy writes as required if they're not the same
464 * size. The QUP hardware supports doing multi-phase transactions
465 * where the FIFO isn't engaged for transmit or receive, but it's
466 * not yet being done here.
469 qcom_spi_transfer_pio_block(struct qcom_spi_softc *sc, int mode,
470 char *tx_buf, int tx_len, char *rx_buf, int rx_len)
474 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, "%s: start\n",
477 if (rx_len != tx_len) {
478 device_printf(sc->sc_dev,
479 "ERROR: tx/rx len doesn't match (%d/%d)\n",
484 QCOM_SPI_ASSERT_LOCKED(sc);
487 * Make initial choices for transfer configuration.
489 ret = qcom_spi_hw_setup_transfer_selection(sc, tx_len);
491 device_printf(sc->sc_dev,
492 "ERROR: failed to setup transfer selection (%d)\n",
497 /* Now set suitable buffer/lengths */
498 sc->transfer.tx_buf = tx_buf;
499 sc->transfer.tx_len = tx_len;
500 sc->transfer.rx_buf = rx_buf;
501 sc->transfer.rx_len = rx_len;
502 sc->transfer.done = false;
503 sc->transfer.active = false;
506 * Loop until the full transfer set is done.
508 * qcom_spi_hw_setup_current_transfer() will take care of
509 * setting a maximum transfer size for the hardware and choose
510 * a suitable operating mode.
512 while (sc->transfer.tx_offset < sc->transfer.tx_len) {
514 * Set transfer to false early; this covers
515 * it also finishing a sub-transfer and we're
516 * about the put the block into RESET state before
517 * starting a new transfer.
519 sc->transfer.active = false;
521 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
522 "%s: tx=%d of %d bytes, rx=%d of %d bytes\n",
524 sc->transfer.tx_offset, sc->transfer.tx_len,
525 sc->transfer.rx_offset, sc->transfer.rx_len);
528 * Set state to RESET before doing anything.
530 * Otherwise the second sub-transfer that we queue up
531 * will generate interrupts immediately when we start
532 * configuring it here and it'll start underflowing.
534 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
536 device_printf(sc->sc_dev,
537 "ERROR: can't transition to RESET (%u)\n", ret);
540 /* blank interrupt state; we'll do a RESET below */
541 bzero(&sc->intr, sizeof(sc->intr));
542 sc->transfer.done = false;
545 * Configure what the transfer configuration for this
546 * sub-transfer will be.
548 ret = qcom_spi_hw_setup_current_transfer(sc);
550 device_printf(sc->sc_dev,
551 "ERROR: failed to setup sub transfer (%d)\n",
557 * For now since we're configuring up PIO, we only setup
558 * the PIO transfer size.
560 ret = qcom_spi_hw_setup_pio_transfer_cnt(sc);
562 device_printf(sc->sc_dev,
563 "ERROR: qcom_spi_hw_setup_pio_transfer_cnt failed"
570 * This is what we'd do to setup the block transfer sizes.
572 ret = qcom_spi_hw_setup_block_transfer_cnt(sc);
574 device_printf(sc->sc_dev,
575 "ERROR: qcom_spi_hw_setup_block_transfer_cnt failed"
581 ret = qcom_spi_hw_setup_io_modes(sc);
583 device_printf(sc->sc_dev,
584 "ERROR: qcom_spi_hw_setup_io_modes failed"
589 ret = qcom_spi_hw_setup_spi_io_clock_polarity(sc,
590 !! (mode & SPIBUS_MODE_CPOL));
592 device_printf(sc->sc_dev,
593 "ERROR: qcom_spi_hw_setup_spi_io_clock_polarity"
594 " failed (%u)\n", ret);
598 ret = qcom_spi_hw_setup_spi_config(sc, sc->state.frequency,
599 !! (mode & SPIBUS_MODE_CPHA));
601 device_printf(sc->sc_dev,
602 "ERROR: qcom_spi_hw_setup_spi_config failed"
607 ret = qcom_spi_hw_setup_qup_config(sc, !! (tx_len > 0),
610 device_printf(sc->sc_dev,
611 "ERROR: qcom_spi_hw_setup_qup_config failed"
616 ret = qcom_spi_hw_setup_operational_mask(sc);
618 device_printf(sc->sc_dev,
619 "ERROR: qcom_spi_hw_setup_operational_mask failed"
625 * Setup is done; reset the controller and start the PIO
630 * Set state to RUN; we may start getting interrupts that
631 * are valid and we need to handle.
633 sc->transfer.active = true;
634 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN);
636 device_printf(sc->sc_dev,
637 "ERROR: can't transition to RUN (%u)\n", ret);
644 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_PAUSE);
646 device_printf(sc->sc_dev,
647 "ERROR: can't transition to PAUSE (%u)\n", ret);
652 * If FIFO mode, write data now. Else, we'll get an
653 * interrupt when it's time to populate more data
656 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
657 ret = qcom_spi_hw_write_pio_fifo(sc);
659 ret = qcom_spi_hw_write_pio_block(sc);
661 device_printf(sc->sc_dev,
662 "ERROR: qcom_spi_hw_write failed (%u)\n", ret);
669 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN);
671 device_printf(sc->sc_dev,
672 "ERROR: can't transition to RUN (%u)\n", ret);
677 * Wait for an interrupt notification (which will
678 * continue to drive the state machine for this
679 * sub-transfer) or timeout.
682 while (ret == 0 && sc->transfer.done == false) {
683 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
684 "%s: waiting\n", __func__);
685 ret = msleep(sc, &sc->sc_mtx, 0, "qcom_spi", 0);
690 * Complete; put controller into reset.
692 * Don't worry about return value here; if we errored out above then
693 * we want to communicate that value to the caller.
695 (void) qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
696 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
697 "%s: completed\n", __func__);
700 * Blank the transfer state so we don't use an old transfer
701 * state in a subsequent interrupt.
703 (void) qcom_spi_hw_complete_transfer(sc);
704 sc->transfer.active = false;
710 qcom_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
712 struct qcom_spi_softc *sc = device_get_softc(dev);
713 uint32_t cs_val, mode_val, clock_val;
716 spibus_get_cs(child, &cs_val);
717 spibus_get_clock(child, &clock_val);
718 spibus_get_mode(child, &mode_val);
720 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
721 "%s: called; child cs=0x%08x, clock=%u, mode=0x%08x, "
722 "cmd=%u/%u bytes; data=%u/%u bytes\n",
727 cmd->tx_cmd_sz, cmd->rx_cmd_sz,
728 cmd->tx_data_sz, cmd->rx_data_sz);
733 * wait until the controller isn't busy
735 while (sc->sc_busy == true)
736 mtx_sleep(sc, &sc->sc_mtx, 0, "qcom_spi_wait", 0);
743 sc->state.cs_high = !! (cs_val & SPIBUS_CS_HIGH);
744 sc->state.frequency = clock_val;
747 * We can't set the clock frequency and enable it
748 * with the driver lock held, as the SPI lock is non-sleepable
749 * and the clock framework is sleepable.
751 * No other transaction is going on right now, so we can
752 * unlock here and do the clock related work.
757 * Set the clock frequency
759 ret = clk_set_freq(sc->clk_iface, sc->state.frequency, 0);
761 device_printf(sc->sc_dev,
762 "ERROR: failed to set frequency to %u\n",
763 sc->state.frequency);
766 clk_enable(sc->clk_iface);
773 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
775 device_printf(sc->sc_dev,
776 "ERROR: can't transition to RESET (%u)\n", ret);
780 /* Assert hardware CS if set, else GPIO */
781 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
782 qcom_spi_hw_spi_cs_force(sc, cs_val & SPIBUS_CS_HIGH, true);
784 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, true);
787 * cmd buffer transfer
789 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_cmd,
790 cmd->tx_cmd_sz, cmd->rx_cmd, cmd->rx_cmd_sz);
792 device_printf(sc->sc_dev,
793 "ERROR: failed to transfer cmd payload (%u)\n", ret);
798 * data buffer transfer
800 if (cmd->tx_data_sz > 0) {
801 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_data,
802 cmd->tx_data_sz, cmd->rx_data, cmd->rx_data_sz);
804 device_printf(sc->sc_dev,
805 "ERROR: failed to transfer data payload (%u)\n",
812 /* De-assert GPIO/CS */
813 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
814 qcom_spi_hw_spi_cs_force(sc, cs_val & ~SPIBUS_CS_HIGH, false);
816 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, false);
819 * Similarly to when we enabled the clock, we can't hold it here
820 * across a clk API as that's a sleep lock and we're non-sleepable.
821 * So instead we unlock/relock here, but we still hold the busy flag.
825 clk_disable(sc->clk_iface);
829 * We're done; so mark the bus as not busy and wakeup
839 qcom_spi_detach(device_t dev)
841 struct qcom_spi_softc *sc = device_get_softc(dev);
844 bus_generic_detach(sc->sc_dev);
845 if (sc->spibus != NULL)
846 device_delete_child(dev, sc->spibus);
849 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
852 clk_disable(sc->clk_iface);
853 clk_release(sc->clk_iface);
856 clk_disable(sc->clk_core);
857 clk_release(sc->clk_core);
860 for (i = 0; i < CS_MAX; i++) {
861 if (sc->cs_pins[i] != NULL)
862 gpio_pin_release(sc->cs_pins[i]);
866 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
868 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
870 mtx_destroy(&sc->sc_mtx);
876 qcom_spi_get_node(device_t bus, device_t dev)
879 return ofw_bus_get_node(bus);
883 static device_method_t qcom_spi_methods[] = {
884 /* Device interface */
885 DEVMETHOD(device_probe, qcom_spi_probe),
886 DEVMETHOD(device_attach, qcom_spi_attach),
887 DEVMETHOD(device_detach, qcom_spi_detach),
891 DEVMETHOD(spibus_transfer, qcom_spi_transfer),
894 DEVMETHOD(ofw_bus_get_node, qcom_spi_get_node),
899 static driver_t qcom_spi_driver = {
902 sizeof(struct qcom_spi_softc),
905 static devclass_t qcom_spi_devclass;
907 DRIVER_MODULE(qcom_spi, simplebus, qcom_spi_driver, qcom_spi_devclass, 0, 0);
908 DRIVER_MODULE(ofw_spibus, qcom_spi, ofw_spibus_driver, ofw_spibus_devclass,
910 MODULE_DEPEND(qcom_spi, ofw_spibus, 1, 1, 1);
911 SIMPLEBUS_PNP_INFO(compat_data);