sys/dev/qcom_tcsr/qcom_tcsr.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice unmodified, this list of conditions, and the following
  11  *    disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34
  35 #include <sys/bus.h>
  36 #include <sys/interrupt.h>
  37 #include <sys/malloc.h>
  38 #include <sys/lock.h>
  39 #include <sys/mutex.h>
  40 #include <sys/kernel.h>
  41 #include <sys/module.h>
  42 #include <sys/rman.h>
  43 #include <sys/gpio.h>
  44
  45 #include <vm/vm.h>
  46 #include <vm/pmap.h>
  47 #include <vm/vm_extern.h>
  48
  49 #include <machine/bus.h>
  50 #include <machine/cpu.h>
  51
  52 #include <dev/fdt/fdt_common.h>
  53 #include <dev/fdt/fdt_pinctrl.h>
  54
  55 #include <dev/gpio/gpiobusvar.h>
  56 #include <dev/ofw/ofw_bus.h>
  57 #include <dev/ofw/ofw_bus_subr.h>
  58
  59 #include <dev/qcom_tcsr/qcom_tcsr_var.h>
  60 #include <dev/qcom_tcsr/qcom_tcsr_reg.h>
  61
  62 /*
  63  * The linux-msm branches that support IPQ4018 use "ipq,tcsr".
  64  * The openwrt addons use qcom,tcsr.  So for now support both.
  65  *
  66  * Also, it's not quite clear yet (since this is the first port!)
  67  * whether these options and registers are specific to the QCA IPQ401x
  68  * part or show up in different linux branches as different registers
  69  * but with the same driver/naming here.  Let's hope that doesn't
  70  * happen.
  71  */
  72 static struct ofw_compat_data compat_data[] = {
  73         { "qcom,tcsr",                  1 },
  74         { "ipq,tcsr",                   1 },
  75         { NULL,                         0 }
  76 };
  77
  78 static int
  79 qcom_tcsr_probe(device_t dev)
  80 {
  81
  82         if (!ofw_bus_status_okay(dev))
  83                 return (ENXIO);
  84
  85         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
  86                 return (ENXIO);
  87
  88         device_set_desc(dev, "Qualcomm Core Top Control and Status Driver");
  89         return (BUS_PROBE_DEFAULT);
  90 }
  91
  92 static int
  93 qcom_tcsr_attach(device_t dev)
  94 {
  95         struct qcom_tcsr_softc *sc = device_get_softc(dev);
  96         int rid, ret;
  97         uint32_t val;
  98
  99         sc->sc_dev = dev;
 100
 101         /*
 102          * Hardware version is stored in the ofw_compat_data table.
 103          */
 104         sc->hw_version =
 105             ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 106
 107         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 108
 109         rid = 0;
 110         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 111             RF_ACTIVE);
 112         if (!sc->sc_mem_res) {
 113                 device_printf(dev, "ERROR: Could not map memory\n");
 114                 ret = ENXIO;
 115                 goto error;
 116         }
 117
 118         /*
 119          * Parse out the open firmware entries to see which particular
 120          * configurations we need to set here.
 121          */
 122
 123         /*
 124          * USB control select.
 125          *
 126          * For linux-msm on the IPQ401x, it actually calls into the SCM
 127          * to make the change.  OpenWRT just does a register write.
 128          * We'll do the register write for now.
 129          */
 130         if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-ctrl-select",
 131             &val, sizeof(val)) > 0) {
 132                 if (bootverbose)
 133                         device_printf(sc->sc_dev,
 134                             "USB control select (val 0x%x)\n",
 135                             val);
 136                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_PORT_SEL, val);
 137         }
 138
 139         /*
 140          * USB high speed phy mode select.
 141          */
 142         if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-hsphy-mode-select",
 143             &val, sizeof(val)) > 0) {
 144                 if (bootverbose)
 145                         device_printf(sc->sc_dev,
 146                             "USB high speed PHY mode select (val 0x%x)\n",
 147                             val);
 148                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_HSPHY_CONFIG, val);
 149         }
 150
 151         /*
 152          * Ethernet switch subsystem interface type select.
 153          */
 154         if (OF_getencprop(ofw_bus_get_node(dev), "qcom,ess-interface-select",
 155             &val, sizeof(val)) > 0) {
 156                 uint32_t reg;
 157
 158                 if (bootverbose)
 159                         device_printf(sc->sc_dev,
 160                             "ESS external interface select (val 0x%x)\n",
 161                             val);
 162                 reg = QCOM_TCSR_READ_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET);
 163                 reg &= ~QCOM_TCSR_ESS_INTERFACE_SEL_MASK;
 164                 reg |= (val & QCOM_TCSR_ESS_INTERFACE_SEL_MASK);
 165                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET, reg);
 166         }
 167
 168         /*
 169          * WiFi GLB select.
 170          */
 171         if (OF_getencprop(ofw_bus_get_node(dev), "qcom,wifi_glb_cfg",
 172             &val, sizeof(val)) > 0) {
 173                 if (bootverbose)
 174                         device_printf(sc->sc_dev,
 175                             "WIFI GLB select (val 0x%x)\n",
 176                             val);
 177                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI0_GLB_CFG_OFFSET, val);
 178                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI1_GLB_CFG_OFFSET, val);
 179         }
 180
 181         /*
 182          * WiFi NOC interconnect memory type.
 183          */
 184         if (OF_getencprop(ofw_bus_get_node(dev),
 185             "qcom,wifi_noc_memtype_m0_m2",
 186             &val, sizeof(val)) > 0) {
 187                 if (bootverbose)
 188                         device_printf(sc->sc_dev,
 189                             "WiFi NOC memory type (val 0x%x)\n",
 190                             val);
 191                 QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_PNOC_SNOC_MEMTYPE_M0_M2, val);
 192         }
 193
 194         return (0);
 195
 196 error:
 197         if (sc->sc_mem_res)
 198                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 199         mtx_destroy(&sc->sc_mtx);
 200         return (ret);
 201 }
 202
 203 static int
 204 qcom_tcsr_detach(device_t dev)
 205 {
 206         struct qcom_tcsr_softc *sc = device_get_softc(dev);
 207
 208         if (sc->sc_mem_res)
 209                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 210
 211         mtx_destroy(&sc->sc_mtx);
 212
 213         return (0);
 214 }
 215
 216 static device_method_t qcom_tcsr_methods[] = {
 217         /* Device interface */
 218         DEVMETHOD(device_probe,         qcom_tcsr_probe),
 219         DEVMETHOD(device_attach,        qcom_tcsr_attach),
 220         DEVMETHOD(device_detach,        qcom_tcsr_detach),
 221
 222         DEVMETHOD_END
 223 };
 224
 225 static driver_t qcom_tcsr_driver = {
 226         "qcom_tcsr",
 227         qcom_tcsr_methods,
 228         sizeof(struct qcom_tcsr_softc),
 229 };
 230
 231 static devclass_t qcom_tcsr_devclass;
 232
 233 /*
 234  * This has to be run early, before the rest of the hardware is potentially
 235  * probed/attached.
 236  */
 237 EARLY_DRIVER_MODULE(qcom_tcsr, simplebus, qcom_tcsr_driver,
 238     qcom_tcsr_devclass, 0, 0,
 239     BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
 240 SIMPLEBUS_PNP_INFO(compat_data);