2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This is a pinmux/gpio controller for the IPQ4018/IPQ4019.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <dev/gpio/gpiobusvar.h>
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
56 #include <dev/fdt/fdt_pinctrl.h>
58 #include "qcom_tlmm_var.h"
60 #include "qcom_tlmm_ipq4018_reg.h"
61 #include "qcom_tlmm_ipq4018_hw.h"
66 * Set the pin function. This is a hardware and pin specific mapping.
68 * Returns 0 if OK, an errno if an error was encountered.
71 qcom_tlmm_ipq4018_hw_pin_set_function(struct qcom_tlmm_softc *sc,
72 int pin, int function)
78 if (pin >= sc->gpio_npins)
81 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
82 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
83 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK
84 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT);
85 reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK)
86 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
87 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
88 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
94 * Get the pin function. This is a hardware and pin specific mapping.
96 * Returns 0 if OK, an errno if a nerror was encountered.
99 qcom_tlmm_ipq4018_hw_pin_get_function(struct qcom_tlmm_softc *sc,
100 int pin, int *function)
104 GPIO_LOCK_ASSERT(sc);
106 if (pin >= sc->gpio_npins)
110 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
111 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
112 reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
113 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK;
120 * Set the OE bit to be output. This assumes the port is configured
124 qcom_tlmm_ipq4018_hw_pin_set_oe_output(struct qcom_tlmm_softc *sc,
129 GPIO_LOCK_ASSERT(sc);
131 if (pin >= sc->gpio_npins)
134 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
135 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
136 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
138 QCOM_TLMM_IPQ4018_REG_PIN(pin, QCOM_TLMM_IPQ4018_REG_PIN_CONTROL),
145 * Set the OE bit to be input. This assumes the port is configured
149 qcom_tlmm_ipq4018_hw_pin_set_oe_input(struct qcom_tlmm_softc *sc,
154 GPIO_LOCK_ASSERT(sc);
156 if (pin >= sc->gpio_npins)
159 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
160 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
161 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
162 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
163 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
169 * Get the GPIO pin direction. is_output is set to true if the pin
170 * is an output pin, false if it's set to an input pin.
173 qcom_tlmm_ipq4018_hw_pin_get_oe_state(struct qcom_tlmm_softc *sc,
174 int pin, bool *is_output)
178 GPIO_LOCK_ASSERT(sc);
180 if (pin >= sc->gpio_npins)
183 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
184 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
185 *is_output = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE);
192 * Set the given GPIO pin to the given value.
195 qcom_tlmm_ipq4018_hw_pin_set_output_value(struct qcom_tlmm_softc *sc,
196 uint32_t pin, unsigned int value)
200 GPIO_LOCK_ASSERT(sc);
202 if (pin >= sc->gpio_npins)
205 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
206 QCOM_TLMM_IPQ4018_REG_PIN_IO));
208 reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
210 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
211 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
212 QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
218 * Get the input state of the current GPIO pin.
221 qcom_tlmm_ipq4018_hw_pin_get_output_value(struct qcom_tlmm_softc *sc,
222 uint32_t pin, unsigned int *val)
226 GPIO_LOCK_ASSERT(sc);
228 if (pin >= sc->gpio_npins)
231 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
232 QCOM_TLMM_IPQ4018_REG_PIN_IO));
234 *val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
241 * Get the input state of the current GPIO pin.
244 qcom_tlmm_ipq4018_hw_pin_get_input_value(struct qcom_tlmm_softc *sc,
245 uint32_t pin, unsigned int *val)
249 GPIO_LOCK_ASSERT(sc);
251 if (pin >= sc->gpio_npins)
254 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
255 QCOM_TLMM_IPQ4018_REG_PIN_IO));
257 *val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
263 * Toggle the current output pin value.
266 qcom_tlmm_ipq4018_hw_pin_toggle_output_value(
267 struct qcom_tlmm_softc *sc, uint32_t pin)
271 GPIO_LOCK_ASSERT(sc);
273 if (pin >= sc->gpio_npins)
276 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
277 QCOM_TLMM_IPQ4018_REG_PIN_IO));
278 if ((reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN) == 0)
279 reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
281 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
282 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
283 QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
289 * Configure the pull-up / pull-down top-level configuration.
291 * This doesn't configure the resistor values, just what's enabled/disabled.
294 qcom_tlmm_ipq4018_hw_pin_set_pupd_config(
295 struct qcom_tlmm_softc *sc, uint32_t pin,
296 qcom_tlmm_pin_pupd_config_t pupd)
300 GPIO_LOCK_ASSERT(sc);
302 if (pin >= sc->gpio_npins)
305 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
306 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
308 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK
309 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT);
312 case QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE:
313 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE
314 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
316 case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN:
317 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN
318 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
320 case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP:
321 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP
322 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
324 case QCOM_TLMM_PIN_PUPD_CONFIG_BUS_HOLD:
325 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD
326 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
330 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
331 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
337 * Fetch the current pull-up / pull-down configuration.
340 qcom_tlmm_ipq4018_hw_pin_get_pupd_config(
341 struct qcom_tlmm_softc *sc, uint32_t pin,
342 qcom_tlmm_pin_pupd_config_t *pupd)
346 GPIO_LOCK_ASSERT(sc);
348 if (pin >= sc->gpio_npins)
351 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
352 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
354 reg >>= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
355 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK;
358 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE:
359 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
361 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN:
362 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN;
364 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP:
365 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP;
368 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
376 * Set the drive strength in mA.
379 qcom_tlmm_ipq4018_hw_pin_set_drive_strength(
380 struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t drv)
384 GPIO_LOCK_ASSERT(sc);
386 if (pin >= sc->gpio_npins)
389 /* Convert mA to hardware */
390 if (drv > 16 || drv < 2)
394 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
395 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
397 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT
398 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK);
399 reg |= (drv & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK)
400 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT;
402 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
403 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
409 * Get the drive strength in mA.
412 qcom_tlmm_ipq4018_hw_pin_get_drive_strength(
413 struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t *drv)
417 GPIO_LOCK_ASSERT(sc);
419 if (pin >= sc->gpio_npins)
422 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
423 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
425 *drv = (reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT)
426 & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK;
428 *drv = (*drv + 1) * 2;
435 * Enable/disable whether this pin is passed through to a VM.
438 qcom_tlmm_ipq4018_hw_pin_set_vm(
439 struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
443 GPIO_LOCK_ASSERT(sc);
445 if (pin >= sc->gpio_npins)
448 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
449 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
451 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
453 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
455 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
456 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
462 * Get the VM configuration bit.
465 qcom_tlmm_ipq4018_hw_pin_get_vm(
466 struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
470 GPIO_LOCK_ASSERT(sc);
472 if (pin >= sc->gpio_npins)
475 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
476 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
478 *enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE);
484 * Enable/disable open drain.
487 qcom_tlmm_ipq4018_hw_pin_set_open_drain(
488 struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
492 GPIO_LOCK_ASSERT(sc);
494 if (pin >= sc->gpio_npins)
497 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
498 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
500 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
502 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
504 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
505 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
511 * Get the open drain configuration bit.
514 qcom_tlmm_ipq4018_hw_pin_get_open_drain(
515 struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
519 GPIO_LOCK_ASSERT(sc);
521 if (pin >= sc->gpio_npins)
524 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
525 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
527 *enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE);