2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This is a pinmux/gpio controller for the IPQ4018/IPQ4019.
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <dev/gpio/gpiobusvar.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/fdt/fdt_pinctrl.h>
55 #include "qcom_tlmm_var.h"
57 #include "qcom_tlmm_ipq4018_reg.h"
58 #include "qcom_tlmm_ipq4018_hw.h"
63 * Set the pin function. This is a hardware and pin specific mapping.
65 * Returns 0 if OK, an errno if an error was encountered.
68 qcom_tlmm_ipq4018_hw_pin_set_function(struct qcom_tlmm_softc *sc,
69 int pin, int function)
75 if (pin >= sc->gpio_npins)
78 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
79 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
80 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK
81 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT);
82 reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK)
83 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
84 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
85 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
91 * Get the pin function. This is a hardware and pin specific mapping.
93 * Returns 0 if OK, an errno if a nerror was encountered.
96 qcom_tlmm_ipq4018_hw_pin_get_function(struct qcom_tlmm_softc *sc,
97 int pin, int *function)
101 GPIO_LOCK_ASSERT(sc);
103 if (pin >= sc->gpio_npins)
107 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
108 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
109 reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;
110 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK;
117 * Set the OE bit to be output. This assumes the port is configured
121 qcom_tlmm_ipq4018_hw_pin_set_oe_output(struct qcom_tlmm_softc *sc,
126 GPIO_LOCK_ASSERT(sc);
128 if (pin >= sc->gpio_npins)
131 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
132 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
133 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
135 QCOM_TLMM_IPQ4018_REG_PIN(pin, QCOM_TLMM_IPQ4018_REG_PIN_CONTROL),
142 * Set the OE bit to be input. This assumes the port is configured
146 qcom_tlmm_ipq4018_hw_pin_set_oe_input(struct qcom_tlmm_softc *sc,
151 GPIO_LOCK_ASSERT(sc);
153 if (pin >= sc->gpio_npins)
156 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
157 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
158 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;
159 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
160 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
166 * Get the GPIO pin direction. is_output is set to true if the pin
167 * is an output pin, false if it's set to an input pin.
170 qcom_tlmm_ipq4018_hw_pin_get_oe_state(struct qcom_tlmm_softc *sc,
171 int pin, bool *is_output)
175 GPIO_LOCK_ASSERT(sc);
177 if (pin >= sc->gpio_npins)
180 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
181 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
182 *is_output = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE);
189 * Set the given GPIO pin to the given value.
192 qcom_tlmm_ipq4018_hw_pin_set_output_value(struct qcom_tlmm_softc *sc,
193 uint32_t pin, unsigned int value)
197 GPIO_LOCK_ASSERT(sc);
199 if (pin >= sc->gpio_npins)
202 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
203 QCOM_TLMM_IPQ4018_REG_PIN_IO));
205 reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
207 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
208 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
209 QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
215 * Get the input state of the current GPIO pin.
218 qcom_tlmm_ipq4018_hw_pin_get_output_value(struct qcom_tlmm_softc *sc,
219 uint32_t pin, unsigned int *val)
223 GPIO_LOCK_ASSERT(sc);
225 if (pin >= sc->gpio_npins)
228 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
229 QCOM_TLMM_IPQ4018_REG_PIN_IO));
231 *val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
238 * Get the input state of the current GPIO pin.
241 qcom_tlmm_ipq4018_hw_pin_get_input_value(struct qcom_tlmm_softc *sc,
242 uint32_t pin, unsigned int *val)
246 GPIO_LOCK_ASSERT(sc);
248 if (pin >= sc->gpio_npins)
251 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
252 QCOM_TLMM_IPQ4018_REG_PIN_IO));
254 *val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);
260 * Toggle the current output pin value.
263 qcom_tlmm_ipq4018_hw_pin_toggle_output_value(
264 struct qcom_tlmm_softc *sc, uint32_t pin)
268 GPIO_LOCK_ASSERT(sc);
270 if (pin >= sc->gpio_npins)
273 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
274 QCOM_TLMM_IPQ4018_REG_PIN_IO));
275 if ((reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN) == 0)
276 reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
278 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;
279 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
280 QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);
286 * Configure the pull-up / pull-down top-level configuration.
288 * This doesn't configure the resistor values, just what's enabled/disabled.
291 qcom_tlmm_ipq4018_hw_pin_set_pupd_config(
292 struct qcom_tlmm_softc *sc, uint32_t pin,
293 qcom_tlmm_pin_pupd_config_t pupd)
297 GPIO_LOCK_ASSERT(sc);
299 if (pin >= sc->gpio_npins)
302 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
303 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
305 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK
306 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT);
309 case QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE:
310 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE
311 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
313 case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN:
314 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN
315 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
317 case QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP:
318 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP
319 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
321 case QCOM_TLMM_PIN_PUPD_CONFIG_BUS_HOLD:
322 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD
323 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
327 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
328 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
334 * Fetch the current pull-up / pull-down configuration.
337 qcom_tlmm_ipq4018_hw_pin_get_pupd_config(
338 struct qcom_tlmm_softc *sc, uint32_t pin,
339 qcom_tlmm_pin_pupd_config_t *pupd)
343 GPIO_LOCK_ASSERT(sc);
345 if (pin >= sc->gpio_npins)
348 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
349 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
351 reg >>= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;
352 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK;
355 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE:
356 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
358 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN:
359 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN;
361 case QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP:
362 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP;
365 *pupd = QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE;
373 * Set the drive strength in mA.
376 qcom_tlmm_ipq4018_hw_pin_set_drive_strength(
377 struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t drv)
381 GPIO_LOCK_ASSERT(sc);
383 if (pin >= sc->gpio_npins)
386 /* Convert mA to hardware */
387 if (drv > 16 || drv < 2)
391 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
392 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
394 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT
395 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK);
396 reg |= (drv & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK)
397 << QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT;
399 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
400 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
406 * Get the drive strength in mA.
409 qcom_tlmm_ipq4018_hw_pin_get_drive_strength(
410 struct qcom_tlmm_softc *sc, uint32_t pin, uint8_t *drv)
414 GPIO_LOCK_ASSERT(sc);
416 if (pin >= sc->gpio_npins)
419 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
420 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
422 *drv = (reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT)
423 & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK;
425 *drv = (*drv + 1) * 2;
432 * Enable/disable whether this pin is passed through to a VM.
435 qcom_tlmm_ipq4018_hw_pin_set_vm(
436 struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
440 GPIO_LOCK_ASSERT(sc);
442 if (pin >= sc->gpio_npins)
445 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
446 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
448 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
450 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;
452 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
453 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
459 * Get the VM configuration bit.
462 qcom_tlmm_ipq4018_hw_pin_get_vm(
463 struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
467 GPIO_LOCK_ASSERT(sc);
469 if (pin >= sc->gpio_npins)
472 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
473 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
475 *enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE);
481 * Enable/disable open drain.
484 qcom_tlmm_ipq4018_hw_pin_set_open_drain(
485 struct qcom_tlmm_softc *sc, uint32_t pin, bool enable)
489 GPIO_LOCK_ASSERT(sc);
491 if (pin >= sc->gpio_npins)
494 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
495 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
497 reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
499 reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;
501 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
502 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);
508 * Get the open drain configuration bit.
511 qcom_tlmm_ipq4018_hw_pin_get_open_drain(
512 struct qcom_tlmm_softc *sc, uint32_t pin, bool *enable)
516 GPIO_LOCK_ASSERT(sc);
518 if (pin >= sc->gpio_npins)
521 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,
522 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL));
524 *enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE);