2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __QCOM_TLMM_IPQ4018_REG_H__
31 #define __QCOM_TLMM_IPQ4018_REG_H__
34 * Each GPIO pin configuration block exists in a 0x1000 sized window.
36 #define QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_BASE 0x0
37 #define QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_SIZE 0x1000
40 * Inside each configuration block are the following registers for
41 * controlling the pin.
43 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL 0x00
44 /* 1 = output gpio pin, 0 = input gpio pin */
46 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK 0x3
47 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT 0x0
48 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE 0
49 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN 1
50 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP 2
51 /* There's no BUSHOLD on IPQ4018 */
52 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD 0
53 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK 0x7
54 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT 2
55 /* function/mux control */
56 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT 6
57 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK 0x7
58 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE (1U << 9)
60 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE (1U << 11)
61 /* VM passthrough enable */
62 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE (1U << 12)
64 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_RES_MASK 0x3
65 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_RES_SHIFT 13
66 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_10K 0x0
67 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_1K5 0x1
68 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_35K 0x2
69 #define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_20K 0x3
71 #define QCOM_TLMM_IPQ4018_REG_PIN_IO 0x04
72 #define QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS (1U << 0)
73 /* read gpio input status */
74 #define QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN (1U << 1)
75 /* set gpio output high or low */
78 #define QCOM_TLMM_IPQ4018_REG_PIN_INTR_CONFIG 0x08
79 #define QCOM_TLMM_IPQ4018_REG_PIN_INTR_STATUS 0x0c
81 #define QCOM_TLMM_IPQ4018_REG_PIN(p, reg) \
82 (((p) * QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_SIZE) + \
83 QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_BASE + (reg))
85 #endif /* __QCOM_TLMM_IPQ4018_REG_H__ */