sys/dev/qcom_tlmm/qcom_tlmm_var.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice unmodified, this list of conditions, and the following
  11  *    disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  *
  30  */
  31
  32 #ifndef __QCOM_TLMM_VAR_H__
  33 #define __QCOM_TLMM_VAR_H__
  34
  35 #define GPIO_LOCK(_sc)          mtx_lock(&(_sc)->gpio_mtx)
  36 #define GPIO_UNLOCK(_sc)        mtx_unlock(&(_sc)->gpio_mtx)
  37 #define GPIO_LOCK_ASSERT(_sc)   mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
  38
  39 /*
  40  * register space access macros
  41  */
  42 #define GPIO_WRITE(sc, reg, val)        do {    \
  43                 bus_write_4(sc->gpio_mem_res, (reg), (val)); \
  44         } while (0)
  45
  46 #define GPIO_READ(sc, reg)       bus_read_4(sc->gpio_mem_res, (reg))
  47
  48 #define GPIO_SET_BITS(sc, reg, bits)    \
  49         GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits))
  50
  51 #define GPIO_CLEAR_BITS(sc, reg, bits)  \
  52         GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits))
  53
  54
  55 enum prop_id {
  56         PIN_ID_BIAS_DISABLE = 0,
  57         PIN_ID_BIAS_HIGH_IMPEDANCE,
  58         PIN_ID_BIAS_BUS_HOLD,
  59         PIN_ID_BIAS_PULL_UP,
  60         PIN_ID_BIAS_PULL_DOWN,
  61         PIN_ID_BIAS_PULL_PIN_DEFAULT,
  62         PIN_ID_DRIVE_PUSH_PULL,
  63         PIN_ID_DRIVE_OPEN_DRAIN,
  64         PIN_ID_DRIVE_OPEN_SOURCE,
  65         PIN_ID_DRIVE_STRENGTH,
  66         PIN_ID_INPUT_ENABLE,
  67         PIN_ID_INPUT_DISABLE,
  68         PIN_ID_INPUT_SCHMITT_ENABLE,
  69         PIN_ID_INPUT_SCHMITT_DISABLE,
  70         PIN_ID_INPUT_DEBOUNCE,
  71         PIN_ID_POWER_SOURCE,
  72         PIN_ID_SLEW_RATE,
  73         PIN_ID_LOW_POWER_MODE_ENABLE,
  74         PIN_ID_LOW_POWER_MODE_DISABLE,
  75         PIN_ID_OUTPUT_LOW,
  76         PIN_ID_OUTPUT_HIGH,
  77         PIN_ID_VM_ENABLE,
  78         PIN_ID_VM_DISABLE,
  79         PROP_ID_MAX_ID
  80 };
  81
  82 struct qcom_tlmm_prop_name {
  83         const char              *name;
  84         enum prop_id            id;
  85         int                     have_value;
  86 };
  87
  88 /*
  89  * Pull-up / pull-down configuration.
  90  */
  91 typedef enum {
  92         QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE = 0,
  93         QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN = 1,
  94         QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP = 2,
  95         QCOM_TLMM_PIN_PUPD_CONFIG_BUS_HOLD = 3,
  96 } qcom_tlmm_pin_pupd_config_t;
  97
  98
  99 /*
 100  * Pull-up / pull-down resistor configuration.
 101  */
 102 typedef enum {
 103         QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_10K = 0,
 104         QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_1K5 = 1,
 105         QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_35K = 2,
 106         QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_20K = 3,
 107 } qcom_tlmm_pin_resistor_pupd_config_t;
 108
 109 /*
 110  * configuration for one pin group.
 111  */
 112 struct qcom_tlmm_pinctrl_cfg {
 113         char            *function;
 114         int             params[PROP_ID_MAX_ID];
 115 };
 116
 117 #define GDEF(_id, ...)                                                  \
 118 {                                                                       \
 119         .id = _id,                                                      \
 120         .name = "gpio" #_id,                                            \
 121         .functions = {"gpio", __VA_ARGS__}                              \
 122 }
 123
 124 struct qcom_tlmm_gpio_mux {
 125         int             id;
 126         char            *name;
 127         char            *functions[16]; /* XXX */
 128 };
 129
 130 #define SDEF(n, r, ps, hs...)                                           \
 131 {                                                                       \
 132         .name = n,                                                      \
 133         .reg = r,                                                       \
 134         .pull_shift = ps,                                               \
 135         .hdrv_shift = hs,                                               \
 136 }
 137
 138
 139 struct qcom_tlmm_spec_pin {
 140         char *name;
 141         uint32_t reg;
 142         uint32_t pull_shift;
 143         uint32_t hdrv_shift;
 144 };
 145
 146 struct qcom_tlmm_softc {
 147         device_t                dev;
 148         device_t                busdev;
 149         struct mtx              gpio_mtx;
 150         struct resource         *gpio_mem_res;
 151         int                     gpio_mem_rid;
 152         struct resource         *gpio_irq_res;
 153         int                     gpio_irq_rid;
 154         void                    *gpio_ih;
 155         int                     gpio_npins;
 156         struct gpio_pin         *gpio_pins;
 157         uint32_t                sc_debug;
 158
 159         const struct qcom_tlmm_gpio_mux *gpio_muxes;
 160         const struct qcom_tlmm_spec_pin *spec_pins;
 161 };
 162
 163 /*
 164  * qcom_tlmm_pinmux.c
 165  */
 166 extern  int qcom_tlmm_pinctrl_configure(device_t dev, phandle_t cfgxref);
 167
 168 #endif  /* __QCOM_TLMM_PINMUX_VAR_H__ */