2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
34 #include "ecore_status.h"
35 #include "ecore_hsi_common.h"
36 #include "ecore_hsi_debug_tools.h"
37 #include "ecore_hsi_init_func.h"
38 #include "ecore_hsi_init_tool.h"
39 #include "ecore_proto_if.h"
40 #include "mcp_public.h"
42 #define ECORE_MAJOR_VERSION 8
43 #define ECORE_MINOR_VERSION 33
44 #define ECORE_REVISION_VERSION 5
45 #define ECORE_ENGINEERING_VERSION 0
47 #define ECORE_VERSION \
48 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
49 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
51 #define STORM_FW_VERSION \
52 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
53 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
55 #define MAX_HWFNS_PER_DEVICE 2
57 #define ARRAY_DECL static const
58 #define ECORE_WFQ_UNIT 100
61 #define ECORE_WID_SIZE (1024)
62 #define ECORE_MIN_WIDS (4)
65 #define ECORE_PF_DEMS_SIZE (4)
68 enum ecore_coalescing_mode {
69 ECORE_COAL_MODE_DISABLE,
70 ECORE_COAL_MODE_ENABLE
74 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
75 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
76 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
77 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
78 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
79 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
80 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
81 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
82 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
83 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
84 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
85 ECORE_ENCRYPT_PASSWORD = DRV_MSG_CODE_ENCRYPT_PASSWORD,
86 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
90 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \
91 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) && \
92 !defined(CONFIG_ECORE_IWARP)
93 #define CONFIG_ECORE_L2
94 #define CONFIG_ECORE_SRIOV
95 #define CONFIG_ECORE_ROCE
96 #define CONFIG_ECORE_IWARP
97 #define CONFIG_ECORE_FCOE
98 #define CONFIG_ECORE_ISCSI
99 #define CONFIG_ECORE_LL2
104 #ifndef __EXTRACT__LINUX__IF__
105 #define MASK_FIELD(_name, _value) \
106 ((_value) &= (_name##_MASK))
108 #define FIELD_VALUE(_name, _value) \
109 ((_value & _name##_MASK) << _name##_SHIFT)
111 #define SET_FIELD(value, name, flag) \
113 (value) &= ~(name##_MASK << name##_SHIFT); \
114 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
117 #define GET_FIELD(value, name) \
118 (((value) >> (name##_SHIFT)) & name##_MASK)
120 #define GET_MFW_FIELD(name, field) \
121 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
123 #define SET_MFW_FIELD(name, field, value) \
125 (name) &= ~(field ## _MASK); \
126 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
130 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
132 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
133 (cid * ECORE_PF_DEMS_SIZE);
138 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
140 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
141 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
146 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
147 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
148 ~((1<<(p_hwfn->p_dev->cache_shift))-1))
152 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
156 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
160 #ifndef __EXTRACT__LINUX__IF__
162 /* Debug print definitions */
163 #define DP_ERR(p_dev, fmt, ...) \
165 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
166 __func__, __LINE__, \
167 (p_dev)->name ? (p_dev)->name : "", \
171 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \
173 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \
174 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
175 __func__, __LINE__, \
176 (p_dev)->name ? (p_dev)->name : "", \
178 OSAL_ASSERT(!is_assert); \
182 #define DP_INFO(p_dev, fmt, ...) \
184 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \
185 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
186 __func__, __LINE__, \
187 (p_dev)->name ? (p_dev)->name : "", \
192 #define DP_VERBOSE(p_dev, module, fmt, ...) \
194 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \
195 ((p_dev)->dp_module & module))) { \
196 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
197 __func__, __LINE__, \
198 (p_dev)->name ? (p_dev)->name : "", \
205 ECORE_LEVEL_VERBOSE = 0x0,
206 ECORE_LEVEL_INFO = 0x1,
207 ECORE_LEVEL_NOTICE = 0x2,
208 ECORE_LEVEL_ERR = 0x3,
211 #define ECORE_LOG_LEVEL_SHIFT (30)
212 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
213 #define ECORE_LOG_INFO_MASK (0x40000000)
214 #define ECORE_LOG_NOTICE_MASK (0x80000000)
218 ECORE_MSG_DRV = 0x0001,
219 ECORE_MSG_PROBE = 0x0002,
220 ECORE_MSG_LINK = 0x0004,
221 ECORE_MSG_TIMER = 0x0008,
222 ECORE_MSG_IFDOWN = 0x0010,
223 ECORE_MSG_IFUP = 0x0020,
224 ECORE_MSG_RX_ERR = 0x0040,
225 ECORE_MSG_TX_ERR = 0x0080,
226 ECORE_MSG_TX_QUEUED = 0x0100,
227 ECORE_MSG_INTR = 0x0200,
228 ECORE_MSG_TX_DONE = 0x0400,
229 ECORE_MSG_RX_STATUS = 0x0800,
230 ECORE_MSG_PKTDATA = 0x1000,
231 ECORE_MSG_HW = 0x2000,
232 ECORE_MSG_WOL = 0x4000,
234 ECORE_MSG_SPQ = 0x10000,
235 ECORE_MSG_STATS = 0x20000,
236 ECORE_MSG_DCB = 0x40000,
237 ECORE_MSG_IOV = 0x80000,
238 ECORE_MSG_SP = 0x100000,
239 ECORE_MSG_STORAGE = 0x200000,
240 ECORE_MSG_OOO = 0x200000,
241 ECORE_MSG_CXT = 0x800000,
242 ECORE_MSG_LL2 = 0x1000000,
243 ECORE_MSG_ILT = 0x2000000,
244 ECORE_MSG_RDMA = 0x4000000,
245 ECORE_MSG_DEBUG = 0x8000000,
246 /* to be added...up to 0x8000000 */
250 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
252 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
253 (val == (cond1) ? true1 : \
254 (val == (cond2) ? true2 : def))
257 struct ecore_ptt_pool;
259 struct ecore_sb_info;
260 struct ecore_sb_attn_info;
261 struct ecore_cxt_mngr;
262 struct ecore_dma_mem;
263 struct ecore_sb_sp_info;
264 struct ecore_ll2_info;
265 struct ecore_l2_info;
266 struct ecore_igu_info;
267 struct ecore_mcp_info;
268 struct ecore_dcbx_info;
269 struct ecore_llh_info;
271 struct ecore_rt_data {
276 enum ecore_tunn_mode {
277 ECORE_MODE_L2GENEVE_TUNN,
278 ECORE_MODE_IPGENEVE_TUNN,
279 ECORE_MODE_L2GRE_TUNN,
280 ECORE_MODE_IPGRE_TUNN,
281 ECORE_MODE_VXLAN_TUNN,
284 enum ecore_tunn_clss {
285 ECORE_TUNN_CLSS_MAC_VLAN,
286 ECORE_TUNN_CLSS_MAC_VNI,
287 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
288 ECORE_TUNN_CLSS_INNER_MAC_VNI,
289 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
293 struct ecore_tunn_update_type {
296 enum ecore_tunn_clss tun_cls;
299 struct ecore_tunn_update_udp_port {
304 struct ecore_tunnel_info {
305 struct ecore_tunn_update_type vxlan;
306 struct ecore_tunn_update_type l2_geneve;
307 struct ecore_tunn_update_type ip_geneve;
308 struct ecore_tunn_update_type l2_gre;
309 struct ecore_tunn_update_type ip_gre;
311 struct ecore_tunn_update_udp_port vxlan_port;
312 struct ecore_tunn_update_udp_port geneve_port;
314 bool b_update_rx_cls;
315 bool b_update_tx_cls;
318 /* The PCI personality is not quite synonymous to protocol ID:
319 * 1. All personalities need CORE connections
320 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
322 enum ecore_pci_personality {
329 ECORE_PCI_DEFAULT /* default in shmem */
332 /* All VFs are symetric, all counters are PF + all VFs */
333 struct ecore_qm_iids {
339 /* The PCI relax ordering is either taken care by management FW or can be
340 * enable/disable by ecore client.
342 enum ecore_pci_rlx_odr {
343 ECORE_DEFAULT_RLX_ODR,
344 ECORE_ENABLE_RLX_ODR,
345 ECORE_DISABLE_RLX_ODR
348 #define MAX_PF_PER_PORT 8
350 /* HW / FW resources, output of features supported below, most information
351 * is received from MFW.
353 enum ecore_resources {
365 ECORE_RDMA_STATS_QUEUE,
368 /* This is needed only internally for matching against the IGU.
369 * In case of legacy MFW, would be set to `0'.
376 /* Features that require resources, given as input to the resource management
377 * algorithm, the output are the resources above
392 enum ecore_port_mode {
393 ECORE_PORT_MODE_DE_2X40G,
394 ECORE_PORT_MODE_DE_2X50G,
395 ECORE_PORT_MODE_DE_1X100G,
396 ECORE_PORT_MODE_DE_4X10G_F,
397 ECORE_PORT_MODE_DE_4X10G_E,
398 ECORE_PORT_MODE_DE_4X20G,
399 ECORE_PORT_MODE_DE_1X40G,
400 ECORE_PORT_MODE_DE_2X25G,
401 ECORE_PORT_MODE_DE_1X25G,
402 ECORE_PORT_MODE_DE_4X25G,
403 ECORE_PORT_MODE_DE_2X10G,
414 #ifndef __EXTRACT__LINUX__IF__
415 enum ecore_hw_err_type {
416 ECORE_HW_ERR_FAN_FAIL,
417 ECORE_HW_ERR_MFW_RESP_FAIL,
418 ECORE_HW_ERR_HW_ATTN,
419 ECORE_HW_ERR_DMAE_FAIL,
420 ECORE_HW_ERR_RAMROD_FAIL,
421 ECORE_HW_ERR_FW_ASSERT,
425 enum ecore_wol_support {
426 ECORE_WOL_SUPPORT_NONE,
427 ECORE_WOL_SUPPORT_PME,
430 enum ecore_db_rec_exec {
436 struct ecore_hw_info {
437 /* PCI personality */
438 enum ecore_pci_personality personality;
439 #define ECORE_IS_RDMA_PERSONALITY(dev) \
440 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
441 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
442 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
443 #define ECORE_IS_ROCE_PERSONALITY(dev) \
444 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
445 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
446 #define ECORE_IS_IWARP_PERSONALITY(dev) \
447 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
448 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
449 #define ECORE_IS_L2_PERSONALITY(dev) \
450 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
451 ECORE_IS_RDMA_PERSONALITY(dev))
452 #define ECORE_IS_FCOE_PERSONALITY(dev) \
453 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
454 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
455 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
457 /* Resource Allocation scheme results */
458 u32 resc_start[ECORE_MAX_RESC];
459 u32 resc_num[ECORE_MAX_RESC];
460 u32 feat_num[ECORE_MAX_FEATURES];
462 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
463 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
464 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
465 RESC_NUM(_p_hwfn, resc))
466 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
468 /* Amount of traffic classes HW supports */
471 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */
474 /* The traffic class used by PF for it's offloaded protocol */
483 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */
485 unsigned char hw_mac_addr[ETH_ALEN];
490 struct ecore_igu_info *p_igu_info;
492 u8 max_chains_per_vf;
496 unsigned long device_capabilities;
498 #ifndef __EXTRACT__LINUX__THROW__
499 /* Default DCBX mode */
505 enum ecore_wol_support b_wol_support;
508 /* maximun size of read/write commands (HW limit) */
509 #define DMAE_MAX_RW_SIZE 0x2000
511 struct ecore_dmae_info {
512 /* Spinlock for synchronizing access to functions */
513 osal_spinlock_t lock;
519 dma_addr_t completion_word_phys_addr;
521 /* The memory location where the DMAE writes the completion
522 * value when an operation is finished on this context.
524 u32 *p_completion_word;
526 dma_addr_t intermediate_buffer_phys_addr;
528 /* An intermediate buffer for DMAE operations that use virtual
529 * addresses - data is DMA'd to/from this buffer and then
530 * memcpy'd to/from the virtual address
532 u32 *p_intermediate_buffer;
534 dma_addr_t dmae_cmd_phys_addr;
535 struct dmae_cmd *p_dmae_cmd;
538 struct ecore_wfq_data {
539 u32 default_min_speed; /* When wfq feature is not configured */
540 u32 min_speed; /* when feature is configured for any 1 vport */
544 struct ecore_qm_info {
545 struct init_qm_pq_params *qm_pq_params;
546 struct init_qm_vport_params *qm_vport_params;
547 struct init_qm_port_params *qm_port_params;
561 u8 max_phys_tcs_per_port;
569 struct ecore_wfq_data *wfq_data;
573 struct ecore_db_recovery_info {
575 osal_spinlock_t lock;
576 u32 db_recovery_counter;
584 struct ecore_fw_data {
585 #ifdef CONFIG_ECORE_BINARY_FW
586 struct fw_ver_info *fw_ver_info;
588 const u8 *modes_tree_buf;
589 union init_op *init_ops;
594 enum ecore_mf_mode_bit {
595 /* Supports PF-classification based on tag */
598 /* Supports PF-classification based on MAC */
599 ECORE_MF_LLH_MAC_CLSS,
601 /* Supports PF-classification based on protocol type */
602 ECORE_MF_LLH_PROTO_CLSS,
604 /* Requires a default PF to be set */
605 ECORE_MF_NEED_DEF_PF,
607 /* Allow LL2 to multicast/broadcast */
608 ECORE_MF_LL2_NON_UNICAST,
610 /* Allow Cross-PF [& child VFs] Tx-switching */
611 ECORE_MF_INTER_PF_SWITCH,
613 /* TODO - if we ever re-utilize any of this logic, we can rename */
614 ECORE_MF_UFP_SPECIFIC,
616 ECORE_MF_DISABLE_ARFS,
618 /* Use vlan for steering */
619 ECORE_MF_8021Q_TAGGING,
621 /* Use stag for steering */
622 ECORE_MF_8021AD_TAGGING,
625 enum ecore_ufp_mode {
627 ECORE_UFP_MODE_VNIC_BW,
628 ECORE_UFP_MODE_UNKNOWN
631 enum ecore_ufp_pri_type {
634 ECORE_UFP_PRI_UNKNOWN
637 struct ecore_ufp_info {
638 enum ecore_ufp_pri_type pri_type;
639 enum ecore_ufp_mode mode;
644 BAR_ID_0, /* used for GRC */
645 BAR_ID_1 /* Used for doorbells */
649 struct ecore_dev *p_dev;
650 u8 my_id; /* ID inside the PF */
651 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
652 u8 rel_pf_id; /* Relative to engine*/
654 #define ECORE_PATH_ID(_p_hwfn) \
655 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
661 char name[NAME_SIZE];
666 u8 num_funcs_on_engine;
670 void OSAL_IOMEM *regview;
671 void OSAL_IOMEM *doorbells;
673 unsigned long db_size;
681 struct ecore_ptt_pool *p_ptt_pool;
684 struct ecore_hw_info hw_info;
686 /* rt_array (for init-tool) */
687 struct ecore_rt_data rt_data;
690 struct ecore_spq *p_spq;
693 struct ecore_eq *p_eq;
696 struct ecore_consq *p_consq;
698 /* Slow-Path definitions */
700 bool b_sp_dpc_enabled;
702 struct ecore_ptt *p_main_ptt;
703 struct ecore_ptt *p_dpc_ptt;
705 /* PTP will be used only by the leading funtion.
706 * Usage of all PTP-apis should be synchronized as result.
708 struct ecore_ptt *p_ptp_ptt;
710 struct ecore_sb_sp_info *p_sp_sb;
711 struct ecore_sb_attn_info *p_sb_attn;
713 /* Protocol related */
715 struct ecore_ll2_info *p_ll2_info;
716 struct ecore_ooo_info *p_ooo_info;
717 struct ecore_iscsi_info *p_iscsi_info;
718 struct ecore_fcoe_info *p_fcoe_info;
719 struct ecore_rdma_info *p_rdma_info;
720 struct ecore_pf_params pf_params;
722 bool b_rdma_enabled_in_prs;
723 u32 rdma_prs_search_reg;
725 struct ecore_cxt_mngr *p_cxt_mngr;
727 /* Flag indicating whether interrupts are enabled or not*/
729 bool b_int_requested;
731 /* True if the driver requests for the link */
732 bool b_drv_link_init;
734 struct ecore_vf_iov *vf_iov_info;
735 struct ecore_pf_iov *pf_iov_info;
736 struct ecore_mcp_info *mcp_info;
737 struct ecore_dcbx_info *p_dcbx_info;
738 struct ecore_ufp_info ufp_info;
740 struct ecore_dmae_info dmae_info;
743 struct ecore_qm_info qm_info;
745 /* Buffer for unzipping firmware data */
746 #ifdef CONFIG_ECORE_ZIPPED_FW
750 struct dbg_tools_data dbg_info;
752 /* PWM region specific data */
756 u32 dpi_start_offset; /* this is used to
761 /* If one of the following is set then EDPM shouldn't be used */
766 struct ecore_l2_info *p_l2_info;
768 /* Mechanism for recovering from doorbell drop */
769 struct ecore_db_recovery_info db_recovery_info;
772 #ifndef __EXTRACT__LINUX__THROW__
781 #ifndef __EXTRACT__LINUX__IF__
782 enum ecore_dev_type {
792 char name[NAME_SIZE];
795 enum ecore_dev_type type;
796 /* Translate type/revision combo into the proper conditions */
797 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
798 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
800 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
801 (CHIP_REV_IS_TEDIBEAR(dev)))
803 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
805 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
806 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
807 #define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev))
808 #define ECORE_IS_E5(dev) ((dev)->type == ECORE_DEV_TYPE_E5)
810 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false)
814 #define ECORE_DEV_ID_MASK 0xff00
815 #define ECORE_DEV_ID_MASK_BB 0x1600
816 #define ECORE_DEV_ID_MASK_AH 0x8000
817 #define ECORE_DEV_ID_MASK_E5 0x8100
820 #define CHIP_NUM_MASK 0xffff
821 #define CHIP_NUM_SHIFT 0
824 #define CHIP_REV_MASK 0xf
825 #define CHIP_REV_SHIFT 0
827 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
828 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
829 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
830 #define CHIP_REV_IS_EMUL(_p_dev) \
831 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
832 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
833 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
834 #define CHIP_REV_IS_FPGA(_p_dev) \
835 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
836 #define CHIP_REV_IS_SLOW(_p_dev) \
837 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
838 #define CHIP_REV_IS_A0(_p_dev) \
839 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
840 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
841 #define CHIP_REV_IS_B0(_p_dev) \
842 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
843 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
844 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
846 #define CHIP_REV_IS_A0(_p_dev) \
847 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
848 #define CHIP_REV_IS_B0(_p_dev) \
849 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
853 #define CHIP_METAL_MASK 0xff
854 #define CHIP_METAL_SHIFT 0
857 #define CHIP_BOND_ID_MASK 0xff
858 #define CHIP_BOND_ID_SHIFT 0
862 u8 num_ports_in_engine;
863 u8 num_funcs_in_port;
867 unsigned long mf_bits;
868 #ifndef __EXTRACT__LINUX__THROW__
869 enum ecore_mf_mode mf_mode;
870 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
871 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
872 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
878 /* Add MF related configuration */
882 /* WoL related configurations */
884 u8 wol_mac[ETH_ALEN];
887 enum ecore_coalescing_mode int_coalescing_mode;
888 u16 rx_coalesce_usecs;
889 u16 tx_coalesce_usecs;
891 /* Start Bar offset of first hwfn */
892 void OSAL_IOMEM *regview;
893 void OSAL_IOMEM *doorbells;
895 unsigned long db_size;
901 const struct iro *iro_arr;
902 #define IRO (p_hwfn->p_dev->iro_arr)
906 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
907 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
908 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
910 /* Engine affinity */
914 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
915 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
916 /* Macro for getting the engine-affinitized hwfn for iWARP */
917 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
918 /* Generic macro for getting the engine-affinitized hwfn */
919 #define ECORE_AFFIN_HWFN(dev) \
920 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
921 ECORE_IWARP_AFFIN_HWFN(dev) : \
922 ECORE_FIR_AFFIN_HWFN(dev))
923 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
924 #define ECORE_AFFIN_HWFN_IDX(dev) \
925 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
928 struct ecore_hw_sriov_info *p_iov_info;
929 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
930 struct ecore_tunnel_info tunnel;
932 bool b_dont_override_vf_msix;
938 u32 rdma_max_srq_sge;
941 struct ecore_eth_stats *reset_stats;
942 struct ecore_fw_data *fw_data;
949 /* Indicates whether should prevent attentions from being reasserted */
952 /* Indicates whether allowing the MFW to collect a crash dump */
955 /* Indicates if the reg_fifo is checked after any register access */
963 struct ecore_llh_info *p_llh_info;
966 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
968 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
969 : MAX_NUM_L2_QUEUES_K2)
970 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
972 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
973 : MAX_SB_PER_PATH_K2)
974 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
978 #define CRC8_TABLE_SIZE 256
982 * @brief ecore_concrete_to_sw_fid - get the sw function id from
983 * the concrete value.
985 * @param concrete_fid
987 * @return OSAL_INLINE u8
989 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
991 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
992 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
993 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
997 sw_fid = vfid + MAX_NUM_PFS;
1005 #define MAX_NUM_VOQS_E4 20
1007 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
1008 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
1009 struct ecore_ptt *p_ptt,
1012 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
1013 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
1014 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
1015 int ecore_device_num_engines(struct ecore_dev *p_dev);
1016 int ecore_device_num_ports(struct ecore_dev *p_dev);
1017 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
1020 /* Flags for indication of required queues */
1021 #define PQ_FLAGS_RLS (1 << 0)
1022 #define PQ_FLAGS_MCOS (1 << 1)
1023 #define PQ_FLAGS_LB (1 << 2)
1024 #define PQ_FLAGS_OOO (1 << 3)
1025 #define PQ_FLAGS_ACK (1 << 4)
1026 #define PQ_FLAGS_OFLD (1 << 5)
1027 #define PQ_FLAGS_VFS (1 << 6)
1028 #define PQ_FLAGS_LLT (1 << 7)
1030 /* physical queue index for cm context intialization */
1031 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
1032 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
1033 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
1034 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
1036 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
1038 /* doorbell recovery mechanism */
1039 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
1040 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
1041 enum ecore_db_rec_exec db_exec);
1043 /* amount of resources used in qm init */
1044 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
1045 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
1046 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
1047 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
1048 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
1050 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
1051 ecore_device_num_ports((_p_hwfn)->p_dev))
1053 /* The PFID<->PPFID calculation is based on the relative index of a PF on its
1054 * port. In BB there is a bug in the LLH in which the PPFID is actually engine
1055 * based, and thus it equals the PFID.
1057 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
1058 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1060 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
1062 #define ECORE_PPFID_BY_PFID(_p_hwfn) \
1063 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
1064 (_p_hwfn)->rel_pf_id : \
1065 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
1067 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1068 struct ecore_ptt *p_ptt, u32 addr,
1071 /* Utility functions for dumping the content of the NIG LLH filters */
1072 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
1073 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
1075 #endif /* __ECORE_H */