2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include "ecore_gtt_reg_addr.h"
38 #include "ecore_chain.h"
39 #include "ecore_status.h"
41 #include "ecore_rt_defs.h"
42 #include "ecore_init_ops.h"
43 #include "ecore_int.h"
44 #include "ecore_cxt.h"
45 #include "ecore_spq.h"
46 #include "ecore_init_fw_funcs.h"
47 #include "ecore_sp_commands.h"
48 #include "ecore_dev_api.h"
49 #include "ecore_sriov.h"
51 #include "ecore_ll2.h"
52 #include "ecore_fcoe.h"
53 #include "ecore_iscsi.h"
54 #include "ecore_ooo.h"
55 #include "ecore_mcp.h"
56 #include "ecore_hw_defs.h"
57 #include "mcp_public.h"
58 #include "ecore_rdma.h"
59 #include "ecore_iro.h"
61 #include "ecore_dev_api.h"
62 #include "ecore_dcbx.h"
63 #include "pcics_reg_driver.h"
66 #include "ecore_tcp_ip.h"
71 #pragma warning(disable : 28167)
72 #pragma warning(disable : 28123)
75 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
76 * registers involved are not split and thus configuration is a race where
77 * some of the PFs configuration might be lost.
78 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
79 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
80 * there's more than a single compiled ecore component in system].
82 static osal_spinlock_t qm_lock;
83 static u32 qm_lock_ref_cnt;
85 void ecore_set_ilt_page_size(struct ecore_dev *p_dev, u8 ilt_page_size)
87 p_dev->ilt_page_size = ilt_page_size;
90 /******************** Doorbell Recovery *******************/
91 /* The doorbell recovery mechanism consists of a list of entries which represent
92 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
93 * entity needs to register with the mechanism and provide the parameters
94 * describing it's doorbell, including a location where last used doorbell data
95 * can be found. The doorbell execute function will traverse the list and
96 * doorbell all of the registered entries.
98 struct ecore_db_recovery_entry {
99 osal_list_entry_t list_entry;
100 void OSAL_IOMEM *db_addr;
102 enum ecore_db_rec_width db_width;
103 enum ecore_db_rec_space db_space;
107 /* display a single doorbell recovery entry */
108 static void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
109 struct ecore_db_recovery_entry *db_entry,
112 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
113 action, db_entry, db_entry->db_addr, db_entry->db_data,
114 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
115 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
119 /* doorbell address sanity (address within doorbell bar range) */
120 static bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
123 /* make sure doorbell address is within the doorbell bar */
124 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
125 (u8 *)p_dev->doorbells + p_dev->db_size) {
127 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
128 db_addr, p_dev->doorbells,
129 (u8 *)p_dev->doorbells + p_dev->db_size);
133 /* make sure doorbell data pointer is not null */
135 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
142 /* find hwfn according to the doorbell address */
143 static struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
144 void OSAL_IOMEM *db_addr)
146 struct ecore_hwfn *p_hwfn;
148 /* in CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
149 if (ECORE_IS_CMT(p_dev))
150 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
151 &p_dev->hwfns[0] : &p_dev->hwfns[1];
153 p_hwfn = ECORE_LEADING_HWFN(p_dev);
158 /* add a new entry to the doorbell recovery mechanism */
159 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
160 void OSAL_IOMEM *db_addr,
162 enum ecore_db_rec_width db_width,
163 enum ecore_db_rec_space db_space)
165 struct ecore_db_recovery_entry *db_entry;
166 struct ecore_hwfn *p_hwfn;
168 /* shortcircuit VFs, for now */
170 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
171 return ECORE_SUCCESS;
174 /* sanitize doorbell address */
175 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
178 /* obtain hwfn from doorbell address */
179 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
182 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
184 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
189 db_entry->db_addr = db_addr;
190 db_entry->db_data = db_data;
191 db_entry->db_width = db_width;
192 db_entry->db_space = db_space;
193 db_entry->hwfn_idx = p_hwfn->my_id;
196 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
198 /* protect the list */
199 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
200 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
201 &p_hwfn->db_recovery_info.list);
202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
204 return ECORE_SUCCESS;
207 /* remove an entry from the doorbell recovery mechanism */
208 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
209 void OSAL_IOMEM *db_addr,
212 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
213 enum _ecore_status_t rc = ECORE_INVAL;
214 struct ecore_hwfn *p_hwfn;
216 /* shortcircuit VFs, for now */
218 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
219 return ECORE_SUCCESS;
222 /* sanitize doorbell address */
223 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
226 /* obtain hwfn from doorbell address */
227 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
229 /* protect the list */
230 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
231 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
232 &p_hwfn->db_recovery_info.list,
234 struct ecore_db_recovery_entry) {
236 /* search according to db_data addr since db_addr is not unique (roce) */
237 if (db_entry->db_data == db_data) {
238 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
239 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
240 &p_hwfn->db_recovery_info.list);
246 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
248 if (rc == ECORE_INVAL) {
250 DP_NOTICE(p_hwfn, false,
251 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
254 OSAL_FREE(p_dev, db_entry);
259 /* initialize the doorbell recovery mechanism */
260 static enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
262 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
264 /* make sure db_size was set in p_dev */
265 if (!p_hwfn->p_dev->db_size) {
266 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
270 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
271 #ifdef CONFIG_ECORE_LOCK_ALLOC
272 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
275 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
276 p_hwfn->db_recovery_info.db_recovery_counter = 0;
278 return ECORE_SUCCESS;
281 /* destroy the doorbell recovery mechanism */
282 static void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
284 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
286 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
287 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
288 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
289 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
290 db_entry = OSAL_LIST_FIRST_ENTRY(&p_hwfn->db_recovery_info.list,
291 struct ecore_db_recovery_entry,
293 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
294 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
295 &p_hwfn->db_recovery_info.list);
296 OSAL_FREE(p_hwfn->p_dev, db_entry);
299 #ifdef CONFIG_ECORE_LOCK_ALLOC
300 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
302 p_hwfn->db_recovery_info.db_recovery_counter = 0;
305 /* print the content of the doorbell recovery mechanism */
306 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
308 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
310 DP_NOTICE(p_hwfn, false,
311 "Dispalying doorbell recovery database. Counter was %d\n",
312 p_hwfn->db_recovery_info.db_recovery_counter);
314 /* protect the list */
315 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
316 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
317 &p_hwfn->db_recovery_info.list,
319 struct ecore_db_recovery_entry) {
320 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
323 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
326 /* ring the doorbell of a single doorbell recovery entry */
327 static void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
328 struct ecore_db_recovery_entry *db_entry,
329 enum ecore_db_rec_exec db_exec)
331 if (db_exec != DB_REC_ONCE) {
332 /* Print according to width */
333 if (db_entry->db_width == DB_REC_WIDTH_32B)
334 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
335 "%s doorbell address %p data %x\n",
336 db_exec == DB_REC_DRY_RUN ?
337 "would have rung" : "ringing",
339 *(u32 *)db_entry->db_data);
341 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
342 "%s doorbell address %p data %llx\n",
343 db_exec == DB_REC_DRY_RUN ?
344 "would have rung" : "ringing",
346 (unsigned long long)*(u64 *)(db_entry->db_data));
350 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
354 /* Flush the write combined buffer. Since there are multiple doorbelling
355 * entities using the same address, if we don't flush, a transaction
358 OSAL_WMB(p_hwfn->p_dev);
360 /* Ring the doorbell */
361 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
362 if (db_entry->db_width == DB_REC_WIDTH_32B)
363 DIRECT_REG_WR(p_hwfn, db_entry->db_addr, *(u32 *)(db_entry->db_data));
365 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr, *(u64 *)(db_entry->db_data));
368 /* Flush the write combined buffer. Next doorbell may come from a
369 * different entity to the same address...
371 OSAL_WMB(p_hwfn->p_dev);
374 /* traverse the doorbell recovery entry list and ring all the doorbells */
375 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
376 enum ecore_db_rec_exec db_exec)
378 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
380 if (db_exec != DB_REC_ONCE) {
381 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
382 p_hwfn->db_recovery_info.db_recovery_counter);
384 /* track amount of times recovery was executed */
385 p_hwfn->db_recovery_info.db_recovery_counter++;
388 /* protect the list */
389 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
390 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
391 &p_hwfn->db_recovery_info.list,
393 struct ecore_db_recovery_entry) {
394 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
395 if (db_exec == DB_REC_ONCE)
399 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
401 /******************** Doorbell Recovery end ****************/
403 /********************************** NIG LLH ***********************************/
405 enum ecore_llh_filter_type {
406 ECORE_LLH_FILTER_TYPE_MAC,
407 ECORE_LLH_FILTER_TYPE_PROTOCOL,
410 struct ecore_llh_mac_filter {
414 struct ecore_llh_protocol_filter {
415 enum ecore_llh_prot_filter_type_t type;
416 u16 source_port_or_eth_type;
420 union ecore_llh_filter {
421 struct ecore_llh_mac_filter mac;
422 struct ecore_llh_protocol_filter protocol;
425 struct ecore_llh_filter_info {
428 enum ecore_llh_filter_type type;
429 union ecore_llh_filter filter;
432 struct ecore_llh_info {
433 /* Number of LLH filters banks */
436 #define MAX_NUM_PPFID 8
437 u8 ppfid_array[MAX_NUM_PPFID];
439 /* Array of filters arrays:
440 * "num_ppfid" elements of filters banks, where each is an array of
441 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
443 struct ecore_llh_filter_info **pp_filters;
446 static void ecore_llh_free(struct ecore_dev *p_dev)
448 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
451 if (p_llh_info != OSAL_NULL) {
452 if (p_llh_info->pp_filters != OSAL_NULL) {
453 for (i = 0; i < p_llh_info->num_ppfid; i++)
454 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
457 OSAL_FREE(p_dev, p_llh_info->pp_filters);
460 OSAL_FREE(p_dev, p_llh_info);
461 p_dev->p_llh_info = OSAL_NULL;
464 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
466 struct ecore_llh_info *p_llh_info;
469 p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
472 p_dev->p_llh_info = p_llh_info;
474 for (i = 0; i < MAX_NUM_PPFID; i++) {
475 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
478 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
479 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
480 p_llh_info->num_ppfid, i);
481 p_llh_info->num_ppfid++;
484 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
485 p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
486 if (!p_llh_info->pp_filters)
489 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
490 sizeof(**p_llh_info->pp_filters);
491 for (i = 0; i < p_llh_info->num_ppfid; i++) {
492 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
494 if (!p_llh_info->pp_filters[i])
498 return ECORE_SUCCESS;
501 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
502 u8 ppfid, u8 filter_idx,
505 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
507 if (ppfid >= p_llh_info->num_ppfid) {
508 DP_NOTICE(p_dev, false,
509 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
510 action, ppfid, p_llh_info->num_ppfid);
514 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
515 DP_NOTICE(p_dev, false,
516 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
517 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
521 return ECORE_SUCCESS;
524 #define ECORE_LLH_INVALID_FILTER_IDX 0xff
526 static enum _ecore_status_t
527 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
528 union ecore_llh_filter *p_filter,
531 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
532 struct ecore_llh_filter_info *p_filters;
533 enum _ecore_status_t rc;
536 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
537 if (rc != ECORE_SUCCESS)
540 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
542 p_filters = p_llh_info->pp_filters[ppfid];
543 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
544 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
545 sizeof(*p_filter))) {
551 return ECORE_SUCCESS;
554 static enum _ecore_status_t
555 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
558 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
559 struct ecore_llh_filter_info *p_filters;
560 enum _ecore_status_t rc;
563 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
564 if (rc != ECORE_SUCCESS)
567 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
569 p_filters = p_llh_info->pp_filters[ppfid];
570 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
571 if (!p_filters[i].b_enabled) {
577 return ECORE_SUCCESS;
580 static enum _ecore_status_t
581 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
582 enum ecore_llh_filter_type type,
583 union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
585 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
586 struct ecore_llh_filter_info *p_filters;
587 enum _ecore_status_t rc;
589 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
590 if (rc != ECORE_SUCCESS)
593 p_filters = p_llh_info->pp_filters[ppfid];
594 if (!p_filters[filter_idx].ref_cnt) {
595 p_filters[filter_idx].b_enabled = true;
596 p_filters[filter_idx].type = type;
597 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
598 sizeof(p_filters[filter_idx].filter));
601 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
603 return ECORE_SUCCESS;
606 static enum _ecore_status_t
607 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
608 enum ecore_llh_filter_type type,
609 union ecore_llh_filter *p_filter,
610 u8 *p_filter_idx, u32 *p_ref_cnt)
612 enum _ecore_status_t rc;
614 /* Check if the same filter already exist */
615 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
617 if (rc != ECORE_SUCCESS)
620 /* Find a new entry in case of a new filter */
621 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
622 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
623 if (rc != ECORE_SUCCESS)
627 /* No free entry was found */
628 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
629 DP_NOTICE(p_dev, false,
630 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
632 return ECORE_NORESOURCES;
635 return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
636 p_filter, p_ref_cnt);
639 static enum _ecore_status_t
640 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
641 u8 filter_idx, u32 *p_ref_cnt)
643 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
644 struct ecore_llh_filter_info *p_filters;
645 enum _ecore_status_t rc;
647 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
648 if (rc != ECORE_SUCCESS)
651 p_filters = p_llh_info->pp_filters[ppfid];
652 if (!p_filters[filter_idx].ref_cnt) {
653 DP_NOTICE(p_dev, false,
654 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
658 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
659 if (!p_filters[filter_idx].ref_cnt)
660 OSAL_MEM_ZERO(&p_filters[filter_idx],
661 sizeof(p_filters[filter_idx]));
663 return ECORE_SUCCESS;
666 static enum _ecore_status_t
667 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
668 union ecore_llh_filter *p_filter,
669 u8 *p_filter_idx, u32 *p_ref_cnt)
671 enum _ecore_status_t rc;
673 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
675 if (rc != ECORE_SUCCESS)
678 /* No matching filter was found */
679 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
680 DP_NOTICE(p_dev, false,
681 "Failed to find a filter in the LLH shadow\n");
685 return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
689 static enum _ecore_status_t
690 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
692 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
693 struct ecore_llh_filter_info *p_filters;
694 enum _ecore_status_t rc;
696 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
697 if (rc != ECORE_SUCCESS)
700 p_filters = p_llh_info->pp_filters[ppfid];
701 OSAL_MEM_ZERO(p_filters,
702 NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
704 return ECORE_SUCCESS;
707 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
708 u8 rel_ppfid, u8 *p_abs_ppfid)
710 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
712 if (rel_ppfid >= p_llh_info->num_ppfid) {
713 DP_NOTICE(p_dev, false,
714 "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
715 rel_ppfid, (u8)(p_llh_info->num_ppfid - 1));
719 *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
721 return ECORE_SUCCESS;
724 static enum _ecore_status_t
725 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
727 struct ecore_dev *p_dev = p_hwfn->p_dev;
730 enum _ecore_status_t rc;
732 rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
733 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
734 DP_NOTICE(p_hwfn, false,
735 "Failed to get the engine affinity configuration\n");
739 /* RoCE PF is bound to a single engine */
740 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
741 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
742 rc = ecore_llh_set_roce_affinity(p_dev, eng);
743 if (rc != ECORE_SUCCESS) {
744 DP_NOTICE(p_dev, false,
745 "Failed to set the RoCE engine affinity\n");
749 DP_VERBOSE(p_dev, ECORE_MSG_SP,
750 "LLH: Set the engine affinity of RoCE packets as %d\n",
754 /* Storage PF is bound to a single engine while L2 PF uses both */
755 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
756 ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
757 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
758 else /* L2_PERSONALITY */
759 eng = ECORE_BOTH_ENG;
761 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
762 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
763 if (rc != ECORE_SUCCESS) {
764 DP_NOTICE(p_dev, false,
765 "Failed to set the engine affinity of ppfid %d\n",
771 DP_VERBOSE(p_dev, ECORE_MSG_SP,
772 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
775 return ECORE_SUCCESS;
778 static enum _ecore_status_t
779 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
780 bool avoid_eng_affin)
782 struct ecore_dev *p_dev = p_hwfn->p_dev;
783 enum _ecore_status_t rc;
785 /* Backwards compatible mode:
786 * - RoCE packets - Use engine 0.
787 * - Non-RoCE packets - Use connection based classification for L2 PFs,
788 * and engine 0 otherwise.
790 if (avoid_eng_affin) {
794 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
796 rc = ecore_llh_set_roce_affinity(p_dev, eng);
797 if (rc != ECORE_SUCCESS) {
798 DP_NOTICE(p_dev, false,
799 "Failed to set the RoCE engine affinity\n");
803 DP_VERBOSE(p_dev, ECORE_MSG_SP,
804 "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
808 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
809 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
811 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
812 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
813 if (rc != ECORE_SUCCESS) {
814 DP_NOTICE(p_dev, false,
815 "Failed to set the engine affinity of ppfid %d\n",
821 DP_VERBOSE(p_dev, ECORE_MSG_SP,
822 "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
825 return ECORE_SUCCESS;
828 return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
831 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
832 struct ecore_ptt *p_ptt,
833 bool avoid_eng_affin)
835 struct ecore_dev *p_dev = p_hwfn->p_dev;
837 enum _ecore_status_t rc;
839 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
842 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
843 if (rc != ECORE_SUCCESS)
846 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
847 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
850 if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
851 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
852 rc = ecore_llh_add_mac_filter(p_dev, 0,
853 p_hwfn->hw_info.hw_mac_addr);
854 if (rc != ECORE_SUCCESS)
855 DP_NOTICE(p_dev, false,
856 "Failed to add an LLH filter with the primary MAC\n");
859 if (ECORE_IS_CMT(p_dev)) {
860 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
861 if (rc != ECORE_SUCCESS)
865 return ECORE_SUCCESS;
868 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
870 return p_dev->p_llh_info->num_ppfid;
873 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
875 return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
878 /* TBD - should be removed when these definitions are available in reg_addr.h */
879 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
880 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
881 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
882 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
884 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
885 u8 ppfid, enum ecore_eng eng)
887 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
888 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
889 u32 addr, val, eng_sel;
890 enum _ecore_status_t rc = ECORE_SUCCESS;
893 if (p_ptt == OSAL_NULL)
896 if (!ECORE_IS_CMT(p_dev))
899 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
900 if (rc != ECORE_SUCCESS)
914 DP_NOTICE(p_dev, false,
915 "Invalid affinity value for ppfid [%d]\n", eng);
920 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
921 val = ecore_rd(p_hwfn, p_ptt, addr);
922 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
923 ecore_wr(p_hwfn, p_ptt, addr, val);
925 /* The iWARP affinity is set as the affinity of ppfid 0 */
926 if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
927 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
929 ecore_ptt_release(p_hwfn, p_ptt);
934 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
937 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
938 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
939 u32 addr, val, eng_sel;
940 enum _ecore_status_t rc = ECORE_SUCCESS;
943 if (p_ptt == OSAL_NULL)
946 if (!ECORE_IS_CMT(p_dev))
958 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
959 0xf /* QP bit 15 */);
962 DP_NOTICE(p_dev, false,
963 "Invalid affinity value for RoCE [%d]\n", eng);
968 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
969 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
970 if (rc != ECORE_SUCCESS)
973 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
974 val = ecore_rd(p_hwfn, p_ptt, addr);
975 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
976 ecore_wr(p_hwfn, p_ptt, addr, val);
979 ecore_ptt_release(p_hwfn, p_ptt);
984 struct ecore_llh_filter_e4_details {
992 static enum _ecore_status_t
993 ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,
994 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
995 struct ecore_llh_filter_e4_details *p_details,
998 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
999 struct ecore_dmae_params params;
1000 enum _ecore_status_t rc;
1003 /* The NIG/LLH registers that are accessed in this function have only 16
1004 * rows which are exposed to a PF. I.e. only the 16 filters of its
1006 * Accessing filters of other ppfids requires pretending to other PFs,
1007 * and thus the usage of the ecore_ppfid_rd/wr() functions.
1010 /* Filter enable - should be done first when removing a filter */
1011 if (b_write_access && !p_details->enable) {
1012 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
1013 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1018 addr = NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * filter_idx * 0x4;
1019 OSAL_MEMSET(¶ms, 0, sizeof(params));
1021 if (b_write_access) {
1022 params.flags = ECORE_DMAE_FLAG_PF_DST;
1023 params.dst_pfid = pfid;
1024 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
1025 (u64)(osal_uintptr_t)&p_details->value,
1026 addr, 2 /* size_in_dwords */, ¶ms);
1028 params.flags = ECORE_DMAE_FLAG_PF_SRC |
1029 ECORE_DMAE_FLAG_COMPLETION_DST;
1030 params.src_pfid = pfid;
1031 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
1032 (u64)(osal_uintptr_t)&p_details->value,
1033 2 /* size_in_dwords */, ¶ms);
1036 if (rc != ECORE_SUCCESS)
1040 addr = NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + filter_idx * 0x4;
1042 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
1044 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1047 /* Filter protocol type */
1048 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + filter_idx * 0x4;
1050 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1051 p_details->protocol_type);
1053 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1056 /* Filter header select */
1057 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 + filter_idx * 0x4;
1059 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1060 p_details->hdr_sel);
1062 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1065 /* Filter enable - should be done last when adding a filter */
1066 if (!b_write_access || p_details->enable) {
1067 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
1069 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1072 p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1076 return ECORE_SUCCESS;
1079 static enum _ecore_status_t
1080 ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1081 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1084 struct ecore_llh_filter_e4_details filter_details;
1086 filter_details.enable = 1;
1087 filter_details.value = ((u64)high << 32) | low;
1088 filter_details.hdr_sel = 0;
1089 filter_details.protocol_type = filter_prot_type;
1090 filter_details.mode = filter_prot_type ?
1091 1 : /* protocol-based classification */
1092 0; /* MAC-address based classification */
1094 return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1096 true /* write access */);
1099 static enum _ecore_status_t
1100 ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn,
1101 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1103 struct ecore_llh_filter_e4_details filter_details;
1105 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1107 return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1109 true /* write access */);
1112 /* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
1113 * Should be removed when the function is implemented.
1115 static enum _ecore_status_t
1116 ecore_llh_add_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
1117 struct ecore_ptt OSAL_UNUSED *p_ptt,
1118 u8 OSAL_UNUSED abs_ppfid, u8 OSAL_UNUSED filter_idx,
1119 u8 OSAL_UNUSED filter_prot_type, u32 OSAL_UNUSED high,
1120 u32 OSAL_UNUSED low)
1122 ECORE_E5_MISSING_CODE;
1124 return ECORE_NOTIMPL;
1127 /* OSAL_UNUSED is temporary used to avoid unused-parameter compilation warnings.
1128 * Should be removed when the function is implemented.
1130 static enum _ecore_status_t
1131 ecore_llh_remove_filter_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
1132 struct ecore_ptt OSAL_UNUSED *p_ptt,
1133 u8 OSAL_UNUSED abs_ppfid,
1134 u8 OSAL_UNUSED filter_idx)
1136 ECORE_E5_MISSING_CODE;
1138 return ECORE_NOTIMPL;
1141 static enum _ecore_status_t
1142 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1143 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, u32 high,
1146 if (ECORE_IS_E4(p_hwfn->p_dev))
1147 return ecore_llh_add_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1148 filter_idx, filter_prot_type,
1151 return ecore_llh_add_filter_e5(p_hwfn, p_ptt, abs_ppfid,
1152 filter_idx, filter_prot_type,
1156 static enum _ecore_status_t
1157 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1158 u8 abs_ppfid, u8 filter_idx)
1160 if (ECORE_IS_E4(p_hwfn->p_dev))
1161 return ecore_llh_remove_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1164 return ecore_llh_remove_filter_e5(p_hwfn, p_ptt, abs_ppfid,
1168 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1169 u8 mac_addr[ETH_ALEN])
1171 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1172 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1173 union ecore_llh_filter filter;
1174 u8 filter_idx, abs_ppfid;
1175 u32 high, low, ref_cnt;
1176 enum _ecore_status_t rc = ECORE_SUCCESS;
1178 if (p_ptt == OSAL_NULL)
1181 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1184 OSAL_MEM_ZERO(&filter, sizeof(filter));
1185 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1186 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1187 ECORE_LLH_FILTER_TYPE_MAC,
1188 &filter, &filter_idx, &ref_cnt);
1189 if (rc != ECORE_SUCCESS)
1192 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1193 if (rc != ECORE_SUCCESS)
1196 /* Configure the LLH only in case of a new the filter */
1198 high = mac_addr[1] | (mac_addr[0] << 8);
1199 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1200 (mac_addr[2] << 24);
1201 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1203 if (rc != ECORE_SUCCESS)
1207 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1208 "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1209 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1210 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1216 DP_NOTICE(p_dev, false,
1217 "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1218 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1219 mac_addr[4], mac_addr[5], ppfid);
1221 ecore_ptt_release(p_hwfn, p_ptt);
1226 static enum _ecore_status_t
1227 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1228 enum ecore_llh_prot_filter_type_t type,
1229 u16 source_port_or_eth_type, u16 dest_port,
1230 u8 *str, osal_size_t str_len)
1233 case ECORE_LLH_FILTER_ETHERTYPE:
1234 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1235 source_port_or_eth_type);
1237 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1238 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1239 source_port_or_eth_type);
1241 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1242 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1243 source_port_or_eth_type);
1245 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1246 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1248 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1249 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1251 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1252 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1253 source_port_or_eth_type, dest_port);
1255 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1256 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1257 source_port_or_eth_type, dest_port);
1260 DP_NOTICE(p_dev, true,
1261 "Non valid LLH protocol filter type %d\n", type);
1265 return ECORE_SUCCESS;
1268 static enum _ecore_status_t
1269 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1270 enum ecore_llh_prot_filter_type_t type,
1271 u16 source_port_or_eth_type, u16 dest_port,
1272 u32 *p_high, u32 *p_low)
1278 case ECORE_LLH_FILTER_ETHERTYPE:
1279 *p_high = source_port_or_eth_type;
1281 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1282 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1283 *p_low = source_port_or_eth_type << 16;
1285 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1286 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1289 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1290 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1291 *p_low = (source_port_or_eth_type << 16) | dest_port;
1294 DP_NOTICE(p_dev, true,
1295 "Non valid LLH protocol filter type %d\n", type);
1299 return ECORE_SUCCESS;
1302 enum _ecore_status_t
1303 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1304 enum ecore_llh_prot_filter_type_t type,
1305 u16 source_port_or_eth_type, u16 dest_port)
1307 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1308 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1309 u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1310 union ecore_llh_filter filter;
1311 u32 high, low, ref_cnt;
1312 enum _ecore_status_t rc = ECORE_SUCCESS;
1314 if (p_ptt == OSAL_NULL)
1317 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1320 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1321 source_port_or_eth_type,
1322 dest_port, str, sizeof(str));
1323 if (rc != ECORE_SUCCESS)
1326 OSAL_MEM_ZERO(&filter, sizeof(filter));
1327 filter.protocol.type = type;
1328 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1329 filter.protocol.dest_port = dest_port;
1330 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1331 ECORE_LLH_FILTER_TYPE_PROTOCOL,
1332 &filter, &filter_idx, &ref_cnt);
1333 if (rc != ECORE_SUCCESS)
1336 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1337 if (rc != ECORE_SUCCESS)
1340 /* Configure the LLH only in case of a new the filter */
1342 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1343 source_port_or_eth_type,
1344 dest_port, &high, &low);
1345 if (rc != ECORE_SUCCESS)
1348 type_bitmap = 0x1 << type;
1349 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1350 type_bitmap, high, low);
1351 if (rc != ECORE_SUCCESS)
1355 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1356 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1357 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1362 DP_NOTICE(p_hwfn, false,
1363 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1366 ecore_ptt_release(p_hwfn, p_ptt);
1371 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1372 u8 mac_addr[ETH_ALEN])
1374 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1375 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1376 union ecore_llh_filter filter;
1377 u8 filter_idx, abs_ppfid;
1378 enum _ecore_status_t rc = ECORE_SUCCESS;
1381 if (p_ptt == OSAL_NULL)
1384 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1387 OSAL_MEM_ZERO(&filter, sizeof(filter));
1388 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1389 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1391 if (rc != ECORE_SUCCESS)
1394 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1395 if (rc != ECORE_SUCCESS)
1398 /* Remove from the LLH in case the filter is not in use */
1400 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1402 if (rc != ECORE_SUCCESS)
1406 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1407 "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1408 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1409 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1415 DP_NOTICE(p_dev, false,
1416 "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1417 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1418 mac_addr[4], mac_addr[5], ppfid);
1420 ecore_ptt_release(p_hwfn, p_ptt);
1423 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1424 enum ecore_llh_prot_filter_type_t type,
1425 u16 source_port_or_eth_type,
1428 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1429 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1430 u8 filter_idx, abs_ppfid, str[32];
1431 union ecore_llh_filter filter;
1432 enum _ecore_status_t rc = ECORE_SUCCESS;
1435 if (p_ptt == OSAL_NULL)
1438 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1441 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1442 source_port_or_eth_type,
1443 dest_port, str, sizeof(str));
1444 if (rc != ECORE_SUCCESS)
1447 OSAL_MEM_ZERO(&filter, sizeof(filter));
1448 filter.protocol.type = type;
1449 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1450 filter.protocol.dest_port = dest_port;
1451 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1453 if (rc != ECORE_SUCCESS)
1456 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1457 if (rc != ECORE_SUCCESS)
1460 /* Remove from the LLH in case the filter is not in use */
1462 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1464 if (rc != ECORE_SUCCESS)
1468 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1469 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1470 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1475 DP_NOTICE(p_dev, false,
1476 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1479 ecore_ptt_release(p_hwfn, p_ptt);
1482 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1484 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1485 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1486 u8 filter_idx, abs_ppfid;
1487 enum _ecore_status_t rc = ECORE_SUCCESS;
1489 if (p_ptt == OSAL_NULL)
1492 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1493 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1496 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1497 if (rc != ECORE_SUCCESS)
1500 rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1501 if (rc != ECORE_SUCCESS)
1504 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1506 if (ECORE_IS_E4(p_dev))
1507 rc = ecore_llh_remove_filter_e4(p_hwfn, p_ptt,
1508 abs_ppfid, filter_idx);
1510 rc = ecore_llh_remove_filter_e5(p_hwfn, p_ptt,
1511 abs_ppfid, filter_idx);
1512 if (rc != ECORE_SUCCESS)
1516 ecore_ptt_release(p_hwfn, p_ptt);
1519 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1523 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1524 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1527 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1528 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1531 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1532 struct ecore_ptt *p_ptt, u32 addr,
1535 struct ecore_dev *p_dev = p_hwfn->p_dev;
1536 u8 ppfid, abs_ppfid;
1537 enum _ecore_status_t rc;
1539 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1540 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1541 if (rc != ECORE_SUCCESS)
1544 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1547 return ECORE_SUCCESS;
1550 static enum _ecore_status_t
1551 ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1554 struct ecore_llh_filter_e4_details filter_details;
1555 u8 abs_ppfid, filter_idx;
1557 enum _ecore_status_t rc;
1559 rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1560 if (rc != ECORE_SUCCESS)
1563 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1564 DP_NOTICE(p_hwfn, false,
1565 "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1566 p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1567 ecore_rd(p_hwfn, p_ptt, addr));
1569 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1571 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1572 rc = ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1573 filter_idx, &filter_details,
1574 false /* read access */);
1575 if (rc != ECORE_SUCCESS)
1578 DP_NOTICE(p_hwfn, false,
1579 "filter %2hhd: enable %d, value 0x%016llx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1580 filter_idx, filter_details.enable,
1581 (unsigned long long)filter_details.value, filter_details.mode,
1582 filter_details.protocol_type, filter_details.hdr_sel);
1585 return ECORE_SUCCESS;
1588 static enum _ecore_status_t
1589 ecore_llh_dump_ppfid_e5(struct ecore_hwfn OSAL_UNUSED *p_hwfn,
1590 struct ecore_ptt OSAL_UNUSED *p_ptt,
1591 u8 OSAL_UNUSED ppfid)
1593 ECORE_E5_MISSING_CODE;
1595 return ECORE_NOTIMPL;
1598 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1600 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1601 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1602 enum _ecore_status_t rc;
1604 if (p_ptt == OSAL_NULL)
1607 if (ECORE_IS_E4(p_dev))
1608 rc = ecore_llh_dump_ppfid_e4(p_hwfn, p_ptt, ppfid);
1610 rc = ecore_llh_dump_ppfid_e5(p_hwfn, p_ptt, ppfid);
1612 ecore_ptt_release(p_hwfn, p_ptt);
1617 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1620 enum _ecore_status_t rc;
1622 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1623 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1624 if (rc != ECORE_SUCCESS)
1628 return ECORE_SUCCESS;
1631 /******************************* NIG LLH - End ********************************/
1634 #define ECORE_MIN_DPIS (4) /* The minimal number of DPIs required to
1635 * load the driver. The number was
1640 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1642 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1643 struct ecore_ptt *p_ptt,
1646 u32 bar_reg = (bar_id == BAR_ID_0 ?
1647 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1650 if (IS_VF(p_hwfn->p_dev))
1651 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1653 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1655 return 1 << (val + 15);
1657 /* The above registers were updated in the past only in CMT mode. Since
1658 * they were found to be useful MFW started updating them from 8.7.7.0.
1659 * In older MFW versions they are set to 0 which means disabled.
1661 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1663 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1664 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1667 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1672 void ecore_init_dp(struct ecore_dev *p_dev,
1679 p_dev->dp_level = dp_level;
1680 p_dev->dp_module = dp_module;
1681 p_dev->dp_ctx = dp_ctx;
1682 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1683 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1685 p_hwfn->dp_level = dp_level;
1686 p_hwfn->dp_module = dp_module;
1687 p_hwfn->dp_ctx = dp_ctx;
1691 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1695 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1696 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1698 p_hwfn->p_dev = p_dev;
1700 p_hwfn->b_active = false;
1702 #ifdef CONFIG_ECORE_LOCK_ALLOC
1703 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1706 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1709 /* hwfn 0 is always active */
1710 p_dev->hwfns[0].b_active = true;
1712 /* set the default cache alignment to 128 (may be overridden later) */
1713 p_dev->cache_shift = 7;
1715 p_dev->ilt_page_size = ECORE_DEFAULT_ILT_PAGE_SIZE;
1717 return ECORE_SUCCESS;
1718 #ifdef CONFIG_ECORE_LOCK_ALLOC
1721 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1723 p_hwfn = &p_dev->hwfns[i];
1724 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1730 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1732 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1734 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1735 qm_info->qm_pq_params = OSAL_NULL;
1736 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1737 qm_info->qm_vport_params = OSAL_NULL;
1738 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1739 qm_info->qm_port_params = OSAL_NULL;
1740 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1741 qm_info->wfq_data = OSAL_NULL;
1744 void ecore_resc_free(struct ecore_dev *p_dev)
1749 for_each_hwfn(p_dev, i)
1750 ecore_l2_free(&p_dev->hwfns[i]);
1754 OSAL_FREE(p_dev, p_dev->fw_data);
1755 p_dev->fw_data = OSAL_NULL;
1757 OSAL_FREE(p_dev, p_dev->reset_stats);
1758 p_dev->reset_stats = OSAL_NULL;
1760 ecore_llh_free(p_dev);
1762 for_each_hwfn(p_dev, i) {
1763 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1765 ecore_cxt_mngr_free(p_hwfn);
1766 ecore_qm_info_free(p_hwfn);
1767 ecore_spq_free(p_hwfn);
1768 ecore_eq_free(p_hwfn);
1769 ecore_consq_free(p_hwfn);
1770 ecore_int_free(p_hwfn);
1771 #ifdef CONFIG_ECORE_LL2
1772 ecore_ll2_free(p_hwfn);
1774 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
1775 ecore_fcoe_free(p_hwfn);
1777 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1778 ecore_iscsi_free(p_hwfn);
1779 ecore_ooo_free(p_hwfn);
1782 #ifdef CONFIG_ECORE_ROCE
1783 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn))
1784 ecore_rdma_info_free(p_hwfn);
1786 ecore_iov_free(p_hwfn);
1787 ecore_l2_free(p_hwfn);
1788 ecore_dmae_info_free(p_hwfn);
1789 ecore_dcbx_info_free(p_hwfn);
1790 /* @@@TBD Flush work-queue ?*/
1792 /* destroy doorbell recovery mechanism */
1793 ecore_db_recovery_teardown(p_hwfn);
1797 /******************** QM initialization *******************/
1798 /* bitmaps for indicating active traffic classes. Special case for Arrowhead 4 port */
1799 #define ACTIVE_TCS_BMAP 0x9f /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1800 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf /* 0..3 actually used, OOO and high priority stuff all use 3 */
1802 /* determines the physical queue flags for a given PF. */
1803 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1808 flags = PQ_FLAGS_LB;
1811 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1812 flags |= PQ_FLAGS_VFS;
1813 if (IS_ECORE_DCQCN(p_hwfn))
1814 flags |= PQ_FLAGS_RLS;
1816 /* protocol flags */
1817 switch (p_hwfn->hw_info.personality) {
1819 flags |= PQ_FLAGS_MCOS;
1821 case ECORE_PCI_FCOE:
1822 flags |= PQ_FLAGS_OFLD;
1824 case ECORE_PCI_ISCSI:
1825 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1827 case ECORE_PCI_ETH_ROCE:
1828 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1830 case ECORE_PCI_ETH_IWARP:
1831 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1834 DP_ERR(p_hwfn, "unknown personality %d\n", p_hwfn->hw_info.personality);
1842 /* Getters for resource amounts necessary for qm initialization */
1843 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1845 return p_hwfn->hw_info.num_hw_tc;
1848 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1850 return IS_ECORE_SRIOV(p_hwfn->p_dev) ? p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1853 #define NUM_DEFAULT_RLS 1
1855 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1857 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1859 /* num RLs can't exceed resource amount of rls or vports or the dcqcn qps */
1860 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1861 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_VPORT),
1862 ROCE_DCQCN_RP_MAX_QPS));
1864 /* make sure after we reserve the default and VF rls we'll have something left */
1865 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1866 if (IS_ECORE_DCQCN(p_hwfn))
1867 DP_NOTICE(p_hwfn, false, "no rate limiters left for PF rate limiting [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1871 /* subtract rls necessary for VFs and one default one for the PF */
1872 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1877 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1879 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1881 /* all pqs share the same vport (hence the 1 below), except for vfs and pf_rl pqs */
1882 return (!!(PQ_FLAGS_RLS & pq_flags)) * ecore_init_qm_get_num_pf_rls(p_hwfn) +
1883 (!!(PQ_FLAGS_VFS & pq_flags)) * ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1886 /* calc amount of PQs according to the requested flags */
1887 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1889 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1891 return (!!(PQ_FLAGS_RLS & pq_flags)) * ecore_init_qm_get_num_pf_rls(p_hwfn) +
1892 (!!(PQ_FLAGS_MCOS & pq_flags)) * ecore_init_qm_get_num_tcs(p_hwfn) +
1893 (!!(PQ_FLAGS_LB & pq_flags)) +
1894 (!!(PQ_FLAGS_OOO & pq_flags)) +
1895 (!!(PQ_FLAGS_ACK & pq_flags)) +
1896 (!!(PQ_FLAGS_OFLD & pq_flags)) +
1897 (!!(PQ_FLAGS_LLT & pq_flags)) +
1898 (!!(PQ_FLAGS_VFS & pq_flags)) * ecore_init_qm_get_num_vfs(p_hwfn);
1901 /* initialize the top level QM params */
1902 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1904 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1907 /* pq and vport bases for this PF */
1908 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1909 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1911 /* rate limiting and weighted fair queueing are always enabled */
1912 qm_info->vport_rl_en = 1;
1913 qm_info->vport_wfq_en = 1;
1915 /* TC config is different for AH 4 port */
1916 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1918 /* in AH 4 port we have fewer TCs per port */
1919 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
1921 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and 4 otherwise */
1922 if (!qm_info->ooo_tc)
1923 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : DCBX_TCP_OOO_TC;
1926 /* initialize qm vport params */
1927 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1929 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1932 /* all vports participate in weighted fair queueing */
1933 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1934 qm_info->qm_vport_params[i].vport_wfq = 1;
1937 /* initialize qm port params */
1938 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1940 /* Initialize qm port parameters */
1941 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1943 /* indicate how ooo and high pri traffic is dealt with */
1944 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1945 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1947 for (i = 0; i < num_ports; i++) {
1948 struct init_qm_port_params *p_qm_port =
1949 &p_hwfn->qm_info.qm_port_params[i];
1951 p_qm_port->active = 1;
1952 p_qm_port->active_phys_tcs = active_phys_tcs;
1953 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
1954 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
1958 /* Reset the params which must be reset for qm init. QM init may be called as
1959 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1960 * params may be affected by the init but would simply recalculate to the same
1961 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1962 * affected as these amounts stay the same.
1964 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1966 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1968 qm_info->num_pqs = 0;
1969 qm_info->num_vports = 0;
1970 qm_info->num_pf_rls = 0;
1971 qm_info->num_vf_pqs = 0;
1972 qm_info->first_vf_pq = 0;
1973 qm_info->first_mcos_pq = 0;
1974 qm_info->first_rl_pq = 0;
1977 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1979 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1981 qm_info->num_vports++;
1983 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1984 DP_ERR(p_hwfn, "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", qm_info->num_vports, ecore_init_qm_get_num_vports(p_hwfn));
1987 /* initialize a single pq and manage qm_info resources accounting.
1988 * The pq_init_flags param determines whether the PQ is rate limited (for VF or PF)
1989 * and whether a new vport is allocated to the pq or not (i.e. vport will be shared)
1992 /* flags for pq init */
1993 #define PQ_INIT_SHARE_VPORT (1 << 0)
1994 #define PQ_INIT_PF_RL (1 << 1)
1995 #define PQ_INIT_VF_RL (1 << 2)
1997 /* defines for pq init */
1998 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1999 #define PQ_INIT_DEFAULT_TC 0
2000 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
2002 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
2003 struct ecore_qm_info *qm_info,
2004 u8 tc, u32 pq_init_flags)
2006 u16 pq_idx = qm_info->num_pqs, max_pq = ecore_init_qm_get_num_pqs(p_hwfn);
2008 if (pq_idx > max_pq)
2009 DP_ERR(p_hwfn, "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
2011 /* init pq params */
2012 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + qm_info->num_vports;
2013 qm_info->qm_pq_params[pq_idx].tc_id = tc;
2014 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
2015 qm_info->qm_pq_params[pq_idx].rl_valid =
2016 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
2018 /* qm params accounting */
2020 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
2021 qm_info->num_vports++;
2023 if (pq_init_flags & PQ_INIT_PF_RL)
2024 qm_info->num_pf_rls++;
2026 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
2027 DP_ERR(p_hwfn, "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", qm_info->num_vports, ecore_init_qm_get_num_vports(p_hwfn));
2029 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
2030 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", qm_info->num_pf_rls, ecore_init_qm_get_num_pf_rls(p_hwfn));
2033 /* get pq index according to PQ_FLAGS */
2034 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
2037 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2039 /* Can't have multiple flags set here */
2040 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
2045 return &qm_info->first_rl_pq;
2047 return &qm_info->first_mcos_pq;
2049 return &qm_info->pure_lb_pq;
2051 return &qm_info->ooo_pq;
2053 return &qm_info->pure_ack_pq;
2055 return &qm_info->offload_pq;
2057 return &qm_info->low_latency_pq;
2059 return &qm_info->first_vf_pq;
2065 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
2069 /* save pq index in qm info */
2070 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
2071 u32 pq_flags, u16 pq_val)
2073 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2075 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
2078 /* get tx pq index, with the PQ TX base already set (ready for context init) */
2079 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
2081 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2083 return *base_pq_idx + CM_TX_PQ_BASE;
2086 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2088 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2091 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2093 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
2096 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2098 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2101 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2103 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
2106 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
2108 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2111 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
2113 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
2116 /* Functions for creating specific types of pqs */
2117 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2119 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2121 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2124 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2125 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2128 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2130 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2132 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2135 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2136 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2139 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2141 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2143 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2146 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2147 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2150 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2152 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2154 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2157 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2158 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2161 static void ecore_init_qm_low_latency_pq(struct ecore_hwfn *p_hwfn)
2163 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2165 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
2168 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
2169 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2172 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2174 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2177 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2180 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2181 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2182 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2185 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2187 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2188 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2190 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2193 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2194 qm_info->num_vf_pqs = num_vfs;
2195 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2196 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
2199 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2201 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2202 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2204 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2207 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2208 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2209 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
2212 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2214 /* rate limited pqs, must come first (FW assumption) */
2215 ecore_init_qm_rl_pqs(p_hwfn);
2217 /* pqs for multi cos */
2218 ecore_init_qm_mcos_pqs(p_hwfn);
2220 /* pure loopback pq */
2221 ecore_init_qm_lb_pq(p_hwfn);
2223 /* out of order pq */
2224 ecore_init_qm_ooo_pq(p_hwfn);
2227 ecore_init_qm_pure_ack_pq(p_hwfn);
2229 /* pq for offloaded protocol */
2230 ecore_init_qm_offload_pq(p_hwfn);
2232 /* low latency pq */
2233 ecore_init_qm_low_latency_pq(p_hwfn);
2235 /* done sharing vports */
2236 ecore_init_qm_advance_vport(p_hwfn);
2239 ecore_init_qm_vf_pqs(p_hwfn);
2242 /* compare values of getters against resources amounts */
2243 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2245 if (ecore_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, ECORE_VPORT)) {
2246 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2250 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2251 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2255 return ECORE_SUCCESS;
2259 * Function for verbose printing of the qm initialization results
2261 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2263 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2264 struct init_qm_vport_params *vport;
2265 struct init_qm_port_params *port;
2266 struct init_qm_pq_params *pq;
2269 /* top level params */
2270 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2271 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq, qm_info->offload_pq, qm_info->pure_ack_pq);
2272 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2273 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs, qm_info->num_vf_pqs, qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2274 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2275 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en, qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl, qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2278 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2279 port = &(qm_info->qm_port_params[i]);
2280 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2281 i, port->active, port->active_phys_tcs, port->num_pbf_cmd_lines, port->num_btb_blocks, port->reserved);
2285 for (i = 0; i < qm_info->num_vports; i++) {
2286 vport = &(qm_info->qm_vport_params[i]);
2287 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
2288 qm_info->start_vport + i, vport->vport_rl, vport->vport_wfq);
2289 for (tc = 0; tc < NUM_OF_TCS; tc++)
2290 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ", vport->first_tx_pq_id[tc]);
2291 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2295 for (i = 0; i < qm_info->num_pqs; i++) {
2296 pq = &(qm_info->qm_pq_params[i]);
2297 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
2298 qm_info->start_pq + i, pq->vport_id, pq->tc_id, pq->wrr_group, pq->rl_valid);
2302 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2304 /* reset params required for init run */
2305 ecore_init_qm_reset_params(p_hwfn);
2307 /* init QM top level params */
2308 ecore_init_qm_params(p_hwfn);
2310 /* init QM port params */
2311 ecore_init_qm_port_params(p_hwfn);
2313 /* init QM vport params */
2314 ecore_init_qm_vport_params(p_hwfn);
2316 /* init QM physical queue params */
2317 ecore_init_qm_pq_params(p_hwfn);
2319 /* display all that init */
2320 ecore_dp_init_qm_params(p_hwfn);
2323 /* This function reconfigures the QM pf on the fly.
2324 * For this purpose we:
2325 * 1. reconfigure the QM database
2326 * 2. set new values to runtime array
2327 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2328 * 4. activate init tool in QM_PF stage
2329 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2331 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2332 struct ecore_ptt *p_ptt)
2334 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2336 enum _ecore_status_t rc;
2338 /* initialize ecore's qm data structure */
2339 ecore_init_qm_info(p_hwfn);
2341 /* stop PF's qm queues */
2342 OSAL_SPIN_LOCK(&qm_lock);
2343 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2344 qm_info->start_pq, qm_info->num_pqs);
2345 OSAL_SPIN_UNLOCK(&qm_lock);
2349 /* clear the QM_PF runtime phase leftovers from previous init */
2350 ecore_init_clear_rt_data(p_hwfn);
2352 /* prepare QM portion of runtime array */
2353 ecore_qm_init_pf(p_hwfn, p_ptt, false);
2355 /* activate init tool on runtime array */
2356 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2357 p_hwfn->hw_info.hw_mode);
2358 if (rc != ECORE_SUCCESS)
2361 /* start PF's qm queues */
2362 OSAL_SPIN_LOCK(&qm_lock);
2363 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2364 qm_info->start_pq, qm_info->num_pqs);
2365 OSAL_SPIN_UNLOCK(&qm_lock);
2369 return ECORE_SUCCESS;
2372 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2374 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2375 enum _ecore_status_t rc;
2377 rc = ecore_init_qm_sanity(p_hwfn);
2378 if (rc != ECORE_SUCCESS)
2381 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2382 sizeof(struct init_qm_pq_params) *
2383 ecore_init_qm_get_num_pqs(p_hwfn));
2384 if (!qm_info->qm_pq_params)
2387 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2388 sizeof(struct init_qm_vport_params) *
2389 ecore_init_qm_get_num_vports(p_hwfn));
2390 if (!qm_info->qm_vport_params)
2393 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2394 sizeof(struct init_qm_port_params) *
2395 p_hwfn->p_dev->num_ports_in_engine);
2396 if (!qm_info->qm_port_params)
2399 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2400 sizeof(struct ecore_wfq_data) *
2401 ecore_init_qm_get_num_vports(p_hwfn));
2402 if (!qm_info->wfq_data)
2405 return ECORE_SUCCESS;
2408 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2409 ecore_qm_info_free(p_hwfn);
2412 /******************** End QM initialization ***************/
2414 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2416 u32 rdma_tasks, excess_tasks;
2418 enum _ecore_status_t rc = ECORE_SUCCESS;
2422 for_each_hwfn(p_dev, i) {
2423 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2424 if (rc != ECORE_SUCCESS)
2430 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2431 sizeof(*p_dev->fw_data));
2432 if (!p_dev->fw_data)
2435 for_each_hwfn(p_dev, i) {
2436 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2437 u32 n_eqes, num_cons;
2439 /* initialize the doorbell recovery mechanism */
2440 rc = ecore_db_recovery_setup(p_hwfn);
2444 /* First allocate the context manager structure */
2445 rc = ecore_cxt_mngr_alloc(p_hwfn);
2449 /* Set the HW cid/tid numbers (in the context manager)
2450 * Must be done prior to any further computations.
2452 rc = ecore_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2456 rc = ecore_alloc_qm_data(p_hwfn);
2461 ecore_init_qm_info(p_hwfn);
2463 /* Compute the ILT client partition */
2464 rc = ecore_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2466 DP_NOTICE(p_hwfn, false, "too many ILT lines; re-computing with less lines\n");
2467 /* In case there are not enough ILT lines we reduce the
2468 * number of RDMA tasks and re-compute.
2470 excess_tasks = ecore_cxt_cfg_ilt_compute_excess(
2471 p_hwfn, line_count);
2475 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2476 rc = ecore_cxt_set_pf_params(p_hwfn, rdma_tasks);
2480 rc = ecore_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2482 DP_ERR(p_hwfn, "failed ILT compute. Requested too many lines: %u\n",
2489 /* CID map / ILT shadow table / T2
2490 * The talbes sizes are determined by the computations above
2492 rc = ecore_cxt_tables_alloc(p_hwfn);
2496 /* SPQ, must follow ILT because initializes SPQ context */
2497 rc = ecore_spq_alloc(p_hwfn);
2501 /* SP status block allocation */
2502 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2505 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2509 rc = ecore_iov_alloc(p_hwfn);
2514 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2515 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2516 u32 n_srq = ecore_cxt_get_total_srq_count(p_hwfn);
2518 /* Calculate the EQ size
2519 * ---------------------
2520 * Each ICID may generate up to one event at a time i.e.
2521 * the event must be handled/cleared before a new one
2522 * can be generated. We calculate the sum of events per
2523 * protocol and create an EQ deep enough to handle the
2525 * - Core - according to SPQ.
2526 * - RoCE - per QP there are a couple of ICIDs, one
2527 * responder and one requester, each can
2528 * generate max 2 EQE (err+qp_destroyed) =>
2529 * n_eqes_qp = 4 * n_qp.
2530 * Each CQ can generate an EQE. There are 2 CQs
2531 * per QP => n_eqes_cq = 2 * n_qp.
2532 * Hence the RoCE total is 6 * n_qp or
2534 * On top of that one eqe shoule be added for
2535 * each XRC SRQ and SRQ.
2536 * - iWARP - can generate three async per QP (error
2537 * detected and qp in error) and an
2538 additional error per CQ. 4* num_cons.
2539 On top of that one eqe shoule be added for
2540 * each SRQ and XRC SRQ.
2541 * - ENet - There can be up to two events per VF. One
2542 * for VF-PF channel and another for VF FLR
2543 * initial cleanup. The number of VFs is
2544 * bounded by MAX_NUM_VFS_BB, and is much
2545 * smaller than RoCE's so we avoid exact
2548 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
2549 num_cons = ecore_cxt_get_proto_cid_count(
2550 p_hwfn, PROTOCOLID_ROCE, OSAL_NULL);
2553 num_cons = ecore_cxt_get_proto_cid_count(
2554 p_hwfn, PROTOCOLID_IWARP,
2558 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2559 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2560 num_cons = ecore_cxt_get_proto_cid_count(
2561 p_hwfn, PROTOCOLID_ISCSI, OSAL_NULL);
2562 n_eqes += 2 * num_cons;
2565 if (n_eqes > 0xFF00) {
2566 DP_ERR(p_hwfn, "EQs maxing out at 0xFF00 elements\n");
2570 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2574 rc = ecore_consq_alloc(p_hwfn);
2578 rc = ecore_l2_alloc(p_hwfn);
2579 if (rc != ECORE_SUCCESS)
2582 #ifdef CONFIG_ECORE_LL2
2583 if (p_hwfn->using_ll2) {
2584 rc = ecore_ll2_alloc(p_hwfn);
2589 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2590 rc = ecore_fcoe_alloc(p_hwfn);
2595 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2596 rc = ecore_iscsi_alloc(p_hwfn);
2600 rc = ecore_ooo_alloc(p_hwfn);
2604 #ifdef CONFIG_ECORE_ROCE
2605 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2606 rc = ecore_rdma_info_alloc(p_hwfn);
2612 /* DMA info initialization */
2613 rc = ecore_dmae_info_alloc(p_hwfn);
2615 DP_NOTICE(p_hwfn, false,
2616 "Failed to allocate memory for dmae_info structure\n");
2620 /* DCBX initialization */
2621 rc = ecore_dcbx_info_alloc(p_hwfn);
2623 DP_NOTICE(p_hwfn, false,
2624 "Failed to allocate memory for dcbx structure\n");
2629 rc = ecore_llh_alloc(p_dev);
2630 if (rc != ECORE_SUCCESS) {
2631 DP_NOTICE(p_dev, false,
2632 "Failed to allocate memory for the llh_info structure\n");
2636 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2637 sizeof(*p_dev->reset_stats));
2638 if (!p_dev->reset_stats) {
2639 DP_NOTICE(p_dev, false,
2640 "Failed to allocate reset statistics\n");
2644 return ECORE_SUCCESS;
2649 ecore_resc_free(p_dev);
2653 void ecore_resc_setup(struct ecore_dev *p_dev)
2658 for_each_hwfn(p_dev, i)
2659 ecore_l2_setup(&p_dev->hwfns[i]);
2663 for_each_hwfn(p_dev, i) {
2664 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2666 ecore_cxt_mngr_setup(p_hwfn);
2667 ecore_spq_setup(p_hwfn);
2668 ecore_eq_setup(p_hwfn);
2669 ecore_consq_setup(p_hwfn);
2671 /* Read shadow of current MFW mailbox */
2672 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2673 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2674 p_hwfn->mcp_info->mfw_mb_cur,
2675 p_hwfn->mcp_info->mfw_mb_length);
2677 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2679 ecore_l2_setup(p_hwfn);
2680 ecore_iov_setup(p_hwfn);
2681 #ifdef CONFIG_ECORE_LL2
2682 if (p_hwfn->using_ll2)
2683 ecore_ll2_setup(p_hwfn);
2685 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
2686 ecore_fcoe_setup(p_hwfn);
2688 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2689 ecore_iscsi_setup(p_hwfn);
2690 ecore_ooo_setup(p_hwfn);
2695 #define FINAL_CLEANUP_POLL_CNT (100)
2696 #define FINAL_CLEANUP_POLL_TIME (10)
2697 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2698 struct ecore_ptt *p_ptt,
2701 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2702 enum _ecore_status_t rc = ECORE_TIMEOUT;
2705 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2706 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2707 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2708 return ECORE_SUCCESS;
2712 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2713 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2718 command |= X_FINAL_CLEANUP_AGG_INT <<
2719 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2720 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2721 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2722 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2724 /* Make sure notification is not set before initiating final cleanup */
2725 if (REG_RD(p_hwfn, addr)) {
2726 DP_NOTICE(p_hwfn, false,
2727 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2728 REG_WR(p_hwfn, addr, 0);
2731 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2732 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2735 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2737 /* Poll until completion */
2738 while (!REG_RD(p_hwfn, addr) && count--)
2739 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2741 if (REG_RD(p_hwfn, addr))
2744 DP_NOTICE(p_hwfn, true, "Failed to receive FW final cleanup notification\n");
2746 /* Cleanup afterwards */
2747 REG_WR(p_hwfn, addr, 0);
2752 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2756 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
2757 hw_mode |= 1 << MODE_BB;
2758 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2759 hw_mode |= 1 << MODE_K2;
2760 } else if (ECORE_IS_E5(p_hwfn->p_dev)) {
2761 hw_mode |= 1 << MODE_E5;
2763 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2764 p_hwfn->p_dev->type);
2768 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE*/
2769 switch (p_hwfn->p_dev->num_ports_in_engine) {
2771 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2774 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2777 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2780 DP_NOTICE(p_hwfn, true, "num_ports_in_engine = %d not supported\n",
2781 p_hwfn->p_dev->num_ports_in_engine);
2785 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
2786 &p_hwfn->p_dev->mf_bits))
2787 hw_mode |= 1 << MODE_MF_SD;
2789 hw_mode |= 1 << MODE_MF_SI;
2792 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2793 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2794 hw_mode |= 1 << MODE_FPGA;
2796 if (p_hwfn->p_dev->b_is_emul_full)
2797 hw_mode |= 1 << MODE_EMUL_FULL;
2799 hw_mode |= 1 << MODE_EMUL_REDUCED;
2803 hw_mode |= 1 << MODE_ASIC;
2805 if (ECORE_IS_CMT(p_hwfn->p_dev))
2806 hw_mode |= 1 << MODE_100G;
2808 p_hwfn->hw_info.hw_mode = hw_mode;
2810 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2811 "Configuring function for hw_mode: 0x%08x\n",
2812 p_hwfn->hw_info.hw_mode);
2814 return ECORE_SUCCESS;
2818 /* MFW-replacement initializations for non-ASIC */
2819 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
2820 struct ecore_ptt *p_ptt)
2822 struct ecore_dev *p_dev = p_hwfn->p_dev;
2826 if (CHIP_REV_IS_EMUL(p_dev)) {
2827 if (ECORE_IS_AH(p_dev))
2829 else if (ECORE_IS_E5(p_dev))
2830 ECORE_E5_MISSING_CODE;
2833 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2835 if (CHIP_REV_IS_EMUL(p_dev) &&
2836 (ECORE_IS_AH(p_dev) || ECORE_IS_E5(p_dev)))
2837 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
2840 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2841 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
2842 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
2843 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2845 if (CHIP_REV_IS_EMUL(p_dev)) {
2846 if (ECORE_IS_AH(p_dev)) {
2847 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2848 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2849 (p_dev->num_ports_in_engine >> 1));
2851 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2852 p_dev->num_ports_in_engine == 4 ? 0 : 3);
2853 } else if (ECORE_IS_E5(p_dev)) {
2854 ECORE_E5_MISSING_CODE;
2858 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2859 for (i = 0; i < 100; i++) {
2861 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2865 DP_NOTICE(p_hwfn, true,
2866 "RBC done failed to complete in PSWRQ2\n");
2869 return ECORE_SUCCESS;
2873 /* Init run time data for all PFs and their VFs on an engine.
2874 * TBD - for VFs - Once we have parent PF info for each VF in
2875 * shmem available as CAU requires knowledge of parent PF for each VF.
2877 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2879 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2882 for_each_hwfn(p_dev, i) {
2883 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2884 struct ecore_igu_info *p_igu_info;
2885 struct ecore_igu_block *p_block;
2886 struct cau_sb_entry sb_entry;
2888 p_igu_info = p_hwfn->hw_info.p_igu_info;
2891 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2893 p_block = &p_igu_info->entry[igu_sb_id];
2895 if (!p_block->is_pf)
2898 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2899 p_block->function_id,
2901 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2907 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2908 struct ecore_ptt *p_ptt)
2910 u32 val, wr_mbs, cache_line_size;
2912 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2925 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2930 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2931 switch (cache_line_size) {
2946 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2950 if (OSAL_CACHE_LINE_SIZE > wr_mbs)
2952 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2953 OSAL_CACHE_LINE_SIZE, wr_mbs);
2955 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2957 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2958 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2962 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2963 struct ecore_ptt *p_ptt,
2966 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2967 struct ecore_dev *p_dev = p_hwfn->p_dev;
2968 u8 vf_id, max_num_vfs;
2971 enum _ecore_status_t rc = ECORE_SUCCESS;
2973 ecore_init_cau_rt_data(p_dev);
2975 /* Program GTT windows */
2976 ecore_gtt_init(p_hwfn, p_ptt);
2979 if (CHIP_REV_IS_EMUL(p_dev)) {
2980 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
2981 if (rc != ECORE_SUCCESS)
2986 if (p_hwfn->mcp_info) {
2987 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2988 qm_info->pf_rl_en = 1;
2989 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2990 qm_info->pf_wfq_en = 1;
2993 ecore_qm_common_rt_init(p_hwfn,
2994 p_dev->num_ports_in_engine,
2995 qm_info->max_phys_tcs_per_port,
2996 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2997 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2998 qm_info->qm_port_params);
3000 ecore_cxt_hw_init_common(p_hwfn);
3002 ecore_init_cache_line_size(p_hwfn, p_ptt);
3004 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
3006 if (rc != ECORE_SUCCESS)
3009 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
3010 * need to decide with which value, maybe runtime
3012 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
3013 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
3015 if (ECORE_IS_BB(p_dev)) {
3016 /* Workaround clears ROCE search for all functions to prevent
3017 * involving non initialized function in processing ROCE packet.
3019 num_pfs = NUM_OF_ENG_PFS(p_dev);
3020 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
3021 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
3022 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3023 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3025 /* pretend to original PF */
3026 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
3029 /* Workaround for avoiding CCFC execution error when getting packets
3030 * with CRC errors, and allowing instead the invoking of the FW error
3032 * This is not done inside the init tool since it currently can't
3033 * perform a pretending to VFs.
3035 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
3036 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
3037 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
3038 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
3039 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
3040 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
3041 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
3042 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
3044 /* pretend to original PF */
3045 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
3051 #define MISC_REG_RESET_REG_2_XMAC_BIT (1<<4)
3052 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1<<5)
3054 #define PMEG_IF_BYTE_COUNT 8
3056 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
3057 struct ecore_ptt *p_ptt,
3063 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3064 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
3065 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
3066 (8 << PMEG_IF_BYTE_COUNT),
3067 (reg_type << 25) | (addr << 8) | port,
3068 (u32)((data >> 32) & 0xffffffff),
3069 (u32)(data & 0xffffffff));
3071 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
3072 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
3074 (8 << PMEG_IF_BYTE_COUNT));
3075 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
3076 (reg_type << 25) | (addr << 8) | port);
3077 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
3078 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
3079 (data >> 32) & 0xffffffff);
3082 #define XLPORT_MODE_REG (0x20a)
3083 #define XLPORT_MAC_CONTROL (0x210)
3084 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
3085 #define XLPORT_ENABLE_REG (0x20b)
3087 #define XLMAC_CTRL (0x600)
3088 #define XLMAC_MODE (0x601)
3089 #define XLMAC_RX_MAX_SIZE (0x608)
3090 #define XLMAC_TX_CTRL (0x604)
3091 #define XLMAC_PAUSE_CTRL (0x60d)
3092 #define XLMAC_PFC_CTRL (0x60e)
3094 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
3095 struct ecore_ptt *p_ptt)
3097 u8 loopback = 0, port = p_hwfn->port_id * 2;
3099 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
3101 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG,
3102 (0x4 << 4) | 0x4, 1, port); /* XLPORT MAC MODE */ /* 0 Quad, 4 Single... */
3103 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
3104 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3105 0x40, 0, port); /*XLMAC: SOFT RESET */
3106 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE,
3107 0x40, 0, port); /*XLMAC: Port Speed >= 10Gbps */
3108 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE,
3109 0x3fff, 0, port); /* XLMAC: Max Size */
3110 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3111 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3113 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL,
3115 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3116 0x30ffffc000ULL, 0, port);
3117 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2),
3118 0, port); /* XLMAC: TX_EN, RX_EN */
3119 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
3120 0, port); /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3121 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG,
3122 1, 0, port); /* Enabled Parallel PFC interface */
3123 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG,
3124 0xf, 1, port); /* XLPORT port enable */
3127 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
3128 struct ecore_ptt *p_ptt)
3130 u8 port = p_hwfn->port_id;
3131 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
3133 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
3135 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
3136 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
3138 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
3139 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
3141 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
3142 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
3144 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
3145 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
3147 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
3148 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
3150 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
3151 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
3153 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
3155 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
3157 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
3159 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
3163 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3164 struct ecore_ptt *p_ptt)
3166 if (ECORE_IS_AH(p_hwfn->p_dev) || ECORE_IS_E5(p_hwfn->p_dev))
3167 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
3169 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3174 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3175 struct ecore_ptt *p_ptt, u8 port)
3177 int port_offset = port ? 0x800 : 0;
3178 u32 xmac_rxctrl = 0;
3181 /* FIXME: move to common start */
3182 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2*sizeof(u32),
3183 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
3185 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3186 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
3188 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3190 /* Set the number of ports on the Warp Core to 10G */
3191 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3193 /* Soft reset of XMAC */
3194 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3195 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3197 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3198 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3200 /* FIXME: move to common end */
3201 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3202 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3204 /* Set Max packet size: initialize XMAC block register for port 0 */
3205 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3207 /* CRC append for Tx packets: init XMAC block register for port 1 */
3208 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3210 /* Enable TX and RX: initialize XMAC block register for port 1 */
3211 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3212 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3213 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3214 XMAC_REG_RX_CTRL_BB + port_offset);
3215 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3216 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3220 static enum _ecore_status_t
3221 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3222 struct ecore_ptt *p_ptt,
3223 u32 pwm_region_size,
3226 u32 dpi_bit_shift, dpi_count, dpi_page_size;
3230 /* Calculate DPI size
3231 * ------------------
3232 * The PWM region contains Doorbell Pages. The first is reserverd for
3233 * the kernel for, e.g, L2. The others are free to be used by non-
3234 * trusted applications, typically from user space. Each page, called a
3235 * doorbell page is sectioned into windows that allow doorbells to be
3236 * issued in parallel by the kernel/application. The size of such a
3237 * window (a.k.a. WID) is 1kB.
3239 * 1kB WID x N WIDS = DPI page size
3240 * DPI page size x N DPIs = PWM region size
3242 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3243 * in order to ensure that two applications won't share the same page.
3244 * It also must contain at least one WID per CPU to allow parallelism.
3245 * It also must be a power of 2, since it is stored as a bit shift.
3247 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3248 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3249 * containing 4 WIDs.
3251 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3252 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3253 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) & ~(OSAL_PAGE_SIZE - 1);
3254 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3255 dpi_count = pwm_region_size / dpi_page_size;
3257 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3258 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3261 p_hwfn->dpi_size = dpi_page_size;
3262 p_hwfn->dpi_count = dpi_count;
3264 /* Update registers */
3265 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3267 if (dpi_count < min_dpis)
3268 return ECORE_NORESOURCES;
3270 return ECORE_SUCCESS;
3273 enum ECORE_ROCE_EDPM_MODE {
3274 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3275 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3276 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3279 static enum _ecore_status_t
3280 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3281 struct ecore_ptt *p_ptt)
3283 struct ecore_rdma_pf_params *p_rdma_pf_params;
3284 u32 pwm_regsize, norm_regsize;
3285 u32 non_pwm_conn, min_addr_reg1;
3286 u32 db_bar_size, n_cpus = 1;
3289 enum _ecore_status_t rc = ECORE_SUCCESS;
3292 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3293 if (ECORE_IS_CMT(p_hwfn->p_dev))
3296 /* Calculate doorbell regions
3297 * -----------------------------------
3298 * The doorbell BAR is made of two regions. The first is called normal
3299 * region and the second is called PWM region. In the normal region
3300 * each ICID has its own set of addresses so that writing to that
3301 * specific address identifies the ICID. In the Process Window Mode
3302 * region the ICID is given in the data written to the doorbell. The
3303 * above per PF register denotes the offset in the doorbell BAR in which
3304 * the PWM region begins.
3305 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3306 * non-PWM connection. The calculation below computes the total non-PWM
3307 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3308 * in units of 4,096 bytes.
3310 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3311 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3313 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
3315 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, OSAL_PAGE_SIZE);
3316 min_addr_reg1 = norm_regsize / 4096;
3317 pwm_regsize = db_bar_size - norm_regsize;
3319 /* Check that the normal and PWM sizes are valid */
3320 if (db_bar_size < norm_regsize) {
3321 DP_ERR(p_hwfn->p_dev,
3322 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3323 db_bar_size, norm_regsize);
3324 return ECORE_NORESOURCES;
3326 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3327 DP_ERR(p_hwfn->p_dev,
3328 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3329 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3331 return ECORE_NORESOURCES;
3334 p_rdma_pf_params = &p_hwfn->pf_params.rdma_pf_params;
3336 /* Calculate number of DPIs */
3337 if (ECORE_IS_IWARP_PERSONALITY(p_hwfn))
3338 p_rdma_pf_params->roce_edpm_mode = ECORE_ROCE_EDPM_MODE_DISABLE;
3340 if (p_rdma_pf_params->roce_edpm_mode <= ECORE_ROCE_EDPM_MODE_DISABLE) {
3341 roce_edpm_mode = p_rdma_pf_params->roce_edpm_mode;
3343 DP_ERR(p_hwfn->p_dev,
3344 "roce edpm mode was configured to an illegal value of %u. Resetting it to 0-Enable EDPM if BAR size is adequate\n",
3345 p_rdma_pf_params->roce_edpm_mode);
3349 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3350 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3351 /* Either EDPM is mandatory, or we are attempting to allocate a
3354 n_cpus = OSAL_NUM_CPUS();
3355 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3358 cond = ((rc != ECORE_SUCCESS) &&
3359 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3360 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3361 if (cond || p_hwfn->dcbx_no_edpm) {
3362 /* Either EDPM is disabled from user configuration, or it is
3363 * disabled via DCBx, or it is not mandatory and we failed to
3364 * allocated a WID per CPU.
3367 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3369 #ifdef CONFIG_ECORE_ROCE
3370 /* If we entered this flow due to DCBX then the DPM register is
3371 * already configured.
3374 ecore_rdma_dpm_bar(p_hwfn, p_ptt);
3378 p_hwfn->wid_count = (u16)n_cpus;
3380 /* Check return codes from above calls */
3381 if (rc != ECORE_SUCCESS) {
3382 #ifndef LINUX_REMOVE
3384 "Failed to allocate enough DPIs. Allocated %d but the current minimum is set to %d. You can reduce this minimum down to %d via user configuration min_dpis or by disabling EDPM via user configuration roce_edpm_mode\n",
3385 p_hwfn->dpi_count, p_rdma_pf_params->min_dpis,
3389 "Failed to allocate enough DPIs. Allocated %d but the current minimum is set to %d. You can reduce this minimum down to %d via the module parameter min_rdma_dpis or by disabling EDPM by setting the module parameter roce_edpm to 2\n",
3390 p_hwfn->dpi_count, p_rdma_pf_params->min_dpis,
3394 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
3395 norm_regsize, pwm_regsize, p_hwfn->dpi_size,
3397 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
3398 "disabled" : "enabled", (unsigned long)OSAL_PAGE_SIZE);
3400 return ECORE_NORESOURCES;
3404 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
3405 norm_regsize, pwm_regsize, p_hwfn->dpi_size, p_hwfn->dpi_count,
3406 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
3407 "disabled" : "enabled", (unsigned long)OSAL_PAGE_SIZE);
3410 p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
3411 * calculate the doorbell
3415 /* Update registers */
3416 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3417 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3418 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3419 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3421 return ECORE_SUCCESS;
3424 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3425 struct ecore_ptt *p_ptt,
3428 enum _ecore_status_t rc = ECORE_SUCCESS;
3430 /* In CMT the gate should be cleared by the 2nd hwfn */
3431 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
3432 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3434 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3436 if (rc != ECORE_SUCCESS)
3439 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3442 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
3443 return ECORE_SUCCESS;
3445 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
3446 if (ECORE_IS_AH(p_hwfn->p_dev))
3447 return ECORE_SUCCESS;
3448 else if (ECORE_IS_BB(p_hwfn->p_dev))
3449 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3451 ECORE_E5_MISSING_CODE;
3452 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3453 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
3454 /* Activate OPTE in CMT */
3457 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3459 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3460 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3461 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3462 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3463 ecore_wr(p_hwfn, p_ptt,
3464 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3465 ecore_wr(p_hwfn, p_ptt,
3466 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3467 ecore_wr(p_hwfn, p_ptt,
3468 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3472 ecore_emul_link_init(p_hwfn, p_ptt);
3474 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
3481 static enum _ecore_status_t
3482 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3483 int hw_mode, struct ecore_hw_init_params *p_params)
3485 u8 rel_pf_id = p_hwfn->rel_pf_id;
3487 enum _ecore_status_t rc = ECORE_SUCCESS;
3491 if (p_hwfn->mcp_info) {
3492 struct ecore_mcp_function_info *p_info;
3494 p_info = &p_hwfn->mcp_info->func_info;
3495 if (p_info->bandwidth_min)
3496 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3498 /* Update rate limit once we'll actually have a link */
3499 p_hwfn->qm_info.pf_rl = 100000;
3501 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3503 ecore_int_igu_init_rt(p_hwfn);
3505 /* Set VLAN in NIG if needed */
3506 if (hw_mode & (1 << MODE_MF_SD)) {
3507 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3508 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3509 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3510 p_hwfn->hw_info.ovlan);
3512 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3513 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3514 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3518 /* Enable classification by MAC if needed */
3519 if (hw_mode & (1 << MODE_MF_SI)) {
3520 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring TAGMAC_CLS_TYPE\n");
3521 STORE_RT_REG(p_hwfn,
3522 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
3525 /* Protocl Configuration - @@@TBD - should we set 0 otherwise?*/
3526 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3527 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3528 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3529 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3530 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3532 /* perform debug configuration when chip is out of reset */
3533 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3535 /* Sanity check before the PF init sequence that uses DMAE */
3536 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3540 /* PF Init sequence */
3541 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3545 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3546 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3550 /* Pure runtime initializations - directly to the HW */
3551 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3553 /* PCI relaxed ordering is generally beneficial for performance,
3554 * but can hurt performance or lead to instability on some setups.
3555 * If management FW is taking care of it go with that, otherwise
3556 * disable to be on the safe side.
3558 pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3560 DP_NOTICE(p_hwfn, true,
3561 "Failed to find the PCI Express Capability structure in the PCI config space\n");
3565 OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3567 if (p_params->pci_rlx_odr_mode == ECORE_ENABLE_RLX_ODR) {
3568 ctrl |= PCI_EXP_DEVCTL_RELAX_EN;
3569 OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev,
3570 pos + PCI_EXP_DEVCTL, ctrl);
3571 } else if (p_params->pci_rlx_odr_mode == ECORE_DISABLE_RLX_ODR) {
3572 ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3573 OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev,
3574 pos + PCI_EXP_DEVCTL, ctrl);
3575 } else if (ecore_mcp_rlx_odr_supported(p_hwfn)) {
3576 DP_INFO(p_hwfn, "PCI relax ordering configured by MFW\n");
3578 ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3579 OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev,
3580 pos + PCI_EXP_DEVCTL, ctrl);
3583 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3584 if (rc != ECORE_SUCCESS)
3587 /* Use the leading hwfn since in CMT only NIG #0 is operational */
3588 if (IS_LEAD_HWFN(p_hwfn)) {
3589 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3590 p_params->avoid_eng_affin);
3591 if (rc != ECORE_SUCCESS)
3595 if (p_params->b_hw_start) {
3596 /* enable interrupts */
3597 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3598 if (rc != ECORE_SUCCESS)
3601 /* send function start command */
3602 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3603 p_params->allow_npar_tx_switch);
3605 DP_NOTICE(p_hwfn, true, "Function start ramrod failed\n");
3608 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3609 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3610 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3612 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
3614 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3616 ecore_wr(p_hwfn, p_ptt,
3617 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3620 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3621 "PRS_REG_SEARCH registers after start PFn\n");
3622 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3623 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3624 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3625 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3626 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3627 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3628 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3629 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3630 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3631 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3632 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3633 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3634 prs_reg = ecore_rd(p_hwfn, p_ptt,
3635 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3636 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3637 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3639 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3640 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3641 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3643 return ECORE_SUCCESS;
3646 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3647 struct ecore_ptt *p_ptt,
3650 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3652 /* Configure the PF's internal FID_enable for master transactions */
3653 ecore_wr(p_hwfn, p_ptt,
3654 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3656 /* Wait until value is set - try for 1 second every 50us */
3657 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3658 val = ecore_rd(p_hwfn, p_ptt,
3659 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3666 if (val != set_val) {
3667 DP_NOTICE(p_hwfn, true,
3668 "PFID_ENABLE_MASTER wasn't changed after a second\n");
3669 return ECORE_UNKNOWN_ERROR;
3672 return ECORE_SUCCESS;
3675 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3676 struct ecore_ptt *p_main_ptt)
3678 /* Read shadow of current MFW mailbox */
3679 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3680 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3681 p_hwfn->mcp_info->mfw_mb_cur,
3682 p_hwfn->mcp_info->mfw_mb_length);
3685 static enum _ecore_status_t
3686 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3687 struct ecore_load_req_params *p_load_req,
3688 struct ecore_drv_load_params *p_drv_load)
3690 /* Make sure that if ecore-client didn't provide inputs, all the
3691 * expected defaults are indeed zero.
3693 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3694 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3695 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3697 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3699 if (p_drv_load == OSAL_NULL)
3702 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3703 ECORE_DRV_ROLE_KDUMP :
3705 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3706 p_load_req->override_force_load = p_drv_load->override_force_load;
3708 /* Old MFW versions don't support timeout values other than default and
3709 * none, so these values are replaced according to the fall-back action.
3712 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3713 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3714 (p_hwfn->mcp_info->capabilities &
3715 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3716 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3720 switch (p_drv_load->mfw_timeout_fallback) {
3721 case ECORE_TO_FALLBACK_TO_NONE:
3722 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3724 case ECORE_TO_FALLBACK_TO_DEFAULT:
3725 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3727 case ECORE_TO_FALLBACK_FAIL_LOAD:
3728 DP_NOTICE(p_hwfn, false,
3729 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3730 p_drv_load->mfw_timeout_val,
3731 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3732 ECORE_LOAD_REQ_LOCK_TO_NONE);
3733 return ECORE_ABORTED;
3737 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3738 p_drv_load->mfw_timeout_val,
3739 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3741 p_load_req->timeout_val);
3743 return ECORE_SUCCESS;
3746 static enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3747 struct ecore_hw_init_params *p_params)
3749 if (p_params->p_tunn) {
3750 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3751 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3754 p_hwfn->b_int_enabled = 1;
3756 return ECORE_SUCCESS;
3759 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3760 struct ecore_ptt *p_ptt)
3762 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3763 1 << p_hwfn->abs_pf_id);
3766 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3767 struct ecore_hw_init_params *p_params)
3769 struct ecore_load_req_params load_req_params;
3770 u32 load_code, resp, param, drv_mb_param;
3771 bool b_default_mtu = true;
3772 struct ecore_hwfn *p_hwfn;
3773 enum _ecore_status_t rc = ECORE_SUCCESS, cancel_load;
3777 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3778 DP_NOTICE(p_dev, false,
3779 "MSI mode is not supported for CMT devices\n");
3784 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3785 if (rc != ECORE_SUCCESS)
3789 for_each_hwfn(p_dev, i) {
3790 p_hwfn = &p_dev->hwfns[i];
3792 /* If management didn't provide a default, set one of our own */
3793 if (!p_hwfn->hw_info.mtu) {
3794 p_hwfn->hw_info.mtu = 1500;
3795 b_default_mtu = false;
3799 ecore_vf_start(p_hwfn, p_params);
3803 rc = ecore_calc_hw_mode(p_hwfn);
3804 if (rc != ECORE_SUCCESS)
3807 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3809 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
3810 &p_dev->mf_bits))) {
3811 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3813 ether_type = ETH_P_8021Q;
3815 ether_type = ETH_P_8021AD;
3816 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3818 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3820 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3822 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3826 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3827 p_params->p_drv_load_params);
3828 if (rc != ECORE_SUCCESS)
3831 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3833 if (rc != ECORE_SUCCESS) {
3834 DP_NOTICE(p_hwfn, false,
3835 "Failed sending a LOAD_REQ command\n");
3839 load_code = load_req_params.load_code;
3840 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3841 "Load request was sent. Load code: 0x%x\n",
3844 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3847 * When coming back from hibernate state, the registers from
3848 * which shadow is read initially are not initialized. It turns
3849 * out that these registers get initialized during the call to
3850 * ecore_mcp_load_req request. So we need to reread them here
3851 * to get the proper shadow register value.
3852 * Note: This is a workaround for the missing MFW
3853 * initialization. It may be removed once the implementation
3856 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3858 /* Only relevant for recovery:
3859 * Clear the indication after the LOAD_REQ command is responded
3862 p_dev->recov_in_prog = false;
3864 if (!qm_lock_ref_cnt) {
3865 #ifdef CONFIG_ECORE_LOCK_ALLOC
3866 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3868 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3872 OSAL_SPIN_LOCK_INIT(&qm_lock);
3876 /* Clean up chip from previous driver if such remains exist.
3877 * This is not needed when the PF is the first one on the
3878 * engine, since afterwards we are going to init the FW.
3880 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3881 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3882 p_hwfn->rel_pf_id, false);
3883 if (rc != ECORE_SUCCESS) {
3884 ecore_hw_err_notify(p_hwfn,
3885 ECORE_HW_ERR_RAMROD_FAIL);
3890 /* Log and clear previous pglue_b errors if such exist */
3891 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
3893 /* Enable the PF's internal FID_enable in the PXP */
3894 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3896 if (rc != ECORE_SUCCESS)
3899 /* Clear the pglue_b was_error indication.
3900 * In E4 it must be done after the BME and the internal
3901 * FID_enable for the PF are set, since VDMs may cause the
3902 * indication to be set again.
3904 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3906 switch (load_code) {
3907 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3908 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3909 p_hwfn->hw_info.hw_mode);
3910 if (rc != ECORE_SUCCESS)
3913 case FW_MSG_CODE_DRV_LOAD_PORT:
3914 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3915 p_hwfn->hw_info.hw_mode);
3916 if (rc != ECORE_SUCCESS)
3919 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3920 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3921 p_hwfn->hw_info.hw_mode,
3925 DP_NOTICE(p_hwfn, false,
3926 "Unexpected load code [0x%08x]", load_code);
3931 if (rc != ECORE_SUCCESS) {
3932 DP_NOTICE(p_hwfn, false,
3933 "init phase failed for loadcode 0x%x (rc %d)\n",
3938 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3939 if (rc != ECORE_SUCCESS) {
3940 DP_NOTICE(p_hwfn, false, "Sending load done failed, rc = %d\n", rc);
3941 if (rc == ECORE_NOMEM) {
3942 DP_NOTICE(p_hwfn, false,
3943 "Sending load done was failed due to memory allocation failure\n");
3949 /* send DCBX attention request command */
3950 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3951 "sending phony dcbx set command to trigger DCBx attention handling\n");
3952 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3953 DRV_MSG_CODE_SET_DCBX,
3954 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3956 if (rc != ECORE_SUCCESS) {
3957 DP_NOTICE(p_hwfn, false,
3958 "Failed to send DCBX attention request\n");
3962 p_hwfn->hw_init_done = true;
3966 /* Get pre-negotiated values for stag, bandwidth etc. */
3967 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3968 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3969 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3970 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3971 DRV_MSG_CODE_GET_OEM_UPDATES,
3972 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3974 if (rc != ECORE_SUCCESS)
3975 DP_NOTICE(p_hwfn, false,
3976 "Failed to send GET_OEM_UPDATES attention request\n");
3980 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3981 drv_mb_param = STORM_FW_VERSION;
3982 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3983 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3984 drv_mb_param, &resp, ¶m);
3985 if (rc != ECORE_SUCCESS)
3986 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3988 if (!b_default_mtu) {
3989 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3990 p_hwfn->hw_info.mtu);
3991 if (rc != ECORE_SUCCESS)
3992 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3995 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3997 ECORE_OV_DRIVER_STATE_DISABLED);
3998 if (rc != ECORE_SUCCESS)
3999 DP_INFO(p_hwfn, "Failed to update driver state\n");
4001 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
4002 ECORE_OV_ESWITCH_VEB);
4003 if (rc != ECORE_SUCCESS)
4004 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
4011 #ifdef CONFIG_ECORE_LOCK_ALLOC
4012 if (!qm_lock_ref_cnt)
4013 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4016 /* The MFW load lock should be released also when initialization fails.
4017 * If supported, use a cancel_load request to update the MFW with the
4020 cancel_load = ecore_mcp_cancel_load_req(p_hwfn, p_hwfn->p_main_ptt);
4021 if (cancel_load == ECORE_NOTIMPL) {
4023 "Send a load done request instead of cancel load\n");
4024 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
4029 #define ECORE_HW_STOP_RETRY_LIMIT (10)
4030 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
4031 struct ecore_hwfn *p_hwfn,
4032 struct ecore_ptt *p_ptt)
4037 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
4038 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
4040 i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
4042 if ((!ecore_rd(p_hwfn, p_ptt,
4043 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
4044 (!ecore_rd(p_hwfn, p_ptt,
4045 TM_REG_PF_SCAN_ACTIVE_TASK)))
4048 /* Dependent on number of connection/tasks, possibly
4049 * 1ms sleep is required between polls
4054 if (i < ECORE_HW_STOP_RETRY_LIMIT)
4057 DP_NOTICE(p_hwfn, false,
4058 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
4059 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
4060 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
4063 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
4067 for_each_hwfn(p_dev, j) {
4068 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4069 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
4071 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4075 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
4076 struct ecore_ptt *p_ptt,
4077 u32 addr, u32 expected_val)
4079 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
4081 if (val != expected_val) {
4082 DP_NOTICE(p_hwfn, true,
4083 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
4084 addr, val, expected_val);
4085 return ECORE_UNKNOWN_ERROR;
4088 return ECORE_SUCCESS;
4091 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
4093 struct ecore_hwfn *p_hwfn;
4094 struct ecore_ptt *p_ptt;
4095 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
4098 for_each_hwfn(p_dev, j) {
4099 p_hwfn = &p_dev->hwfns[j];
4100 p_ptt = p_hwfn->p_main_ptt;
4102 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
4105 ecore_vf_pf_int_cleanup(p_hwfn);
4106 rc = ecore_vf_pf_reset(p_hwfn);
4107 if (rc != ECORE_SUCCESS) {
4108 DP_NOTICE(p_hwfn, true,
4109 "ecore_vf_pf_reset failed. rc = %d.\n",
4111 rc2 = ECORE_UNKNOWN_ERROR;
4116 /* mark the hw as uninitialized... */
4117 p_hwfn->hw_init_done = false;
4119 /* Send unload command to MCP */
4120 if (!p_dev->recov_in_prog) {
4121 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
4122 if (rc != ECORE_SUCCESS) {
4123 DP_NOTICE(p_hwfn, false,
4124 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
4126 rc2 = ECORE_UNKNOWN_ERROR;
4130 OSAL_DPC_SYNC(p_hwfn);
4132 /* After this point no MFW attentions are expected, e.g. prevent
4133 * race between pf stop and dcbx pf update.
4136 rc = ecore_sp_pf_stop(p_hwfn);
4137 if (rc != ECORE_SUCCESS) {
4138 DP_NOTICE(p_hwfn, false,
4139 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
4141 rc2 = ECORE_UNKNOWN_ERROR;
4144 /* perform debug action after PF stop was sent */
4145 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4147 /* close NIG to BRB gate */
4148 ecore_wr(p_hwfn, p_ptt,
4149 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4152 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4153 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4154 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4155 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4156 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4158 /* @@@TBD - clean transmission queues (5.b) */
4159 /* @@@TBD - clean BTB (5.c) */
4161 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4163 /* @@@TBD - verify DMAE requests are done (8) */
4165 /* Disable Attention Generation */
4166 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4167 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4168 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4169 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4170 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4171 if (rc != ECORE_SUCCESS) {
4172 DP_NOTICE(p_hwfn, true,
4173 "Failed to return IGU CAM to default\n");
4174 rc2 = ECORE_UNKNOWN_ERROR;
4177 /* Need to wait 1ms to guarantee SBs are cleared */
4180 if (!p_dev->recov_in_prog) {
4181 ecore_verify_reg_val(p_hwfn, p_ptt,
4182 QM_REG_USG_CNT_PF_TX, 0);
4183 ecore_verify_reg_val(p_hwfn, p_ptt,
4184 QM_REG_USG_CNT_PF_OTHER, 0);
4185 /* @@@TBD - assert on incorrect xCFC values (10.b) */
4188 /* Disable PF in HW blocks */
4189 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4190 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4192 if (IS_LEAD_HWFN(p_hwfn) &&
4193 OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4194 !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4195 ecore_llh_remove_mac_filter(p_dev, 0,
4196 p_hwfn->hw_info.hw_mac_addr);
4199 #ifdef CONFIG_ECORE_LOCK_ALLOC
4200 if (!qm_lock_ref_cnt)
4201 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4204 if (!p_dev->recov_in_prog) {
4205 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4206 if (rc == ECORE_NOMEM) {
4207 DP_NOTICE(p_hwfn, false,
4208 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4209 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4211 if (rc != ECORE_SUCCESS) {
4212 DP_NOTICE(p_hwfn, false,
4213 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4215 rc2 = ECORE_UNKNOWN_ERROR;
4220 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4221 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4222 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4224 /* Clear the PF's internal FID_enable in the PXP.
4225 * In CMT this should only be done for first hw-function, and
4226 * only after all transactions have stopped for all active
4229 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4231 if (rc != ECORE_SUCCESS) {
4232 DP_NOTICE(p_hwfn, true,
4233 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4235 rc2 = ECORE_UNKNOWN_ERROR;
4242 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4246 for_each_hwfn(p_dev, j) {
4247 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4248 struct ecore_ptt *p_ptt;
4251 ecore_vf_pf_int_cleanup(p_hwfn);
4254 p_ptt = ecore_ptt_acquire(p_hwfn);
4258 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Shutting down the fastpath\n");
4260 ecore_wr(p_hwfn, p_ptt,
4261 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4263 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4264 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4265 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4266 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4267 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4269 /* @@@TBD - clean transmission queues (5.b) */
4270 /* @@@TBD - clean BTB (5.c) */
4272 /* @@@TBD - verify DMAE requests are done (8) */
4274 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4275 /* Need to wait 1ms to guarantee SBs are cleared */
4277 ecore_ptt_release(p_hwfn, p_ptt);
4280 return ECORE_SUCCESS;
4283 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4285 struct ecore_ptt *p_ptt;
4287 if (IS_VF(p_hwfn->p_dev))
4288 return ECORE_SUCCESS;
4290 p_ptt = ecore_ptt_acquire(p_hwfn);
4294 /* If roce info is allocated it means roce is initialized and should
4295 * be enabled in searcher.
4297 if (p_hwfn->p_rdma_info &&
4298 p_hwfn->p_rdma_info->active &&
4299 p_hwfn->b_rdma_enabled_in_prs)
4300 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
4302 /* Re-open incoming traffic */
4303 ecore_wr(p_hwfn, p_ptt,
4304 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4305 ecore_ptt_release(p_hwfn, p_ptt);
4307 return ECORE_SUCCESS;
4310 enum _ecore_status_t ecore_set_nwuf_reg(struct ecore_dev *p_dev, u32 reg_idx,
4311 u32 pattern_size, u32 crc)
4313 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4314 enum _ecore_status_t rc = ECORE_SUCCESS;
4315 struct ecore_ptt *p_ptt;
4319 p_ptt = ecore_ptt_acquire(p_hwfn);
4323 /* Get length and CRC register offsets */
4327 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_LEN_BB :
4328 WOL_REG_ACPI_PAT_0_LEN_K2_E5;
4329 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_0_CRC_BB :
4330 WOL_REG_ACPI_PAT_0_CRC_K2_E5;
4333 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_1_LEN_BB :
4334 WOL_REG_ACPI_PAT_1_LEN_K2_E5;
4335 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_1_CRC_BB :
4336 WOL_REG_ACPI_PAT_1_CRC_K2_E5;
4339 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_2_LEN_BB :
4340 WOL_REG_ACPI_PAT_2_LEN_K2_E5;
4341 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_2_CRC_BB :
4342 WOL_REG_ACPI_PAT_2_CRC_K2_E5;
4345 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_3_LEN_BB :
4346 WOL_REG_ACPI_PAT_3_LEN_K2_E5;
4347 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_3_CRC_BB :
4348 WOL_REG_ACPI_PAT_3_CRC_K2_E5;
4351 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_4_LEN_BB :
4352 WOL_REG_ACPI_PAT_4_LEN_K2_E5;
4353 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_4_CRC_BB :
4354 WOL_REG_ACPI_PAT_4_CRC_K2_E5;
4357 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_5_LEN_BB :
4358 WOL_REG_ACPI_PAT_5_LEN_K2_E5;
4359 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_5_CRC_BB :
4360 WOL_REG_ACPI_PAT_5_CRC_K2_E5;
4363 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_6_LEN_BB :
4364 WOL_REG_ACPI_PAT_6_LEN_K2_E5;
4365 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_6_CRC_BB :
4366 WOL_REG_ACPI_PAT_6_CRC_K2_E5;
4369 reg_len = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_LEN_BB :
4370 WOL_REG_ACPI_PAT_7_LEN_K2_E5;
4371 reg_crc = ECORE_IS_BB(p_dev) ? NIG_REG_ACPI_PAT_7_CRC_BB :
4372 WOL_REG_ACPI_PAT_7_CRC_K2_E5;
4375 rc = ECORE_UNKNOWN_ERROR;
4379 /* Allign pattern size to 4 */
4380 while (pattern_size % 4)
4383 /* Write pattern length and crc value */
4384 if (ECORE_IS_BB(p_dev)) {
4385 rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, reg_len, pattern_size);
4386 if (rc != ECORE_SUCCESS) {
4387 DP_NOTICE(p_hwfn, false,
4388 "Failed to update the ACPI pattern length\n");
4392 rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, reg_crc, crc);
4393 if (rc != ECORE_SUCCESS) {
4394 DP_NOTICE(p_hwfn, false,
4395 "Failed to update the ACPI pattern crc value\n");
4399 ecore_mcp_wol_wr(p_hwfn, p_ptt, reg_len, pattern_size);
4400 ecore_mcp_wol_wr(p_hwfn, p_ptt, reg_crc, crc);
4404 "ecore_set_nwuf_reg: idx[%d] reg_crc[0x%x=0x%08x] "
4405 "reg_len[0x%x=0x%x]\n",
4406 reg_idx, reg_crc, crc, reg_len, pattern_size);
4408 ecore_ptt_release(p_hwfn, p_ptt);
4413 void ecore_wol_buffer_clear(struct ecore_hwfn *p_hwfn,
4414 struct ecore_ptt *p_ptt)
4416 const u32 wake_buffer_clear_offset =
4417 ECORE_IS_BB(p_hwfn->p_dev) ?
4418 NIG_REG_WAKE_BUFFER_CLEAR_BB : WOL_REG_WAKE_BUFFER_CLEAR_K2_E5;
4420 DP_INFO(p_hwfn->p_dev,
4421 "ecore_wol_buffer_clear: reset "
4422 "REG_WAKE_BUFFER_CLEAR offset=0x%08x\n",
4423 wake_buffer_clear_offset);
4425 if (ECORE_IS_BB(p_hwfn->p_dev)) {
4426 ecore_wr(p_hwfn, p_ptt, wake_buffer_clear_offset, 1);
4427 ecore_wr(p_hwfn, p_ptt, wake_buffer_clear_offset, 0);
4429 ecore_mcp_wol_wr(p_hwfn, p_ptt, wake_buffer_clear_offset, 1);
4430 ecore_mcp_wol_wr(p_hwfn, p_ptt, wake_buffer_clear_offset, 0);
4434 enum _ecore_status_t ecore_get_wake_info(struct ecore_hwfn *p_hwfn,
4435 struct ecore_ptt *p_ptt,
4436 struct ecore_wake_info *wake_info)
4438 struct ecore_dev *p_dev = p_hwfn->p_dev;
4439 u32 *buf = OSAL_NULL;
4441 const u32 reg_wake_buffer_offest =
4442 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_BUFFER_BB :
4443 WOL_REG_WAKE_BUFFER_K2_E5;
4445 wake_info->wk_info = ecore_rd(p_hwfn, p_ptt,
4446 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_INFO_BB :
4447 WOL_REG_WAKE_INFO_K2_E5);
4448 wake_info->wk_details = ecore_rd(p_hwfn, p_ptt,
4449 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_DETAILS_BB :
4450 WOL_REG_WAKE_DETAILS_K2_E5);
4451 wake_info->wk_pkt_len = ecore_rd(p_hwfn, p_ptt,
4452 ECORE_IS_BB(p_dev) ? NIG_REG_WAKE_PKT_LEN_BB :
4453 WOL_REG_WAKE_PKT_LEN_K2_E5);
4456 "ecore_get_wake_info: REG_WAKE_INFO=0x%08x "
4457 "REG_WAKE_DETAILS=0x%08x "
4458 "REG_WAKE_PKT_LEN=0x%08x\n",
4460 wake_info->wk_details,
4461 wake_info->wk_pkt_len);
4463 buf = (u32 *)wake_info->wk_buffer;
4465 for (i = 0; i < (wake_info->wk_pkt_len / sizeof(u32)); i++)
4467 if ((i*sizeof(u32)) >= sizeof(wake_info->wk_buffer))
4470 "ecore_get_wake_info: i index to 0 high=%d\n",
4474 buf[i] = ecore_rd(p_hwfn, p_ptt,
4475 reg_wake_buffer_offest + (i * sizeof(u32)));
4476 DP_INFO(p_dev, "ecore_get_wake_info: wk_buffer[%u]: 0x%08x\n",
4480 ecore_wol_buffer_clear(p_hwfn, p_ptt);
4482 return ECORE_SUCCESS;
4485 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4486 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4488 ecore_ptt_pool_free(p_hwfn);
4489 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4490 p_hwfn->hw_info.p_igu_info = OSAL_NULL;
4493 /* Setup bar access */
4494 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4496 /* clear indirect access */
4497 if (ECORE_IS_AH(p_hwfn->p_dev) || ECORE_IS_E5(p_hwfn->p_dev)) {
4498 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4499 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
4500 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4501 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
4502 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4503 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
4504 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4505 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
4507 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4508 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4509 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4510 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4511 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4512 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4513 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4514 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4517 /* Clean previous pglue_b errors if such exist */
4518 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4520 /* enable internal target-read */
4521 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4522 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4525 static void get_function_id(struct ecore_hwfn *p_hwfn)
4528 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
4529 PXP_PF_ME_OPAQUE_ADDR);
4531 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4533 /* Bits 16-19 from the ME registers are the pf_num */
4534 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4535 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4536 PXP_CONCRETE_FID_PFID);
4537 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4538 PXP_CONCRETE_FID_PORT);
4540 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4541 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4542 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4545 void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4547 u32 *feat_num = p_hwfn->hw_info.feat_num;
4548 struct ecore_sb_cnt_info sb_cnt;
4551 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4552 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4554 #ifdef CONFIG_ECORE_ROCE
4555 /* Roce CNQ require each: 1 status block. 1 CNQ, we divide the
4556 * status blocks equally between L2 / RoCE but with consideration as
4557 * to how many l2 queues / cnqs we have
4559 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
4560 #ifndef __EXTRACT__LINUX__THROW__
4564 feat_num[ECORE_RDMA_CNQ] =
4567 RESC_NUM(p_hwfn, ECORE_RDMA_CNQ_RAM));
4569 #ifndef __EXTRACT__LINUX__THROW__
4570 /* Upper layer might require less */
4571 max_cnqs = (u32)p_hwfn->pf_params.rdma_pf_params.max_cnqs;
4573 if (max_cnqs == ECORE_RDMA_PF_PARAMS_CNQS_NONE)
4575 feat_num[ECORE_RDMA_CNQ] =
4577 feat_num[ECORE_RDMA_CNQ],
4582 non_l2_sbs = feat_num[ECORE_RDMA_CNQ];
4586 /* L2 Queues require each: 1 status block. 1 L2 queue */
4587 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4588 /* Start by allocating VF queues, then PF's */
4589 feat_num[ECORE_VF_L2_QUE] =
4591 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4593 feat_num[ECORE_PF_L2_QUE] =
4595 sb_cnt.cnt - non_l2_sbs,
4596 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4597 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4600 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4601 feat_num[ECORE_FCOE_CQ] =
4602 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
4605 if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
4606 feat_num[ECORE_ISCSI_CQ] =
4607 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
4610 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4611 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4612 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4613 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4614 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4615 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4616 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4620 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4623 case ECORE_L2_QUEUE:
4637 case ECORE_RDMA_CNQ_RAM:
4638 return "RDMA_CNQ_RAM";
4641 case ECORE_LL2_QUEUE:
4643 case ECORE_CMDQS_CQS:
4645 case ECORE_RDMA_STATS_QUEUE:
4646 return "RDMA_STATS_QUEUE";
4652 return "UNKNOWN_RESOURCE";
4656 static enum _ecore_status_t
4657 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4658 struct ecore_ptt *p_ptt,
4659 enum ecore_resources res_id,
4663 enum _ecore_status_t rc;
4665 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4666 resc_max_val, p_mcp_resp);
4667 if (rc != ECORE_SUCCESS) {
4668 DP_NOTICE(p_hwfn, false,
4669 "MFW response failure for a max value setting of resource %d [%s]\n",
4670 res_id, ecore_hw_get_resc_name(res_id));
4674 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4676 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4677 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4679 return ECORE_SUCCESS;
4682 static enum _ecore_status_t
4683 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4684 struct ecore_ptt *p_ptt)
4686 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4687 u32 resc_max_val, mcp_resp;
4689 enum _ecore_status_t rc;
4691 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4693 case ECORE_LL2_QUEUE:
4694 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
4696 case ECORE_RDMA_CNQ_RAM:
4697 /* No need for a case for ECORE_CMDQS_CQS since
4698 * CNQ/CMDQS are the same resource.
4700 resc_max_val = NUM_OF_GLOBAL_QUEUES;
4702 case ECORE_RDMA_STATS_QUEUE:
4703 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
4704 : RDMA_NUM_STATISTIC_COUNTERS_BB;
4707 resc_max_val = BDQ_NUM_RESOURCES;
4713 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4714 resc_max_val, &mcp_resp);
4715 if (rc != ECORE_SUCCESS)
4718 /* There's no point to continue to the next resource if the
4719 * command is not supported by the MFW.
4720 * We do continue if the command is supported but the resource
4721 * is unknown to the MFW. Such a resource will be later
4722 * configured with the default allocation values.
4724 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4725 return ECORE_NOTIMPL;
4728 return ECORE_SUCCESS;
4732 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4733 enum ecore_resources res_id,
4734 u32 *p_resc_num, u32 *p_resc_start)
4736 u8 num_funcs = p_hwfn->num_funcs_on_engine;
4737 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4740 case ECORE_L2_QUEUE:
4741 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
4742 MAX_NUM_L2_QUEUES_BB) / num_funcs;
4745 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
4746 MAX_NUM_VPORTS_BB) / num_funcs;
4749 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
4750 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
4753 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
4754 MAX_QM_TX_QUEUES_BB) / num_funcs;
4755 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
4758 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
4762 /* Each VFC resource can accommodate both a MAC and a VLAN */
4763 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4766 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
4767 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
4769 case ECORE_LL2_QUEUE:
4770 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
4772 case ECORE_RDMA_CNQ_RAM:
4773 case ECORE_CMDQS_CQS:
4774 /* CNQ/CMDQS are the same resource */
4775 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
4777 case ECORE_RDMA_STATS_QUEUE:
4778 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
4779 RDMA_NUM_STATISTIC_COUNTERS_BB) /
4783 if (p_hwfn->hw_info.personality != ECORE_PCI_ISCSI &&
4784 p_hwfn->hw_info.personality != ECORE_PCI_FCOE)
4790 /* Since we want its value to reflect whether MFW supports
4791 * the new scheme, have a default of 0.
4803 else if (p_hwfn->p_dev->num_ports_in_engine == 4)
4804 *p_resc_start = p_hwfn->port_id;
4805 else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI)
4806 *p_resc_start = p_hwfn->port_id;
4807 else if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE)
4808 *p_resc_start = p_hwfn->port_id + 2;
4811 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4815 return ECORE_SUCCESS;
4818 static enum _ecore_status_t
4819 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4820 bool drv_resc_alloc)
4822 u32 dflt_resc_num = 0, dflt_resc_start = 0;
4823 u32 mcp_resp, *p_resc_num, *p_resc_start;
4824 enum _ecore_status_t rc;
4826 p_resc_num = &RESC_NUM(p_hwfn, res_id);
4827 p_resc_start = &RESC_START(p_hwfn, res_id);
4829 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4831 if (rc != ECORE_SUCCESS) {
4833 "Failed to get default amount for resource %d [%s]\n",
4834 res_id, ecore_hw_get_resc_name(res_id));
4839 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4840 *p_resc_num = dflt_resc_num;
4841 *p_resc_start = dflt_resc_start;
4846 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4847 &mcp_resp, p_resc_num, p_resc_start);
4848 if (rc != ECORE_SUCCESS) {
4849 DP_NOTICE(p_hwfn, false,
4850 "MFW response failure for an allocation request for resource %d [%s]\n",
4851 res_id, ecore_hw_get_resc_name(res_id));
4855 /* Default driver values are applied in the following cases:
4856 * - The resource allocation MB command is not supported by the MFW
4857 * - There is an internal error in the MFW while processing the request
4858 * - The resource ID is unknown to the MFW
4860 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4862 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
4863 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4864 dflt_resc_num, dflt_resc_start);
4865 *p_resc_num = dflt_resc_num;
4866 *p_resc_start = dflt_resc_start;
4870 if ((*p_resc_num != dflt_resc_num ||
4871 *p_resc_start != dflt_resc_start) &&
4872 res_id != ECORE_SB) {
4874 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4875 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4876 *p_resc_start, dflt_resc_num, dflt_resc_start,
4877 drv_resc_alloc ? " - Applying default values" : "");
4878 if (drv_resc_alloc) {
4879 *p_resc_num = dflt_resc_num;
4880 *p_resc_start = dflt_resc_start;
4884 /* PQs have to divide by 8 [that's the HW granularity].
4885 * Reduce number so it would fit.
4887 if ((res_id == ECORE_PQ) &&
4888 ((*p_resc_num % 8) || (*p_resc_start % 8))) {
4890 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
4891 *p_resc_num, (*p_resc_num) & ~0x7,
4892 *p_resc_start, (*p_resc_start) & ~0x7);
4893 *p_resc_num &= ~0x7;
4894 *p_resc_start &= ~0x7;
4897 return ECORE_SUCCESS;
4900 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4901 bool drv_resc_alloc)
4903 enum _ecore_status_t rc;
4906 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4907 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4908 if (rc != ECORE_SUCCESS)
4912 return ECORE_SUCCESS;
4915 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4916 struct ecore_ptt *p_ptt)
4918 u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn);
4919 struct ecore_dev *p_dev = p_hwfn->p_dev;
4920 enum _ecore_status_t rc;
4922 rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4923 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4925 else if (rc == ECORE_NOTIMPL)
4926 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4928 if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4930 "Fix the PPFID bitmap to inculde the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
4931 native_ppfid_idx, p_dev->ppfid_bitmap);
4932 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4935 return ECORE_SUCCESS;
4938 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4939 struct ecore_ptt *p_ptt,
4940 bool drv_resc_alloc)
4942 struct ecore_resc_unlock_params resc_unlock_params;
4943 struct ecore_resc_lock_params resc_lock_params;
4944 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4946 enum _ecore_status_t rc;
4948 u32 *resc_start = p_hwfn->hw_info.resc_start;
4949 u32 *resc_num = p_hwfn->hw_info.resc_num;
4950 /* For AH, an equal share of the ILT lines between the maximal number of
4951 * PFs is not enough for RoCE. This would be solved by the future
4952 * resource allocation scheme, but isn't currently present for
4953 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4954 * to work - the BB number of ILT lines divided by its max PFs number.
4956 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4959 /* Setting the max values of the soft resources and the following
4960 * resources allocation queries should be atomic. Since several PFs can
4961 * run in parallel - a resource lock is needed.
4962 * If either the resource lock or resource set value commands are not
4963 * supported - skip the the max values setting, release the lock if
4964 * needed, and proceed to the queries. Other failures, including a
4965 * failure to acquire the lock, will cause this function to fail.
4966 * Old drivers that don't acquire the lock can run in parallel, and
4967 * their allocation values won't be affected by the updated max values.
4970 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4971 ECORE_RESC_LOCK_RESC_ALLOC, false);
4973 /* Changes on top of the default values to accommodate parallel attempts
4975 * [10 x 10 msec by default ==> 20 x 50 msec]
4977 resc_lock_params.retry_num *= 2;
4978 resc_lock_params.retry_interval *= 5;
4980 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4981 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4983 } else if (rc == ECORE_NOTIMPL) {
4985 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4986 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4987 DP_NOTICE(p_hwfn, false,
4988 "Failed to acquire the resource lock for the resource allocation commands\n");
4991 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4992 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4993 DP_NOTICE(p_hwfn, false,
4994 "Failed to set the max values of the soft resources\n");
4995 goto unlock_and_exit;
4996 } else if (rc == ECORE_NOTIMPL) {
4998 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4999 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
5000 &resc_unlock_params);
5001 if (rc != ECORE_SUCCESS)
5003 "Failed to release the resource lock for the resource allocation commands\n");
5007 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
5008 if (rc != ECORE_SUCCESS)
5009 goto unlock_and_exit;
5011 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
5012 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
5013 &resc_unlock_params);
5014 if (rc != ECORE_SUCCESS)
5016 "Failed to release the resource lock for the resource allocation commands\n");
5020 if (IS_LEAD_HWFN(p_hwfn)) {
5021 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
5022 if (rc != ECORE_SUCCESS)
5027 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
5028 /* Reduced build contains less PQs */
5029 if (!(p_hwfn->p_dev->b_is_emul_full)) {
5030 resc_num[ECORE_PQ] = 32;
5031 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
5032 p_hwfn->enabled_func_idx;
5035 /* For AH emulation, since we have a possible maximal number of
5036 * 16 enabled PFs, in case there are not enough ILT lines -
5037 * allocate only first PF as RoCE and have all the other ETH
5038 * only with less ILT lines.
5040 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
5041 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
5042 resc_num[ECORE_ILT],
5043 roce_min_ilt_lines);
5046 /* Correct the common ILT calculation if PF0 has more */
5047 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
5048 p_hwfn->p_dev->b_is_emul_full &&
5049 p_hwfn->rel_pf_id &&
5050 resc_num[ECORE_ILT] < roce_min_ilt_lines)
5051 resc_start[ECORE_ILT] += roce_min_ilt_lines -
5052 resc_num[ECORE_ILT];
5055 /* Sanity for ILT */
5056 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
5057 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
5058 DP_NOTICE(p_hwfn, true, "Can't assign ILT pages [%08x,...,%08x]\n",
5059 RESC_START(p_hwfn, ECORE_ILT),
5060 RESC_END(p_hwfn, ECORE_ILT) - 1);
5064 /* This will also learn the number of SBs from MFW */
5065 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
5068 ecore_hw_set_feat(p_hwfn);
5070 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5071 "The numbers for each resource are:\n");
5072 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
5073 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
5074 ecore_hw_get_resc_name(res_id),
5075 RESC_NUM(p_hwfn, res_id),
5076 RESC_START(p_hwfn, res_id));
5078 return ECORE_SUCCESS;
5081 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
5082 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
5083 &resc_unlock_params);
5087 static enum _ecore_status_t
5088 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
5089 struct ecore_ptt *p_ptt,
5090 struct ecore_hw_prepare_params *p_params)
5092 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
5093 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
5094 struct ecore_mcp_link_capabilities *p_caps;
5095 struct ecore_mcp_link_params *link;
5096 enum _ecore_status_t rc;
5097 u32 dcbx_mode; /* __LINUX__THROW__ */
5099 /* Read global nvm_cfg address */
5100 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
5102 /* Verify MCP has initialized it */
5103 if (!nvm_cfg_addr) {
5104 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
5105 if (p_params->b_relaxed_probe)
5106 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
5110 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
5111 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
5113 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5114 OFFSETOF(struct nvm_cfg1, glob) +
5115 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
5117 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
5119 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
5120 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
5121 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
5122 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
5124 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
5125 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
5127 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
5128 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
5130 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
5131 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
5133 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
5134 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
5136 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
5137 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
5139 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
5140 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
5142 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
5143 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
5145 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
5146 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
5148 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
5149 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
5151 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
5152 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
5155 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
5160 #ifndef __EXTRACT__LINUX__THROW__
5161 /* Read DCBX configuration */
5162 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5163 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
5164 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
5166 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
5167 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
5168 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
5169 switch (dcbx_mode) {
5170 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
5171 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
5173 case NVM_CFG1_PORT_DCBX_MODE_CEE:
5174 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
5176 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
5177 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
5180 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
5184 /* Read default link configuration */
5185 link = &p_hwfn->mcp_info->link_input;
5186 p_caps = &p_hwfn->mcp_info->link_capabilities;
5187 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5188 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
5189 link_temp = ecore_rd(p_hwfn, p_ptt,
5191 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
5192 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
5193 link->speed.advertised_speeds = link_temp;
5194 p_caps->speed_capabilities = link->speed.advertised_speeds;
5196 link_temp = ecore_rd(p_hwfn, p_ptt,
5198 OFFSETOF(struct nvm_cfg1_port, link_settings));
5199 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
5200 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
5201 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
5202 link->speed.autoneg = true;
5204 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
5205 link->speed.forced_speed = 1000;
5207 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
5208 link->speed.forced_speed = 10000;
5210 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
5211 link->speed.forced_speed = 20000;
5213 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
5214 link->speed.forced_speed = 25000;
5216 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
5217 link->speed.forced_speed = 40000;
5219 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
5220 link->speed.forced_speed = 50000;
5222 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
5223 link->speed.forced_speed = 100000;
5226 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n",
5230 p_caps->default_speed = link->speed.forced_speed; /* __LINUX__THROW__ */
5231 p_caps->default_speed_autoneg = link->speed.autoneg;
5233 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
5234 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
5235 link->pause.autoneg = !!(link_temp &
5236 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
5237 link->pause.forced_rx = !!(link_temp &
5238 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
5239 link->pause.forced_tx = !!(link_temp &
5240 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
5241 link->loopback_mode = 0;
5243 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
5244 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
5245 OFFSETOF(struct nvm_cfg1_port, ext_phy));
5246 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
5247 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
5248 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
5249 link->eee.enable = true;
5250 switch (link_temp) {
5251 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
5252 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
5253 link->eee.enable = false;
5255 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
5256 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
5258 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
5259 p_caps->eee_lpi_timer =
5260 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
5262 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
5263 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
5267 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
5268 link->eee.tx_lpi_enable = link->eee.enable;
5269 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
5271 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
5274 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5275 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
5276 link->speed.forced_speed, link->speed.advertised_speeds,
5277 link->speed.autoneg, link->pause.autoneg,
5278 p_caps->default_eee, p_caps->eee_lpi_timer);
5280 /* Read Multi-function information from shmem */
5281 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5282 OFFSETOF(struct nvm_cfg1, glob) +
5283 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
5285 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
5287 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
5288 NVM_CFG1_GLOB_MF_MODE_OFFSET;
5291 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5292 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
5294 case NVM_CFG1_GLOB_MF_MODE_UFP:
5295 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5296 1 << ECORE_MF_LLH_PROTO_CLSS |
5297 1 << ECORE_MF_UFP_SPECIFIC |
5298 1 << ECORE_MF_8021Q_TAGGING;
5300 case NVM_CFG1_GLOB_MF_MODE_BD:
5301 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5302 1 << ECORE_MF_LLH_PROTO_CLSS |
5303 1 << ECORE_MF_8021AD_TAGGING;
5305 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5306 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5307 1 << ECORE_MF_LLH_PROTO_CLSS |
5308 1 << ECORE_MF_LL2_NON_UNICAST |
5309 1 << ECORE_MF_INTER_PF_SWITCH |
5310 1 << ECORE_MF_DISABLE_ARFS;
5312 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5313 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5314 1 << ECORE_MF_LLH_PROTO_CLSS |
5315 1 << ECORE_MF_LL2_NON_UNICAST;
5316 if (ECORE_IS_BB(p_hwfn->p_dev))
5317 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
5320 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
5321 p_hwfn->p_dev->mf_bits);
5323 if (ECORE_IS_CMT(p_hwfn->p_dev))
5324 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
5326 #ifndef __EXTRACT__LINUX__THROW__
5327 /* It's funny since we have another switch, but it's easier
5328 * to throw this away in linux this way. Long term, it might be
5329 * better to have have getters for needed ECORE_MF_* fields,
5330 * convert client code and eliminate this.
5333 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5334 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5336 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5337 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5339 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5340 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5342 case NVM_CFG1_GLOB_MF_MODE_UFP:
5343 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5348 /* Read Multi-function information from shmem */
5349 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5350 OFFSETOF(struct nvm_cfg1, glob) +
5351 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5353 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5354 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5355 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5356 &p_hwfn->hw_info.device_capabilities);
5357 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5358 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5359 &p_hwfn->hw_info.device_capabilities);
5360 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5361 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5362 &p_hwfn->hw_info.device_capabilities);
5363 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5364 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5365 &p_hwfn->hw_info.device_capabilities);
5366 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5367 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5368 &p_hwfn->hw_info.device_capabilities);
5370 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5371 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5373 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5379 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5380 struct ecore_ptt *p_ptt)
5382 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5383 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5384 struct ecore_dev *p_dev = p_hwfn->p_dev;
5386 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5388 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5389 * in the other bits are selected.
5390 * Bits 1-15 are for functions 1-15, respectively, and their value is
5391 * '0' only for enabled functions (function 0 always exists and
5393 * In case of CMT in BB, only the "even" functions are enabled, and thus
5394 * the number of functions for both hwfns is learnt from the same bits.
5396 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
5398 if (reg_function_hide & 0x1) {
5399 if (ECORE_IS_BB(p_dev)) {
5400 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5412 /* Get the number of the enabled functions on the engine */
5413 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5420 /* Get the PF index within the enabled functions */
5421 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5422 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5430 p_hwfn->num_funcs_on_engine = num_funcs;
5431 p_hwfn->enabled_func_idx = enabled_func_idx;
5434 if (CHIP_REV_IS_FPGA(p_dev)) {
5435 DP_NOTICE(p_hwfn, false,
5436 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5437 p_hwfn->num_funcs_on_engine = 4;
5441 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5442 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5443 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5444 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5447 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
5448 struct ecore_ptt *p_ptt)
5450 struct ecore_dev *p_dev = p_hwfn->p_dev;
5454 /* Read the port mode */
5455 if (CHIP_REV_IS_FPGA(p_dev))
5457 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
5458 /* In CMT on emulation, assume 1 port */
5462 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
5464 if (port_mode < 3) {
5465 p_dev->num_ports_in_engine = 1;
5466 } else if (port_mode <= 5) {
5467 p_dev->num_ports_in_engine = 2;
5469 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
5470 p_dev->num_ports_in_engine);
5472 /* Default num_ports_in_engine to something */
5473 p_dev->num_ports_in_engine = 1;
5477 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
5478 struct ecore_ptt *p_ptt)
5480 struct ecore_dev *p_dev = p_hwfn->p_dev;
5484 p_dev->num_ports_in_engine = 0;
5487 if (CHIP_REV_IS_EMUL(p_dev)) {
5488 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5489 switch ((port & 0xf000) >> 12) {
5491 p_dev->num_ports_in_engine = 1;
5494 p_dev->num_ports_in_engine = 2;
5497 p_dev->num_ports_in_engine = 4;
5500 DP_NOTICE(p_hwfn, false,
5501 "Unknown port mode in ECO_RESERVED %08x\n",
5506 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
5507 port = ecore_rd(p_hwfn, p_ptt,
5508 CNIG_REG_NIG_PORT0_CONF_K2_E5 + (i * 4));
5510 p_dev->num_ports_in_engine++;
5513 if (!p_dev->num_ports_in_engine) {
5514 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
5516 /* Default num_ports_in_engine to something */
5517 p_dev->num_ports_in_engine = 1;
5521 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5522 struct ecore_ptt *p_ptt)
5524 struct ecore_dev *p_dev = p_hwfn->p_dev;
5526 /* Determine the number of ports per engine */
5527 if (ECORE_IS_BB(p_dev))
5528 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
5530 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
5532 /* Get the total number of ports of the device */
5533 if (ECORE_IS_CMT(p_dev)) {
5534 /* In CMT there is always only one port */
5535 p_dev->num_ports = 1;
5537 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
5538 p_dev->num_ports = p_dev->num_ports_in_engine *
5539 ecore_device_num_engines(p_dev);
5542 u32 addr, global_offsize, global_addr;
5544 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5546 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5547 global_addr = SECTION_ADDR(global_offsize, 0);
5548 addr = global_addr + OFFSETOF(struct public_global, max_ports);
5549 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5553 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5554 struct ecore_ptt *p_ptt)
5556 struct ecore_mcp_link_capabilities *p_caps;
5559 p_caps = &p_hwfn->mcp_info->link_capabilities;
5560 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5563 p_caps->eee_speed_caps = 0;
5564 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5565 OFFSETOF(struct public_port, eee_status));
5566 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5567 EEE_SUPPORTED_SPEED_OFFSET;
5568 if (eee_status & EEE_1G_SUPPORTED)
5569 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5570 if (eee_status & EEE_10G_ADV)
5571 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5574 static enum _ecore_status_t
5575 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5576 enum ecore_pci_personality personality,
5577 struct ecore_hw_prepare_params *p_params)
5579 bool drv_resc_alloc = p_params->drv_resc_alloc;
5580 enum _ecore_status_t rc;
5582 /* Since all information is common, only first hwfns should do this */
5583 if (IS_LEAD_HWFN(p_hwfn)) {
5584 rc = ecore_iov_hw_info(p_hwfn);
5585 if (rc != ECORE_SUCCESS) {
5586 if (p_params->b_relaxed_probe)
5587 p_params->p_relaxed_res =
5588 ECORE_HW_PREPARE_BAD_IOV;
5594 if (IS_LEAD_HWFN(p_hwfn))
5595 ecore_hw_info_port_num(p_hwfn, p_ptt);
5597 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5600 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
5602 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5603 if (rc != ECORE_SUCCESS)
5609 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5610 if (rc != ECORE_SUCCESS) {
5611 if (p_params->b_relaxed_probe)
5612 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5618 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5620 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5621 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5624 static u8 mcp_hw_mac[6] = {0, 2, 3, 4, 5, 6};
5626 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5627 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5631 if (ecore_mcp_is_init(p_hwfn)) {
5632 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5633 p_hwfn->hw_info.ovlan =
5634 p_hwfn->mcp_info->func_info.ovlan;
5636 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5638 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5640 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5643 if (personality != ECORE_PCI_DEFAULT) {
5644 p_hwfn->hw_info.personality = personality;
5645 } else if (ecore_mcp_is_init(p_hwfn)) {
5646 enum ecore_pci_personality protocol;
5648 protocol = p_hwfn->mcp_info->func_info.protocol;
5649 p_hwfn->hw_info.personality = protocol;
5653 /* To overcome ILT lack for emulation, until at least until we'll have
5654 * a definite answer from system about it, allow only PF0 to be RoCE.
5656 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
5657 if (!p_hwfn->rel_pf_id)
5658 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5660 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5664 /* although in BB some constellations may support more than 4 tcs,
5665 * that can result in performance penalty in some cases. 4
5666 * represents a good tradeoff between performance and flexibility.
5668 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5670 /* start out with a single active tc. This can be increased either
5671 * by dcbx negotiation or by upper layer driver
5673 p_hwfn->hw_info.num_active_tc = 1;
5675 ecore_get_num_funcs(p_hwfn, p_ptt);
5677 if (ecore_mcp_is_init(p_hwfn))
5678 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5680 /* In case of forcing the driver's default resource allocation, calling
5681 * ecore_hw_get_resc() should come after initializing the personality
5682 * and after getting the number of functions, since the calculation of
5683 * the resources/features depends on them.
5684 * This order is not harmful if not forcing.
5686 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5687 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5689 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5695 #define ECORE_MAX_DEVICE_NAME_LEN (8)
5697 void ecore_get_dev_name(struct ecore_dev *p_dev, u8 *name, u8 max_chars)
5701 n = OSAL_MIN_T(u8, max_chars, ECORE_MAX_DEVICE_NAME_LEN);
5702 OSAL_SNPRINTF(name, n, "%s %c%d", ECORE_IS_BB(p_dev) ? "BB" : "AH",
5703 'A' + p_dev->chip_rev, (int)p_dev->chip_metal);
5706 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5707 struct ecore_ptt *p_ptt)
5709 struct ecore_dev *p_dev = p_hwfn->p_dev;
5713 /* Read Vendor Id / Device Id */
5714 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5716 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5719 /* Determine type */
5720 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5721 switch (device_id_mask) {
5722 case ECORE_DEV_ID_MASK_BB:
5723 p_dev->type = ECORE_DEV_TYPE_BB;
5725 case ECORE_DEV_ID_MASK_AH:
5726 p_dev->type = ECORE_DEV_TYPE_AH;
5728 case ECORE_DEV_ID_MASK_E5:
5729 p_dev->type = ECORE_DEV_TYPE_E5;
5732 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5734 return ECORE_ABORTED;
5737 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5738 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5739 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5740 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5742 /* Learn number of HW-functions */
5743 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5745 if (tmp & (1 << p_hwfn->rel_pf_id)) {
5746 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5747 p_dev->num_hwfns = 2;
5749 p_dev->num_hwfns = 1;
5753 if (CHIP_REV_IS_EMUL(p_dev)) {
5754 /* For some reason we have problems with this register
5755 * in B0 emulation; Simply assume no CMT
5757 DP_NOTICE(p_dev->hwfns, false, "device on emul - assume no CMT\n");
5758 p_dev->num_hwfns = 1;
5762 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5763 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5764 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5765 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5767 DP_INFO(p_dev->hwfns,
5768 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5769 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5770 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5771 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5774 if (ECORE_IS_BB_A0(p_dev)) {
5775 DP_NOTICE(p_dev->hwfns, false,
5776 "The chip type/rev (BB A0) is not supported!\n");
5777 return ECORE_ABORTED;
5781 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5782 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5784 if (CHIP_REV_IS_EMUL(p_dev)) {
5785 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5786 if (tmp & (1 << 29)) {
5787 DP_NOTICE(p_hwfn, false, "Emulation: Running on a FULL build\n");
5788 p_dev->b_is_emul_full = true;
5790 DP_NOTICE(p_hwfn, false, "Emulation: Running on a REDUCED build\n");
5795 return ECORE_SUCCESS;
5798 #ifndef LINUX_REMOVE
5799 void ecore_hw_hibernate_prepare(struct ecore_dev *p_dev)
5806 for_each_hwfn(p_dev, j) {
5807 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5809 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Mark hw/fw uninitialized\n");
5811 p_hwfn->hw_init_done = false;
5813 ecore_ptt_invalidate(p_hwfn);
5817 void ecore_hw_hibernate_resume(struct ecore_dev *p_dev)
5824 for_each_hwfn(p_dev, j) {
5825 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5826 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
5828 ecore_hw_hwfn_prepare(p_hwfn);
5831 DP_NOTICE(p_hwfn, false, "ptt acquire failed\n");
5833 ecore_load_mcp_offsets(p_hwfn, p_ptt);
5834 ecore_ptt_release(p_hwfn, p_ptt);
5836 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "Reinitialized hw after low power state\n");
5842 static enum _ecore_status_t
5843 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5844 void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5845 struct ecore_hw_prepare_params *p_params)
5847 struct ecore_mdump_retain_data mdump_retain;
5848 struct ecore_dev *p_dev = p_hwfn->p_dev;
5849 struct ecore_mdump_info mdump_info;
5850 enum _ecore_status_t rc = ECORE_SUCCESS;
5852 /* Split PCI bars evenly between hwfns */
5853 p_hwfn->regview = p_regview;
5854 p_hwfn->doorbells = p_doorbells;
5855 p_hwfn->db_phys_addr = db_phys_addr;
5857 #ifndef LINUX_REMOVE
5858 p_hwfn->reg_offset = (u8 *)p_hwfn->regview - (u8 *)p_hwfn->p_dev->regview;
5859 p_hwfn->db_offset = (u8 *)p_hwfn->doorbells - (u8 *)p_hwfn->p_dev->doorbells;
5863 return ecore_vf_hw_prepare(p_hwfn);
5865 /* Validate that chip access is feasible */
5866 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5867 DP_ERR(p_hwfn, "Reading the ME register returns all Fs; Preventing further chip access\n");
5868 if (p_params->b_relaxed_probe)
5869 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5873 get_function_id(p_hwfn);
5875 /* Allocate PTT pool */
5876 rc = ecore_ptt_pool_alloc(p_hwfn);
5878 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5879 if (p_params->b_relaxed_probe)
5880 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5884 /* Allocate the main PTT */
5885 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5887 /* First hwfn learns basic information, e.g., number of hwfns */
5888 if (!p_hwfn->my_id) {
5889 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5890 if (rc != ECORE_SUCCESS) {
5891 if (p_params->b_relaxed_probe)
5892 p_params->p_relaxed_res =
5893 ECORE_HW_PREPARE_FAILED_DEV;
5898 ecore_hw_hwfn_prepare(p_hwfn);
5900 /* Initialize MCP structure */
5901 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5903 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5904 if (p_params->b_relaxed_probe)
5905 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5909 /* Read the device configuration information from the HW and SHMEM */
5910 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5911 p_params->personality, p_params);
5913 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5917 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5918 * called, since among others it sets the ports number in an engine.
5920 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5921 !p_dev->recov_in_prog) {
5922 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5923 if (rc != ECORE_SUCCESS)
5924 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5927 /* Check if mdump logs/data are present and update the epoch value */
5928 if (IS_LEAD_HWFN(p_hwfn)) {
5930 if (!CHIP_REV_IS_EMUL(p_dev)) {
5932 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5934 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5935 DP_NOTICE(p_hwfn, false,
5936 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5938 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5940 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5941 DP_NOTICE(p_hwfn, false,
5942 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5943 mdump_retain.epoch, mdump_retain.pf,
5944 mdump_retain.status);
5946 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5953 /* Allocate the init RT array and initialize the init-ops engine */
5954 rc = ecore_init_alloc(p_hwfn);
5956 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5957 if (p_params->b_relaxed_probe)
5958 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5963 if (CHIP_REV_IS_FPGA(p_dev)) {
5964 DP_NOTICE(p_hwfn, false,
5965 "FPGA: workaround; Prevent DMAE parities\n");
5966 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
5969 DP_NOTICE(p_hwfn, false,
5970 "FPGA: workaround: Set VF bar0 size\n");
5971 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5972 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
5978 if (IS_LEAD_HWFN(p_hwfn))
5979 ecore_iov_free_hw_info(p_dev);
5980 ecore_mcp_free(p_hwfn);
5982 ecore_hw_hwfn_free(p_hwfn);
5987 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5988 struct ecore_hw_prepare_params *p_params)
5990 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5991 enum _ecore_status_t rc;
5993 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5994 p_dev->allow_mdump = p_params->allow_mdump;
5996 if (p_params->b_relaxed_probe)
5997 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5999 /* Store the precompiled init data ptrs */
6001 ecore_init_iro_array(p_dev);
6003 /* Initialize the first hwfn - will learn number of hwfns */
6004 rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
6005 p_dev->doorbells, p_dev->db_phys_addr,
6007 if (rc != ECORE_SUCCESS)
6010 p_params->personality = p_hwfn->hw_info.personality;
6012 /* initilalize 2nd hwfn if necessary */
6013 if (ECORE_IS_CMT(p_dev)) {
6014 void OSAL_IOMEM *p_regview, *p_doorbell;
6015 u8 OSAL_IOMEM *addr;
6019 /* adjust bar offset for second engine */
6020 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
6022 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
6023 p_regview = (void OSAL_IOMEM *)addr;
6025 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
6027 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
6028 p_doorbell = (void OSAL_IOMEM *)addr;
6029 db_phys_addr = p_dev->db_phys_addr + offset;
6031 /* prepare second hw function */
6032 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
6033 p_doorbell, db_phys_addr,
6036 /* in case of error, need to free the previously
6037 * initiliazed hwfn 0.
6039 if (rc != ECORE_SUCCESS) {
6040 if (p_params->b_relaxed_probe)
6041 p_params->p_relaxed_res =
6042 ECORE_HW_PREPARE_FAILED_ENG2;
6045 ecore_init_free(p_hwfn);
6046 ecore_mcp_free(p_hwfn);
6047 ecore_hw_hwfn_free(p_hwfn);
6049 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
6058 void ecore_hw_remove(struct ecore_dev *p_dev)
6060 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
6064 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
6065 ECORE_OV_DRIVER_STATE_NOT_LOADED);
6067 for_each_hwfn(p_dev, i) {
6068 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6071 ecore_vf_pf_release(p_hwfn);
6075 ecore_init_free(p_hwfn);
6076 ecore_hw_hwfn_free(p_hwfn);
6077 ecore_mcp_free(p_hwfn);
6079 #ifdef CONFIG_ECORE_LOCK_ALLOC
6080 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
6084 ecore_iov_free_hw_info(p_dev);
6087 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
6088 struct ecore_chain *p_chain)
6090 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
6091 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
6092 struct ecore_chain_next *p_next;
6098 size = p_chain->elem_size * p_chain->usable_per_page;
6100 for (i = 0; i < p_chain->page_cnt; i++) {
6104 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
6105 p_virt_next = p_next->next_virt;
6106 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
6108 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
6109 ECORE_CHAIN_PAGE_SIZE);
6111 p_virt = p_virt_next;
6112 p_phys = p_phys_next;
6116 static void ecore_chain_free_single(struct ecore_dev *p_dev,
6117 struct ecore_chain *p_chain)
6119 if (!p_chain->p_virt_addr)
6122 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
6123 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
6126 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
6127 struct ecore_chain *p_chain)
6129 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
6130 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
6131 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
6133 if (!pp_virt_addr_tbl)
6139 for (i = 0; i < page_cnt; i++) {
6140 if (!pp_virt_addr_tbl[i])
6143 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
6144 *(dma_addr_t *)p_pbl_virt,
6145 ECORE_CHAIN_PAGE_SIZE);
6147 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
6150 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
6152 if (!p_chain->b_external_pbl) {
6153 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
6154 p_chain->pbl_sp.p_phys_table, pbl_size);
6157 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
6158 p_chain->pbl.pp_virt_addr_tbl = OSAL_NULL;
6161 void ecore_chain_free(struct ecore_dev *p_dev,
6162 struct ecore_chain *p_chain)
6164 switch (p_chain->mode) {
6165 case ECORE_CHAIN_MODE_NEXT_PTR:
6166 ecore_chain_free_next_ptr(p_dev, p_chain);
6168 case ECORE_CHAIN_MODE_SINGLE:
6169 ecore_chain_free_single(p_dev, p_chain);
6171 case ECORE_CHAIN_MODE_PBL:
6172 ecore_chain_free_pbl(p_dev, p_chain);
6177 static enum _ecore_status_t
6178 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
6179 enum ecore_chain_cnt_type cnt_type,
6180 osal_size_t elem_size, u32 page_cnt)
6182 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
6184 /* The actual chain size can be larger than the maximal possible value
6185 * after rounding up the requested elements number to pages, and after
6186 * taking into acount the unusuable elements (next-ptr elements).
6187 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
6188 * size/capacity fields are of a u32 type.
6190 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
6191 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
6192 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
6193 chain_size > ECORE_U32_MAX)) {
6194 DP_NOTICE(p_dev, true,
6195 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
6196 (unsigned long long)chain_size);
6200 return ECORE_SUCCESS;
6203 static enum _ecore_status_t
6204 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
6206 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
6207 dma_addr_t p_phys = 0;
6210 for (i = 0; i < p_chain->page_cnt; i++) {
6211 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6212 ECORE_CHAIN_PAGE_SIZE);
6214 DP_NOTICE(p_dev, false,
6215 "Failed to allocate chain memory\n");
6220 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6221 ecore_chain_reset(p_chain);
6223 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6227 p_virt_prev = p_virt;
6229 /* Last page's next element should point to the beginning of the
6232 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6233 p_chain->p_virt_addr,
6234 p_chain->p_phys_addr);
6236 return ECORE_SUCCESS;
6239 static enum _ecore_status_t
6240 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
6242 dma_addr_t p_phys = 0;
6243 void *p_virt = OSAL_NULL;
6245 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
6247 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
6251 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6252 ecore_chain_reset(p_chain);
6254 return ECORE_SUCCESS;
6257 static enum _ecore_status_t
6258 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
6259 struct ecore_chain *p_chain,
6260 struct ecore_chain_ext_pbl *ext_pbl)
6262 u32 page_cnt = p_chain->page_cnt, size, i;
6263 dma_addr_t p_phys = 0, p_pbl_phys = 0;
6264 void **pp_virt_addr_tbl = OSAL_NULL;
6265 u8 *p_pbl_virt = OSAL_NULL;
6266 void *p_virt = OSAL_NULL;
6268 size = page_cnt * sizeof(*pp_virt_addr_tbl);
6269 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
6270 if (!pp_virt_addr_tbl) {
6271 DP_NOTICE(p_dev, false,
6272 "Failed to allocate memory for the chain virtual addresses table\n");
6276 /* The allocation of the PBL table is done with its full size, since it
6277 * is expected to be successive.
6278 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
6279 * failure, since pp_virt_addr_tbl was previously allocated, and it
6280 * should be saved to allow its freeing during the error flow.
6282 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
6284 if (ext_pbl == OSAL_NULL) {
6285 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
6287 p_pbl_virt = ext_pbl->p_pbl_virt;
6288 p_pbl_phys = ext_pbl->p_pbl_phys;
6289 p_chain->b_external_pbl = true;
6292 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
6295 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
6299 for (i = 0; i < page_cnt; i++) {
6300 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6301 ECORE_CHAIN_PAGE_SIZE);
6303 DP_NOTICE(p_dev, false,
6304 "Failed to allocate chain memory\n");
6309 ecore_chain_init_mem(p_chain, p_virt, p_phys);
6310 ecore_chain_reset(p_chain);
6313 /* Fill the PBL table with the physical address of the page */
6314 *(dma_addr_t *)p_pbl_virt = p_phys;
6315 /* Keep the virtual address of the page */
6316 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
6318 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
6321 return ECORE_SUCCESS;
6324 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
6325 enum ecore_chain_use_mode intended_use,
6326 enum ecore_chain_mode mode,
6327 enum ecore_chain_cnt_type cnt_type,
6328 u32 num_elems, osal_size_t elem_size,
6329 struct ecore_chain *p_chain,
6330 struct ecore_chain_ext_pbl *ext_pbl)
6333 enum _ecore_status_t rc = ECORE_SUCCESS;
6335 if (mode == ECORE_CHAIN_MODE_SINGLE)
6338 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
6340 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
6343 DP_NOTICE(p_dev, false,
6344 "Cannot allocate a chain with the given arguments:\n"
6345 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
6346 intended_use, mode, cnt_type, num_elems, elem_size);
6350 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
6351 mode, cnt_type, p_dev->dp_ctx);
6354 case ECORE_CHAIN_MODE_NEXT_PTR:
6355 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6357 case ECORE_CHAIN_MODE_SINGLE:
6358 rc = ecore_chain_alloc_single(p_dev, p_chain);
6360 case ECORE_CHAIN_MODE_PBL:
6361 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6367 return ECORE_SUCCESS;
6370 ecore_chain_free(p_dev, p_chain);
6374 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6375 u16 src_id, u16 *dst_id)
6377 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6380 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6381 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6382 DP_NOTICE(p_hwfn, true, "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6388 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6390 return ECORE_SUCCESS;
6393 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6394 u8 src_id, u8 *dst_id)
6396 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6399 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6400 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6401 DP_NOTICE(p_hwfn, true, "vport id [%d] is not valid, available indices [%d - %d]\n",
6407 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6409 return ECORE_SUCCESS;
6412 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6413 u8 src_id, u8 *dst_id)
6415 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6418 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6419 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6420 DP_NOTICE(p_hwfn, true, "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6426 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6428 return ECORE_SUCCESS;
6431 enum _ecore_status_t
6432 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6433 struct ecore_ptt *p_ptt)
6435 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6436 ecore_wr(p_hwfn, p_ptt,
6437 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6438 1 << p_hwfn->abs_pf_id / 2);
6439 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6440 return ECORE_SUCCESS;
6442 DP_NOTICE(p_hwfn, false,
6443 "This function can't be set as default\n");
6448 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6449 struct ecore_ptt *p_ptt,
6450 u32 hw_addr, void *p_eth_qzone,
6451 osal_size_t eth_qzone_size,
6454 struct coalescing_timeset *p_coal_timeset;
6456 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6457 DP_NOTICE(p_hwfn, true,
6458 "Coalescing configuration not enabled\n");
6462 p_coal_timeset = p_eth_qzone;
6463 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6464 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6465 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6466 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6468 return ECORE_SUCCESS;
6471 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6472 u16 rx_coal, u16 tx_coal,
6475 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6476 enum _ecore_status_t rc = ECORE_SUCCESS;
6477 struct ecore_ptt *p_ptt;
6479 /* TODO - Configuring a single queue's coalescing but
6480 * claiming all queues are abiding same configuration
6481 * for PF and VF both.
6484 #ifdef CONFIG_ECORE_SRIOV
6485 if (IS_VF(p_hwfn->p_dev))
6486 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6488 #endif /* #ifdef CONFIG_ECORE_SRIOV */
6490 p_ptt = ecore_ptt_acquire(p_hwfn);
6495 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6498 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6502 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6505 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6508 ecore_ptt_release(p_hwfn, p_ptt);
6513 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6514 struct ecore_ptt *p_ptt,
6516 struct ecore_queue_cid *p_cid)
6518 struct ustorm_eth_queue_zone eth_qzone;
6519 u8 timeset, timer_res;
6521 enum _ecore_status_t rc;
6523 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6524 if (coalesce <= 0x7F)
6526 else if (coalesce <= 0xFF)
6528 else if (coalesce <= 0x1FF)
6531 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6534 timeset = (u8)(coalesce >> timer_res);
6536 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6537 p_cid->sb_igu_id, false);
6538 if (rc != ECORE_SUCCESS)
6541 address = BAR0_MAP_REG_USDM_RAM +
6542 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6544 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6545 sizeof(struct ustorm_eth_queue_zone), timeset);
6546 if (rc != ECORE_SUCCESS)
6553 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6554 struct ecore_ptt *p_ptt,
6556 struct ecore_queue_cid *p_cid)
6558 struct xstorm_eth_queue_zone eth_qzone;
6559 u8 timeset, timer_res;
6561 enum _ecore_status_t rc;
6563 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6564 if (coalesce <= 0x7F)
6566 else if (coalesce <= 0xFF)
6568 else if (coalesce <= 0x1FF)
6571 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6574 timeset = (u8)(coalesce >> timer_res);
6576 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6577 p_cid->sb_igu_id, true);
6578 if (rc != ECORE_SUCCESS)
6581 address = BAR0_MAP_REG_XSDM_RAM +
6582 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6584 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6585 sizeof(struct xstorm_eth_queue_zone), timeset);
6590 /* Calculate final WFQ values for all vports and configure it.
6591 * After this configuration each vport must have
6592 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
6594 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6595 struct ecore_ptt *p_ptt,
6598 struct init_qm_vport_params *vport_params;
6601 vport_params = p_hwfn->qm_info.qm_vport_params;
6603 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6604 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6606 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6608 ecore_init_vport_wfq(p_hwfn, p_ptt,
6609 vport_params[i].first_tx_pq_id,
6610 vport_params[i].vport_wfq);
6614 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6619 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6620 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
6623 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6624 struct ecore_ptt *p_ptt)
6626 struct init_qm_vport_params *vport_params;
6629 vport_params = p_hwfn->qm_info.qm_vport_params;
6631 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6632 ecore_init_wfq_default_param(p_hwfn);
6633 ecore_init_vport_wfq(p_hwfn, p_ptt,
6634 vport_params[i].first_tx_pq_id,
6635 vport_params[i].vport_wfq);
6639 /* This function performs several validations for WFQ
6640 * configuration and required min rate for a given vport
6641 * 1. req_rate must be greater than one percent of min_pf_rate.
6642 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6643 * rates to get less than one percent of min_pf_rate.
6644 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6646 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6647 u16 vport_id, u32 req_rate,
6650 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6651 int non_requested_count = 0, req_count = 0, i, num_vports;
6653 num_vports = p_hwfn->qm_info.num_vports;
6655 /* Accounting for the vports which are configured for WFQ explicitly */
6656 for (i = 0; i < num_vports; i++) {
6659 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6661 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6662 total_req_min_rate += tmp_speed;
6666 /* Include current vport data as well */
6668 total_req_min_rate += req_rate;
6669 non_requested_count = num_vports - req_count;
6671 /* validate possible error cases */
6672 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6673 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6674 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6675 vport_id, req_rate, min_pf_rate);
6679 /* TBD - for number of vports greater than 100 */
6680 if (num_vports > ECORE_WFQ_UNIT) {
6681 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6682 "Number of vports is greater than %d\n",
6687 if (total_req_min_rate > min_pf_rate) {
6688 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6689 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6690 total_req_min_rate, min_pf_rate);
6694 /* Data left for non requested vports */
6695 total_left_rate = min_pf_rate - total_req_min_rate;
6696 left_rate_per_vp = total_left_rate / non_requested_count;
6698 /* validate if non requested get < 1% of min bw */
6699 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6700 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6701 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6702 left_rate_per_vp, min_pf_rate);
6706 /* now req_rate for given vport passes all scenarios.
6707 * assign final wfq rates to all vports.
6709 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6710 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6712 for (i = 0; i < num_vports; i++) {
6713 if (p_hwfn->qm_info.wfq_data[i].configured)
6716 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6719 return ECORE_SUCCESS;
6722 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6723 struct ecore_ptt *p_ptt,
6724 u16 vp_id, u32 rate)
6726 struct ecore_mcp_link_state *p_link;
6727 int rc = ECORE_SUCCESS;
6729 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
6731 if (!p_link->min_pf_rate) {
6732 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6733 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6737 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6739 if (rc == ECORE_SUCCESS)
6740 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6741 p_link->min_pf_rate);
6743 DP_NOTICE(p_hwfn, false,
6744 "Validation failed while configuring min rate\n");
6749 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6750 struct ecore_ptt *p_ptt,
6753 bool use_wfq = false;
6754 int rc = ECORE_SUCCESS;
6757 /* Validate all pre configured vports for wfq */
6758 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6761 if (!p_hwfn->qm_info.wfq_data[i].configured)
6764 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6767 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6768 if (rc != ECORE_SUCCESS) {
6769 DP_NOTICE(p_hwfn, false,
6770 "WFQ validation failed while configuring min rate\n");
6775 if (rc == ECORE_SUCCESS && use_wfq)
6776 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6778 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6783 /* Main API for ecore clients to configure vport min rate.
6784 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6785 * rate - Speed in Mbps needs to be assigned to a given vport.
6787 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6789 int i, rc = ECORE_INVAL;
6791 /* TBD - for multiple hardware functions - that is 100 gig */
6792 if (ECORE_IS_CMT(p_dev)) {
6793 DP_NOTICE(p_dev, false,
6794 "WFQ configuration is not supported for this device\n");
6798 for_each_hwfn(p_dev, i) {
6799 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6800 struct ecore_ptt *p_ptt;
6802 p_ptt = ecore_ptt_acquire(p_hwfn);
6804 return ECORE_TIMEOUT;
6806 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6808 if (rc != ECORE_SUCCESS) {
6809 ecore_ptt_release(p_hwfn, p_ptt);
6813 ecore_ptt_release(p_hwfn, p_ptt);
6819 /* API to configure WFQ from mcp link change */
6820 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6821 struct ecore_ptt *p_ptt,
6826 /* TBD - for multiple hardware functions - that is 100 gig */
6827 if (ECORE_IS_CMT(p_dev)) {
6828 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6829 "WFQ configuration is not supported for this device\n");
6833 for_each_hwfn(p_dev, i) {
6834 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6836 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6841 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6842 struct ecore_ptt *p_ptt,
6843 struct ecore_mcp_link_state *p_link,
6846 int rc = ECORE_SUCCESS;
6848 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6850 if (!p_link->line_speed && (max_bw != 100))
6853 p_link->speed = (p_link->line_speed * max_bw) / 100;
6854 p_hwfn->qm_info.pf_rl = p_link->speed;
6856 /* Since the limiter also affects Tx-switched traffic, we don't want it
6857 * to limit such traffic in case there's no actual limit.
6858 * In that case, set limit to imaginary high boundary.
6861 p_hwfn->qm_info.pf_rl = 100000;
6863 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6864 p_hwfn->qm_info.pf_rl);
6866 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6867 "Configured MAX bandwidth to be %08x Mb/sec\n",
6873 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6874 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6876 int i, rc = ECORE_INVAL;
6878 if (max_bw < 1 || max_bw > 100) {
6879 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6883 for_each_hwfn(p_dev, i) {
6884 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6885 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6886 struct ecore_mcp_link_state *p_link;
6887 struct ecore_ptt *p_ptt;
6889 p_link = &p_lead->mcp_info->link_output;
6891 p_ptt = ecore_ptt_acquire(p_hwfn);
6893 return ECORE_TIMEOUT;
6895 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6898 ecore_ptt_release(p_hwfn, p_ptt);
6900 if (rc != ECORE_SUCCESS)
6907 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6908 struct ecore_ptt *p_ptt,
6909 struct ecore_mcp_link_state *p_link,
6912 int rc = ECORE_SUCCESS;
6914 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6915 p_hwfn->qm_info.pf_wfq = min_bw;
6917 if (!p_link->line_speed)
6920 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6922 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6924 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6925 "Configured MIN bandwidth to be %d Mb/sec\n",
6926 p_link->min_pf_rate);
6931 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6932 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6934 int i, rc = ECORE_INVAL;
6936 if (min_bw < 1 || min_bw > 100) {
6937 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6941 for_each_hwfn(p_dev, i) {
6942 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6943 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6944 struct ecore_mcp_link_state *p_link;
6945 struct ecore_ptt *p_ptt;
6947 p_link = &p_lead->mcp_info->link_output;
6949 p_ptt = ecore_ptt_acquire(p_hwfn);
6951 return ECORE_TIMEOUT;
6953 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6955 if (rc != ECORE_SUCCESS) {
6956 ecore_ptt_release(p_hwfn, p_ptt);
6960 if (p_link->min_pf_rate) {
6961 u32 min_rate = p_link->min_pf_rate;
6963 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6968 ecore_ptt_release(p_hwfn, p_ptt);
6974 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6976 struct ecore_mcp_link_state *p_link;
6978 p_link = &p_hwfn->mcp_info->link_output;
6980 if (p_link->min_pf_rate)
6981 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6983 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6984 sizeof(*p_hwfn->qm_info.wfq_data) *
6985 p_hwfn->qm_info.num_vports);
6988 int ecore_device_num_engines(struct ecore_dev *p_dev)
6990 return ECORE_IS_BB(p_dev) ? 2 : 1;
6993 int ecore_device_num_ports(struct ecore_dev *p_dev)
6995 return p_dev->num_ports;
6998 void ecore_set_fw_mac_addr(__le16 *fw_msb,
7003 ((u8 *)fw_msb)[0] = mac[1];
7004 ((u8 *)fw_msb)[1] = mac[0];
7005 ((u8 *)fw_mid)[0] = mac[3];
7006 ((u8 *)fw_mid)[1] = mac[2];
7007 ((u8 *)fw_lsb)[0] = mac[5];
7008 ((u8 *)fw_lsb)[1] = mac[4];
7011 void ecore_set_dev_access_enable(struct ecore_dev *p_dev, bool b_enable)
7013 if (p_dev->recov_in_prog != !b_enable) {
7014 DP_INFO(p_dev, "%s access to the device\n",
7015 b_enable ? "Enable" : "Disable");
7016 p_dev->recov_in_prog = !b_enable;
7021 #pragma warning(pop)