2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ECORE_HSI_INIT_TOOL__
33 #define __ECORE_HSI_INIT_TOOL__
34 /**************************************/
35 /* Init Tool HSI constants and macros */
36 /**************************************/
38 /* Width of GRC address in bits (addresses are specified in dwords) */
39 #define GRC_ADDR_BITS 23
40 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
42 /* indicates an init that should be applied to any phase ID */
43 #define ANY_PHASE_ID 0xffff
45 /* Max size in dwords of a zipped array */
46 #define MAX_ZIPPED_SIZE 8192
60 MODE_BB_A0_DEPRECATED,
103 * Binary buffer header
105 struct bin_buffer_hdr
107 u32 offset /* buffer offset in bytes from the beginning of the binary file */;
108 u32 length /* buffer length in bytes */;
113 * binary init buffer types
115 enum bin_init_buffer_type
117 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
118 BIN_BUF_INIT_CMD /* init commands */,
119 BIN_BUF_INIT_VAL /* init data */,
120 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
121 BIN_BUF_INIT_IRO /* internal RAM offsets */,
122 MAX_BIN_INIT_BUFFER_TYPE
127 * init array header: raw
129 struct init_array_raw_hdr
132 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
133 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
134 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
135 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
139 * init array header: standard
141 struct init_array_standard_hdr
144 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
145 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
146 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */
147 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
151 * init array header: zipped
153 struct init_array_zipped_hdr
156 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
157 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
158 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */
159 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
163 * init array header: pattern
165 struct init_array_pattern_hdr
168 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
169 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
170 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */
171 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
172 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */
173 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
177 * init array header union
181 struct init_array_raw_hdr raw /* raw init array header */;
182 struct init_array_standard_hdr standard /* standard init array header */;
183 struct init_array_zipped_hdr zipped /* zipped init array header */;
184 struct init_array_pattern_hdr pattern /* pattern init array header */;
194 enum init_array_types
196 INIT_ARR_STANDARD /* standard init array */,
197 INIT_ARR_ZIPPED /* zipped init array */,
198 INIT_ARR_PATTERN /* a repeated pattern */,
205 * init operation: callback
207 struct init_callback_op
210 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
211 #define INIT_CALLBACK_OP_OP_SHIFT 0
212 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
213 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
214 u16 callback_id /* Callback ID */;
215 u16 block_id /* Blocks ID */;
220 * init operation: delay
225 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
226 #define INIT_DELAY_OP_OP_SHIFT 0
227 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
228 #define INIT_DELAY_OP_RESERVED_SHIFT 4
229 u32 delay /* delay in us */;
234 * init operation: if_mode
236 struct init_if_mode_op
239 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
240 #define INIT_IF_MODE_OP_OP_SHIFT 0
241 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
242 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
243 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */
244 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
246 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
251 * init operation: if_phase
253 struct init_if_phase_op
256 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
257 #define INIT_IF_PHASE_OP_OP_SHIFT 0
258 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */
259 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
260 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
261 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
262 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */
263 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
265 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
266 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
267 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
268 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
269 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
270 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
275 * init mode operators
279 INIT_MODE_OP_NOT /* init mode not operator */,
280 INIT_MODE_OP_OR /* init mode or operator */,
281 INIT_MODE_OP_AND /* init mode and operator */,
287 * init operation: raw
292 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
293 #define INIT_RAW_OP_OP_SHIFT 0
294 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
295 #define INIT_RAW_OP_PARAM1_SHIFT 4
296 u32 param2 /* Init param 2 */;
302 struct init_op_array_params
304 u16 size /* array size in dwords */;
305 u16 offset /* array start offset in dwords */;
309 * Write init operation arguments
311 union init_write_args
313 u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */;
314 u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */;
315 u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */;
316 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */;
320 * init operation: write
325 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */
326 #define INIT_WRITE_OP_OP_SHIFT 0
327 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */
328 #define INIT_WRITE_OP_SOURCE_SHIFT 4
329 #define INIT_WRITE_OP_RESERVED_MASK 0x1
330 #define INIT_WRITE_OP_RESERVED_SHIFT 7
331 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */
332 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
333 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */
334 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
335 union init_write_args args /* Write init operation arguments */;
339 * init operation: read
344 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */
345 #define INIT_READ_OP_OP_SHIFT 0
346 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */
347 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
348 #define INIT_READ_OP_RESERVED_MASK 0x1
349 #define INIT_READ_OP_RESERVED_SHIFT 8
350 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */
351 #define INIT_READ_OP_ADDRESS_SHIFT 9
352 u32 expected_val /* expected polling value, used only when polling is done */;
356 * Init operations union
360 struct init_raw_op raw /* raw init operation */;
361 struct init_write_op write /* write init operation */;
362 struct init_read_op read /* read init operation */;
363 struct init_if_mode_op if_mode /* if_mode init operation */;
364 struct init_if_phase_op if_phase /* if_phase init operation */;
365 struct init_callback_op callback /* callback init operation */;
366 struct init_delay_op delay /* delay init operation */;
372 * Init command operation types
376 INIT_OP_READ /* GRC read init command */,
377 INIT_OP_WRITE /* GRC write init command */,
378 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */,
379 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */,
380 INIT_OP_DELAY /* delay init command */,
381 INIT_OP_CALLBACK /* callback init command */,
391 INIT_POLL_NONE /* No polling */,
392 INIT_POLL_EQ /* init value is included in the init command */,
393 INIT_POLL_OR /* init value is all zeros */,
394 INIT_POLL_AND /* init value is an array of values */,
404 enum init_source_types
406 INIT_SRC_INLINE /* init value is included in the init command */,
407 INIT_SRC_ZEROS /* init value is all zeros */,
408 INIT_SRC_ARRAY /* init value is an array of values */,
409 INIT_SRC_RUNTIME /* init value is provided during runtime */,
410 MAX_INIT_SOURCE_TYPES
417 * Internal RAM Offsets macro data
421 u32 base /* RAM field offset */;
422 u16 m1 /* multiplier 1 */;
423 u16 m2 /* multiplier 2 */;
424 u16 m3 /* multiplier 3 */;
425 u16 size /* RAM field size */;
428 #endif /* __ECORE_HSI_INIT_TOOL__ */