2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __ECORE_HSI_IWARP__
32 #define __ECORE_HSI_IWARP__
33 /************************************************************************/
34 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */
35 /************************************************************************/
36 #include "ecore_hsi_rdma.h"
37 /************************************************************************/
38 /* Add include to common TCP target */
39 /************************************************************************/
40 #include "tcp_common.h"
42 /************************************************************************/
43 /* Add include to common iwarp target for both eCore and protocol iwarp driver */
44 /************************************************************************/
45 #include "iwarp_common.h"
48 * The iwarp storm context of Ystorm
50 struct ystorm_iwarp_conn_st_ctx
56 * The iwarp storm context of Pstorm
58 struct pstorm_iwarp_conn_st_ctx
64 * The iwarp storm context of Xstorm
66 struct xstorm_iwarp_conn_st_ctx
71 struct e4_xstorm_iwarp_conn_ag_ctx
73 u8 reserved0 /* cdu_validation */;
76 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
77 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
78 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
79 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
80 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 /* exist_in_qm2 */
81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
82 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
83 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
84 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
85 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
86 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
87 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
88 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
89 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
90 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
91 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
93 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
94 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
95 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
96 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
97 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
99 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
100 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
101 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
102 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
103 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
104 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
105 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
106 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
107 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */
108 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
111 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
113 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
114 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
115 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
116 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
117 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
120 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
122 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
124 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
126 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
129 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
131 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
132 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
133 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
134 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
135 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
137 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
138 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
139 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
140 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
141 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */
142 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
143 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
144 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
146 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */
147 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
148 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
149 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
150 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
151 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
152 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */
153 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
155 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
156 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
157 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */
158 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
159 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
160 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
161 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
162 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
163 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
164 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
166 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
167 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
168 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */
169 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
170 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
171 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
172 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
173 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
174 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
175 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
176 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
177 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
178 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
179 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
180 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
181 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
183 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
184 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
185 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
186 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
187 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
188 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
189 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
190 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
191 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */
192 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
193 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
194 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
195 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */
196 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
197 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
198 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
200 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
201 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
202 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */
203 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
204 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
205 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
206 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */
207 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
208 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
209 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
210 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
211 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
212 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
213 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
214 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */
215 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
217 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */
218 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
219 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
220 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
221 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */
222 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
223 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
224 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
225 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
226 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
227 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
228 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
229 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
230 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
231 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
232 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
234 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */
235 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
236 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
237 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
238 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
239 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
240 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
241 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
242 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */
243 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
244 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
245 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
246 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
247 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
248 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
249 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
251 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */
252 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
253 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */
254 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
255 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */
256 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
257 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */
258 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
259 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
260 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
261 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */
262 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
263 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
264 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
265 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
266 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
268 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
269 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
270 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
271 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
272 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
273 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
274 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 /* bit19 */
275 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
276 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit20 */
277 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
278 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit21 */
279 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
280 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
281 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
282 u8 byte2 /* byte2 */;
283 __le16 physical_q0 /* physical_q0 */;
284 __le16 physical_q1 /* physical_q1 */;
285 __le16 sq_comp_cons /* physical_q2 */;
286 __le16 sq_tx_cons /* word3 */;
287 __le16 sq_prod /* word4 */;
288 __le16 word5 /* word5 */;
289 __le16 conn_dpi /* conn_dpi */;
290 u8 byte3 /* byte3 */;
291 u8 byte4 /* byte4 */;
292 u8 byte5 /* byte5 */;
293 u8 byte6 /* byte6 */;
294 __le32 reg0 /* reg0 */;
295 __le32 reg1 /* reg1 */;
296 __le32 reg2 /* reg2 */;
297 __le32 more_to_send_seq /* reg3 */;
298 __le32 reg4 /* reg4 */;
299 __le32 rewinded_snd_max /* cf_array0 */;
300 __le32 rd_msn /* cf_array1 */;
301 __le16 irq_prod_via_msdm /* word7 */;
302 __le16 irq_cons /* word8 */;
303 __le16 hq_cons_th_or_mpa_data /* word9 */;
304 __le16 hq_cons /* word10 */;
305 __le32 atom_msn /* reg7 */;
306 __le32 orq_cons /* reg8 */;
307 __le32 orq_cons_th /* reg9 */;
308 u8 byte7 /* byte7 */;
309 u8 max_ord /* byte8 */;
310 u8 wqe_data_pad_bytes /* byte9 */;
311 u8 former_hq_prod /* byte10 */;
312 u8 irq_prod_via_msem /* byte11 */;
313 u8 byte12 /* byte12 */;
314 u8 max_pkt_pdu_size_lo /* byte13 */;
315 u8 max_pkt_pdu_size_hi /* byte14 */;
316 u8 byte15 /* byte15 */;
317 u8 e5_reserved /* e5_reserved */;
318 __le16 e5_reserved4 /* word11 */;
319 __le32 reg10 /* reg10 */;
320 __le32 reg11 /* reg11 */;
321 __le32 shared_queue_page_addr_lo /* reg12 */;
322 __le32 shared_queue_page_addr_hi /* reg13 */;
323 __le32 reg14 /* reg14 */;
324 __le32 reg15 /* reg15 */;
325 __le32 reg16 /* reg16 */;
326 __le32 reg17 /* reg17 */;
329 struct e4_tstorm_iwarp_conn_ag_ctx
331 u8 reserved0 /* cdu_validation */;
332 u8 state /* state */;
334 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
335 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
336 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
337 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
338 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
339 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
340 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */
341 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
342 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
343 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
344 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */
345 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
346 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
347 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
349 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */
350 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
351 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */
352 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
353 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
354 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
355 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
356 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
358 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
359 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
360 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
361 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
362 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
363 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
364 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
365 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
367 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */
368 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
369 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
370 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 2
371 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
372 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
373 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */
374 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
375 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf2en */
376 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
377 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */
378 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
380 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
381 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
382 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
383 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
384 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
385 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
386 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
387 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
388 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
389 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
390 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */
391 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
392 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
393 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 6
394 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
395 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
397 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
398 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
399 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
400 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
401 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
402 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
403 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
404 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
405 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
406 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
407 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */
408 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
409 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
410 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
411 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
412 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
413 __le32 reg0 /* reg0 */;
414 __le32 reg1 /* reg1 */;
415 __le32 unaligned_nxt_seq /* reg2 */;
416 __le32 reg3 /* reg3 */;
417 __le32 reg4 /* reg4 */;
418 __le32 reg5 /* reg5 */;
419 __le32 reg6 /* reg6 */;
420 __le32 reg7 /* reg7 */;
421 __le32 reg8 /* reg8 */;
422 u8 orq_cache_idx /* byte2 */;
423 u8 hq_prod /* byte3 */;
424 __le16 sq_tx_cons_th /* word0 */;
425 u8 orq_prod /* byte4 */;
426 u8 irq_cons /* byte5 */;
427 __le16 sq_tx_cons /* word1 */;
428 __le16 conn_dpi /* conn_dpi */;
429 __le16 rq_prod /* word3 */;
430 __le32 snd_seq /* reg9 */;
431 __le32 reg10 /* reg10 */;
435 * The iwarp storm context of Tstorm
437 struct tstorm_iwarp_conn_st_ctx
443 * The iwarp storm context of Mstorm
445 struct mstorm_iwarp_conn_st_ctx
451 * The iwarp storm context of Ustorm
453 struct ustorm_iwarp_conn_st_ctx
459 * iwarp connection context
461 struct iwarp_conn_context
463 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */;
464 struct regpair ystorm_st_padding[2] /* padding */;
465 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */;
466 struct regpair pstorm_st_padding[2] /* padding */;
467 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */;
468 struct regpair xstorm_st_padding[2] /* padding */;
469 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
470 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
471 struct timers_context timer_context /* timer context */;
472 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
473 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */;
474 struct regpair tstorm_st_padding[2] /* padding */;
475 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */;
476 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */;
481 * iWARP create QP params passed by driver to FW in CreateQP Request Ramrod
483 struct iwarp_create_qp_ramrod_data
486 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
487 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
488 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
489 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
490 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
491 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
492 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
493 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
494 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
495 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
496 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
497 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
498 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
499 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
500 u8 reserved1 /* Basic/Enhanced */;
505 struct regpair qp_handle_for_cqe /* For use in CQEs */;
506 struct rdma_srq_id srq_id;
507 __le32 cq_cid_for_sq /* Cid of the CQ that will be posted from SQ */;
508 __le32 cq_cid_for_rq /* Cid of the CQ that will be posted from RQ */;
510 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */;
511 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */;
517 * iWARP completion queue types
519 enum iwarp_eqe_async_opcode
521 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE /* Async completion oafter TCP 3-way handshake */,
522 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED /* Enhanced MPA reply arrived. Driver should either send RTR or reject */,
523 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE /* MPA Negotiations completed */,
524 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED /* Async completion that indicates to the driver that the CID can be re-used. */,
525 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED /* Async EQE indicating detection of an error/exception on a QP at Firmware */,
526 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE /* Async EQE indicating QP is in Error state. */,
527 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW /* Async EQE indicating CQ, whose handle is sent with this event, has overflowed */,
528 MAX_IWARP_EQE_ASYNC_OPCODE
532 struct iwarp_eqe_data_mpa_async_completion
534 __le16 ulp_data_len /* On active side, length of ULP Data, from peers MPA Connect Response */;
539 struct iwarp_eqe_data_tcp_async_completion
541 __le16 ulp_data_len /* On passive side, length of ULP Data, from peers active MPA Connect Request */;
542 u8 mpa_handshake_mode /* Negotiation type Basic/Enhanced */;
548 * iWARP completion queue types
550 enum iwarp_eqe_sync_opcode
552 IWARP_EVENT_TYPE_TCP_OFFLOAD=11 /* iWARP event queue response after option 2 offload Ramrod */,
553 IWARP_EVENT_TYPE_TCP_ABORT,
554 IWARP_EVENT_TYPE_MPA_OFFLOAD /* Synchronous completion for MPA offload Request */,
555 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
556 IWARP_EVENT_TYPE_CREATE_QP,
557 IWARP_EVENT_TYPE_QUERY_QP,
558 IWARP_EVENT_TYPE_MODIFY_QP,
559 IWARP_EVENT_TYPE_DESTROY_QP,
560 MAX_IWARP_EQE_SYNC_OPCODE
565 * iWARP EQE completion status
567 enum iwarp_fw_return_code
569 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET=5 /* Got invalid packet SYN/SYN-ACK */,
570 IWARP_CONN_ERROR_TCP_CONNECTION_RST /* Got RST during offload TCP connection */,
571 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT /* TCP connection setup timed out */,
572 IWARP_CONN_ERROR_MPA_ERROR_REJECT /* Got Reject in MPA reply. */,
573 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER /* Got MPA request with higher version that we support. */,
574 IWARP_CONN_ERROR_MPA_RST /* Got RST during MPA negotiation */,
575 IWARP_CONN_ERROR_MPA_FIN /* Got FIN during MPA negotiation */,
576 IWARP_CONN_ERROR_MPA_RTR_MISMATCH /* RTR mismatch detected when MPA reply arrived. */,
577 IWARP_CONN_ERROR_MPA_INSUF_IRD /* Insufficient IRD on the MPA reply that arrived. */,
578 IWARP_CONN_ERROR_MPA_INVALID_PACKET /* Incoming MPAp acket failed on FW verifications */,
579 IWARP_CONN_ERROR_MPA_LOCAL_ERROR /* Detected an internal error during MPA negotiation. */,
580 IWARP_CONN_ERROR_MPA_TIMEOUT /* MPA negotiation timed out. */,
581 IWARP_CONN_ERROR_MPA_TERMINATE /* Got Terminate during MPA negotiation. */,
582 IWARP_QP_IN_ERROR_GOOD_CLOSE /* LLP connection was closed gracefully - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */,
583 IWARP_QP_IN_ERROR_BAD_CLOSE /* LLP Connection was closed abortively - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */,
584 IWARP_EXCEPTION_DETECTED_LLP_CLOSED /* LLP has been disociated from the QP, although the TCP connection may not be closed yet - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
585 IWARP_EXCEPTION_DETECTED_LLP_RESET /* LLP has Reset (either because of an RST, or a bad-close condition) - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
586 IWARP_EXCEPTION_DETECTED_IRQ_FULL /* Peer sent more outstanding Read Requests than IRD - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
587 IWARP_EXCEPTION_DETECTED_RQ_EMPTY /* SEND request received with RQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
588 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT /* TCP Retransmissions timed out - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
589 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR /* Peers Remote Access caused error */,
590 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW /* CQ overflow detected */,
591 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC /* Local catastrophic error detected - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
592 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR /* Local Access error detected while responding - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */,
593 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR /* An operation/protocol error caused by Remote Consumer */,
594 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED /* Peer sent a TERMINATE message */,
595 MAX_IWARP_FW_RETURN_CODE
600 * unaligned opaque data received from LL2
602 struct iwarp_init_func_params
604 u8 ll2_ooo_q_index /* LL2 OOO queue id. The unaligned queue id will be + 1 */;
610 * iwarp func init ramrod data
612 struct iwarp_init_func_ramrod_data
614 struct rdma_init_func_ramrod_data rdma;
615 struct tcp_init_params tcp;
616 struct iwarp_init_func_params iwarp;
621 * iWARP QP - possible states to transition to
623 enum iwarp_modify_qp_new_state_type
625 IWARP_MODIFY_QP_STATE_CLOSING=1 /* graceful close */,
626 IWARP_MODIFY_QP_STATE_ERROR=2 /* abortive close, if LLP connection still exists */,
627 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
632 * iwarp modify qp responder ramrod data
634 struct iwarp_modify_qp_ramrod_data
636 __le16 transition_to_state;
638 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
639 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
640 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
641 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
642 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
643 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
644 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 /* change QP state as per transition_to_state field */
645 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
646 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 /* If set, the rdma_rd/wr/atomic_en should be updated */
647 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
648 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
649 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
656 * MPA params for Enhanced mode
665 * MPA host Address-Len for private data
667 struct mpa_ulp_buffer
675 * iWARP MPA offload params common to Basic and Enhanced modes
677 struct mpa_outgoing_params
680 u8 reject /* Valid only for passive side. */;
682 struct mpa_rq_params out_rq;
683 struct mpa_ulp_buffer outgoing_ulp_buffer /* ULP buffer populated by the host */;
687 * iWARP MPA offload params passed by driver to FW in MPA Offload Request Ramrod
689 struct iwarp_mpa_offload_ramrod_data
691 struct mpa_outgoing_params common;
693 u8 mode /* Basic/Enhanced */;
694 u8 tcp_connect_side /* Passive/Active. use enum tcp_connect_mode */;
696 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 /* (use enum mpa_rtr_type) */
697 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
698 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
699 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
701 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA reply */;
702 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */;
703 struct regpair handle_for_async /* a host cookie that will be echoed back with in every qp-specific async EQE */;
704 struct regpair shared_queue_addr /* Address of shared queue address that consist of SQ/RQ and FW internal queues (IRQ/ORQ/HQ) */;
705 u8 stats_counter_id /* Statistics counter ID to use */;
711 * iWARP TCP connection offload params passed by driver to FW
713 struct iwarp_offload_params
715 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA request */;
716 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */;
717 struct regpair handle_for_async /* host handle that will be echoed back with in every qp-specific async EQE */;
718 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */;
719 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */;
720 u8 stats_counter_id /* Statistics counter ID to use */;
721 u8 mpa_mode /* Basic/Enahnced. Used for a verification for incoming MPA request */;
727 * iWARP query QP output params
729 struct iwarp_query_qp_output_params
732 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
733 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
734 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
735 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
736 u8 reserved1[4] /* 64 bit alignment */;
741 * iWARP query QP ramrod data
743 struct iwarp_query_qp_ramrod_data
745 struct regpair output_params_addr;
750 * iWARP Ramrod Command IDs
752 enum iwarp_ramrod_cmd_id
754 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD=11 /* iWARP TCP connection offload ramrod */,
755 IWARP_RAMROD_CMD_ID_TCP_ABORT /* Abort TCP connection without changing the QP state. */,
756 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD /* iWARP MPA offload ramrod */,
757 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
758 IWARP_RAMROD_CMD_ID_CREATE_QP,
759 IWARP_RAMROD_CMD_ID_QUERY_QP,
760 IWARP_RAMROD_CMD_ID_MODIFY_QP,
761 IWARP_RAMROD_CMD_ID_DESTROY_QP,
762 MAX_IWARP_RAMROD_CMD_ID
767 * Per PF iWARP retransmit path statistics
769 struct iwarp_rxmit_stats_drv
771 struct regpair tx_go_to_slow_start_event_cnt /* Number of times slow start event occurred */;
772 struct regpair tx_fast_retransmit_event_cnt /* Number of times fast retransmit event occurred */;
777 * iWARP and TCP connection offload params passed by driver to FW in iWARP offload ramrod
779 struct iwarp_tcp_offload_ramrod_data
781 struct iwarp_offload_params iwarp /* iWARP connection offload params */;
782 struct tcp_offload_params_opt2 tcp /* tcp offload params */;
787 * iWARP MPA negotiation types
789 enum mpa_negotiation_mode
791 MPA_NEGOTIATION_TYPE_BASIC=1,
792 MPA_NEGOTIATION_TYPE_ENHANCED=2,
793 MAX_MPA_NEGOTIATION_MODE
800 * iWARP MPA Enhanced mode RTR types
804 MPA_RTR_TYPE_NONE=0 /* No RTR type */,
805 MPA_RTR_TYPE_ZERO_SEND=1,
806 MPA_RTR_TYPE_ZERO_WRITE=2,
807 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE=3,
808 MPA_RTR_TYPE_ZERO_READ=4,
809 MPA_RTR_TYPE_ZERO_SEND_AND_READ=5,
810 MPA_RTR_TYPE_ZERO_WRITE_AND_READ=6,
811 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ=7,
821 * unaligned opaque data received from LL2
823 struct unaligned_opaque_data
825 __le16 first_mpa_offset /* offset of first MPA byte that should be processed */;
826 u8 tcp_payload_offset /* offset of first the byte that comes after the last byte of the TCP Hdr */;
828 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 /* packet reached window right edge */
829 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
830 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x7F
831 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 1
839 struct e4_mstorm_iwarp_conn_ag_ctx
841 u8 reserved /* cdu_validation */;
842 u8 state /* state */;
844 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
845 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
846 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
847 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
848 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */
849 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
850 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
851 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
852 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
853 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
855 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */
856 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
857 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
858 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
859 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
860 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
861 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
862 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
863 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
864 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
865 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
866 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
867 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */
868 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
869 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
870 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
871 __le16 rcq_cons /* word0 */;
872 __le16 rcq_cons_th /* word1 */;
873 __le32 reg0 /* reg0 */;
874 __le32 reg1 /* reg1 */;
879 struct e4_ustorm_iwarp_conn_ag_ctx
881 u8 reserved /* cdu_validation */;
882 u8 byte1 /* state */;
884 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
885 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
886 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
887 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
888 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
889 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
890 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
891 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
892 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
893 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
895 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
896 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
897 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
898 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
899 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
900 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
901 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
902 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
904 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
905 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
906 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
907 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
908 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
909 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
910 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
911 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
912 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
913 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
914 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
915 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
916 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
917 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
918 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
919 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
921 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
922 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
923 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
924 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
925 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
926 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
927 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
928 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
929 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
930 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
931 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
932 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
933 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
934 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
935 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
936 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
937 u8 byte2 /* byte2 */;
938 u8 byte3 /* byte3 */;
939 __le16 word0 /* conn_dpi */;
940 __le16 word1 /* word1 */;
941 __le32 cq_cons /* reg0 */;
942 __le32 cq_se_prod /* reg1 */;
943 __le32 cq_prod /* reg2 */;
944 __le32 reg3 /* reg3 */;
945 __le16 word2 /* word2 */;
946 __le16 word3 /* word3 */;
951 struct e4_ystorm_iwarp_conn_ag_ctx
953 u8 byte0 /* cdu_validation */;
954 u8 byte1 /* state */;
956 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
957 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
958 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
959 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
960 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
961 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
962 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
963 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
964 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
965 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
967 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
968 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
969 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
970 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
971 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
972 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
973 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
974 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
975 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
976 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
977 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
978 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
979 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
980 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
981 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
982 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
983 u8 byte2 /* byte2 */;
984 u8 byte3 /* byte3 */;
985 __le16 word0 /* word0 */;
986 __le32 reg0 /* reg0 */;
987 __le32 reg1 /* reg1 */;
988 __le16 word1 /* word1 */;
989 __le16 word2 /* word2 */;
990 __le16 word3 /* word3 */;
991 __le16 word4 /* word4 */;
992 __le32 reg2 /* reg2 */;
993 __le32 reg3 /* reg3 */;
997 struct e5_mstorm_iwarp_conn_ag_ctx
999 u8 reserved /* cdu_validation */;
1000 u8 state_and_core_id /* state_and_core_id */;
1002 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1003 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1004 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1005 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
1006 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */
1007 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
1008 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1009 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
1010 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1011 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
1013 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */
1014 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
1015 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1016 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
1017 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1018 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
1019 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1020 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
1021 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1022 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
1023 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1024 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
1025 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */
1026 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
1027 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1028 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
1029 __le16 rcq_cons /* word0 */;
1030 __le16 rcq_cons_th /* word1 */;
1031 __le32 reg0 /* reg0 */;
1032 __le32 reg1 /* reg1 */;
1036 struct e5_tstorm_iwarp_conn_ag_ctx
1038 u8 reserved0 /* cdu_validation */;
1039 u8 state_and_core_id /* state_and_core_id */;
1041 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1042 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1043 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1044 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
1045 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1046 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
1047 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */
1048 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
1049 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1050 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
1051 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */
1052 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
1053 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1054 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
1056 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */
1057 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
1058 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */
1059 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
1060 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
1061 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
1062 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1063 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
1065 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1066 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
1067 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1068 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
1069 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1070 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
1071 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1072 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
1074 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */
1075 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1076 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1077 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 2
1078 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1079 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
1080 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */
1081 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
1082 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf2en */
1083 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
1084 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */
1085 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
1087 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1088 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
1089 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1090 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
1091 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1092 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
1093 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1094 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
1095 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1096 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
1097 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */
1098 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
1099 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1100 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 6
1101 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1102 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
1104 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1105 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
1106 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1107 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
1108 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1109 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
1110 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1111 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
1112 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1113 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
1114 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */
1115 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
1116 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1117 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
1118 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1119 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
1121 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
1122 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1123 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
1124 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1125 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
1126 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1127 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
1128 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
1129 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
1130 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
1131 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
1132 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
1133 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
1134 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
1135 u8 orq_cache_idx /* byte2 */;
1136 __le16 sq_tx_cons_th /* word0 */;
1137 __le32 reg0 /* reg0 */;
1138 __le32 reg1 /* reg1 */;
1139 __le32 unaligned_nxt_seq /* reg2 */;
1140 __le32 reg3 /* reg3 */;
1141 __le32 reg4 /* reg4 */;
1142 __le32 reg5 /* reg5 */;
1143 __le32 reg6 /* reg6 */;
1144 __le32 reg7 /* reg7 */;
1145 __le32 reg8 /* reg8 */;
1146 u8 hq_prod /* byte3 */;
1147 u8 orq_prod /* byte4 */;
1148 u8 irq_cons /* byte5 */;
1149 u8 e4_reserved8 /* byte6 */;
1150 __le16 sq_tx_cons /* word1 */;
1151 __le16 conn_dpi /* conn_dpi */;
1152 __le32 snd_seq /* reg9 */;
1153 __le16 rq_prod /* word3 */;
1154 __le16 e4_reserved9 /* word4 */;
1158 struct e5_ustorm_iwarp_conn_ag_ctx
1160 u8 reserved /* cdu_validation */;
1161 u8 byte1 /* state_and_core_id */;
1163 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1164 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1165 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1166 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
1167 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1168 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
1169 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1170 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
1171 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1172 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
1174 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1175 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
1176 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1177 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
1178 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1179 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
1180 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1181 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
1183 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1184 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
1185 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1186 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
1187 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1188 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
1189 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1190 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
1191 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
1192 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1193 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
1194 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
1195 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1196 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
1197 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
1198 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
1200 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
1201 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
1202 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1203 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
1204 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1205 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
1206 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1207 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
1208 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1209 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
1210 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1211 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
1212 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1213 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
1214 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1215 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
1217 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
1218 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1219 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
1220 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1221 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
1222 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1223 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
1224 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
1225 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
1226 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
1227 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
1228 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
1229 u8 byte2 /* byte2 */;
1230 __le16 word0 /* conn_dpi */;
1231 __le16 word1 /* word1 */;
1232 __le32 cq_cons /* reg0 */;
1233 __le32 cq_se_prod /* reg1 */;
1234 __le32 cq_prod /* reg2 */;
1235 __le32 reg3 /* reg3 */;
1236 __le16 word2 /* word2 */;
1237 __le16 word3 /* word3 */;
1241 struct e5_xstorm_iwarp_conn_ag_ctx
1243 u8 reserved0 /* cdu_validation */;
1244 u8 state_and_core_id /* state_and_core_id */;
1246 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1247 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1248 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
1249 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
1250 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */
1251 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_SHIFT 2
1252 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1253 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1254 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1255 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
1256 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
1257 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
1258 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
1259 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
1260 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
1261 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
1263 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
1264 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
1265 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
1266 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
1267 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1268 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
1269 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1270 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
1271 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1272 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
1273 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
1274 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
1275 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1276 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
1277 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */
1278 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
1280 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1281 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
1282 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1283 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
1284 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1285 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
1286 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
1287 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
1289 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1290 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
1291 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1292 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
1293 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1294 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
1295 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1296 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
1298 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1299 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
1300 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1301 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
1302 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1303 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
1304 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1305 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
1307 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1308 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
1309 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1310 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
1311 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */
1312 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
1313 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1314 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
1316 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */
1317 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
1318 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
1319 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
1320 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
1321 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
1322 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */
1323 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
1325 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
1326 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1327 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */
1328 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
1329 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1330 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1331 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1332 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
1333 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1334 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
1336 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1337 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
1338 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */
1339 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
1340 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1341 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
1342 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1343 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
1344 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1345 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
1346 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1347 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
1348 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1349 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
1350 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1351 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
1353 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1354 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
1355 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1356 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
1357 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1358 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
1359 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1360 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
1361 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */
1362 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
1363 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1364 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
1365 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */
1366 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
1367 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1368 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
1370 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1371 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
1372 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */
1373 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
1374 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
1375 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
1376 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */
1377 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
1378 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1379 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1380 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1381 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
1382 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1383 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
1384 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */
1385 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
1387 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */
1388 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
1389 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1390 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
1391 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */
1392 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
1393 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1394 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
1395 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1396 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
1397 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1398 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
1399 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1400 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1401 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
1402 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
1404 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */
1405 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
1406 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
1407 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
1408 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1409 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1410 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1411 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1412 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */
1413 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
1414 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1415 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
1416 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
1417 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
1418 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
1419 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
1421 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */
1422 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
1423 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */
1424 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
1425 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */
1426 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
1427 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */
1428 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
1429 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1430 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1431 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */
1432 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
1433 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1434 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1435 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1436 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1438 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
1439 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
1440 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1441 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
1442 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1443 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
1444 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
1445 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_SHIFT 4
1446 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_MASK 0x1 /* bit21 */
1447 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_SHIFT 5
1448 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
1449 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
1450 u8 byte2 /* byte2 */;
1451 __le16 physical_q0 /* physical_q0 */;
1452 __le16 physical_q1 /* physical_q1 */;
1453 __le16 sq_comp_cons /* physical_q2 */;
1454 __le16 sq_tx_cons /* word3 */;
1455 __le16 sq_prod /* word4 */;
1456 __le16 word5 /* word5 */;
1457 __le16 conn_dpi /* conn_dpi */;
1458 u8 byte3 /* byte3 */;
1459 u8 byte4 /* byte4 */;
1460 u8 byte5 /* byte5 */;
1461 u8 byte6 /* byte6 */;
1462 __le32 reg0 /* reg0 */;
1463 __le32 reg1 /* reg1 */;
1464 __le32 reg2 /* reg2 */;
1465 __le32 more_to_send_seq /* reg3 */;
1466 __le32 reg4 /* reg4 */;
1467 __le32 rewinded_snd_max /* cf_array0 */;
1468 __le32 rd_msn /* cf_array1 */;
1470 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */
1471 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1472 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */
1473 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1474 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */
1475 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1476 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */
1477 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
1478 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */
1479 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
1480 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */
1481 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
1482 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */
1483 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
1484 u8 byte7 /* byte7 */;
1485 __le16 irq_prod_via_msdm /* word7 */;
1486 __le16 irq_cons /* word8 */;
1487 __le16 hq_cons_th_or_mpa_data /* word9 */;
1488 __le16 hq_cons /* word10 */;
1489 __le16 tx_rdma_edpm_usg_cnt /* word11 */;
1490 __le32 atom_msn /* reg7 */;
1491 __le32 orq_cons /* reg8 */;
1492 __le32 orq_cons_th /* reg9 */;
1493 u8 max_ord /* byte8 */;
1494 u8 wqe_data_pad_bytes /* byte9 */;
1495 u8 former_hq_prod /* byte10 */;
1496 u8 irq_prod_via_msem /* byte11 */;
1497 u8 byte12 /* byte12 */;
1498 u8 max_pkt_pdu_size_lo /* byte13 */;
1499 u8 max_pkt_pdu_size_hi /* byte14 */;
1500 u8 byte15 /* byte15 */;
1501 __le32 reg10 /* reg10 */;
1502 __le32 reg11 /* reg11 */;
1503 __le32 reg12 /* reg12 */;
1504 __le32 shared_queue_page_addr_lo /* reg13 */;
1505 __le32 shared_queue_page_addr_hi /* reg14 */;
1506 __le32 reg15 /* reg15 */;
1507 __le32 reg16 /* reg16 */;
1508 __le32 reg17 /* reg17 */;
1512 struct e5_ystorm_iwarp_conn_ag_ctx
1514 u8 byte0 /* cdu_validation */;
1515 u8 byte1 /* state_and_core_id */;
1517 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1518 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
1519 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1520 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
1521 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1522 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
1523 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1524 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
1525 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1526 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
1528 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1529 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
1530 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1531 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
1532 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1533 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
1534 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1535 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
1536 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1537 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
1538 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1539 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
1540 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1541 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
1542 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1543 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
1544 u8 byte2 /* byte2 */;
1545 u8 byte3 /* byte3 */;
1546 __le16 word0 /* word0 */;
1547 __le32 reg0 /* reg0 */;
1548 __le32 reg1 /* reg1 */;
1549 __le16 word1 /* word1 */;
1550 __le16 word2 /* word2 */;
1551 __le16 word3 /* word3 */;
1552 __le16 word4 /* word4 */;
1553 __le32 reg2 /* reg2 */;
1554 __le32 reg3 /* reg3 */;
1557 #endif /* __ECORE_HSI_IWARP__ */