2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __ECORE_HSI_RDMA__
32 #define __ECORE_HSI_RDMA__
33 /************************************************************************/
34 /* Add include to common rdma target for both eCore and protocol rdma driver */
35 /************************************************************************/
36 #include "rdma_common.h"
39 * The rdma task context of Mstorm
41 struct ystorm_rdma_task_st_ctx
43 struct regpair temp[4];
46 struct e4_ystorm_rdma_task_ag_ctx
48 u8 reserved /* cdu_validation */;
50 __le16 msem_ctx_upd_seq /* icid */;
52 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
53 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
54 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
55 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
56 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
57 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
58 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
59 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
60 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
61 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
64 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
66 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
67 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
68 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
69 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
70 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
71 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
72 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
74 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
75 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
76 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
77 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
78 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
79 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
80 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
81 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
82 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
83 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
84 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
85 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
86 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
87 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
88 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
89 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
91 __le32 mw_cnt /* reg0 */;
92 u8 ref_cnt_seq /* byte3 */;
93 u8 ctx_upd_seq /* byte4 */;
94 __le16 dif_flags /* word1 */;
95 __le16 tx_ref_count /* word2 */;
96 __le16 last_used_ltid /* word3 */;
97 __le16 parent_mr_lo /* word4 */;
98 __le16 parent_mr_hi /* word5 */;
99 __le32 fbo_lo /* reg1 */;
100 __le32 fbo_hi /* reg2 */;
103 struct e4_mstorm_rdma_task_ag_ctx
105 u8 reserved /* cdu_validation */;
106 u8 byte1 /* state */;
107 __le16 icid /* icid */;
109 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
110 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
111 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
112 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
113 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
114 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
115 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
116 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
117 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
118 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
121 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
123 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
124 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
125 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
126 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
127 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
128 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
129 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
131 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
132 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
133 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
134 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
135 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
136 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
137 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
138 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
139 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
140 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
141 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
142 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
143 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
144 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
145 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
146 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
148 __le32 mw_cnt /* reg0 */;
149 u8 ref_cnt_seq /* byte3 */;
150 u8 ctx_upd_seq /* byte4 */;
151 __le16 dif_flags /* word1 */;
152 __le16 tx_ref_count /* word2 */;
153 __le16 last_used_ltid /* word3 */;
154 __le16 parent_mr_lo /* word4 */;
155 __le16 parent_mr_hi /* word5 */;
156 __le32 fbo_lo /* reg1 */;
157 __le32 fbo_hi /* reg2 */;
161 * The roce task context of Mstorm
163 struct mstorm_rdma_task_st_ctx
165 struct regpair temp[4];
169 * The roce task context of Ustorm
171 struct ustorm_rdma_task_st_ctx
173 struct regpair temp[2];
176 struct e4_ustorm_rdma_task_ag_ctx
178 u8 reserved /* cdu_validation */;
179 u8 byte1 /* state */;
180 __le16 icid /* icid */;
182 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
183 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
184 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
185 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
186 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */
187 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
188 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
192 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
194 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
195 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
196 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
197 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */
198 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
200 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */
201 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
202 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */
203 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
204 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */
205 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
206 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
207 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
208 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */
209 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
210 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
211 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
212 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
213 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
214 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
215 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
217 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
218 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
219 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
220 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
221 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
222 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
223 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
224 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
225 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */
226 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
227 __le32 dif_err_intervals /* reg0 */;
228 __le32 dif_error_1st_interval /* reg1 */;
229 __le32 reg2 /* reg2 */;
230 __le32 dif_runt_value /* reg3 */;
231 __le32 reg4 /* reg4 */;
232 __le32 reg5 /* reg5 */;
238 struct e4_rdma_task_context
240 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
241 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
242 struct tdif_task_context tdif_context /* tdif context */;
243 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
244 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
245 struct rdif_task_context rdif_context /* rdif context */;
246 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
247 struct regpair ustorm_st_padding[2] /* padding */;
248 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
252 struct e5_ystorm_rdma_task_ag_ctx
254 u8 reserved /* cdu_validation */;
255 u8 byte1 /* state_and_core_id */;
256 __le16 msem_ctx_upd_seq /* icid */;
258 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
259 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
260 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
261 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
262 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
263 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
264 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
265 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
266 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
267 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
269 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
270 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
271 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
272 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
273 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
274 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
275 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
276 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
277 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
278 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
280 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
281 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
282 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
283 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
284 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
285 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
286 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
287 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
288 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
289 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
290 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
291 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
292 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
293 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
294 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
295 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
297 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */
298 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
299 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
300 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
301 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
302 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
303 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */
304 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
305 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */
306 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
307 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */
308 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
309 __le32 mw_cnt /* reg0 */;
311 u8 ref_cnt_seq /* byte3 */;
312 u8 ctx_upd_seq /* byte4 */;
313 u8 e4_reserved7 /* byte5 */;
314 __le16 dif_flags /* word1 */;
315 __le16 tx_ref_count /* word2 */;
316 __le16 last_used_ltid /* word3 */;
317 __le16 parent_mr_lo /* word4 */;
318 __le16 parent_mr_hi /* word5 */;
319 __le16 e4_reserved8 /* word6 */;
320 __le32 fbo_lo /* reg1 */;
323 struct e5_mstorm_rdma_task_ag_ctx
325 u8 reserved /* cdu_validation */;
326 u8 byte1 /* state_and_core_id */;
327 __le16 icid /* icid */;
329 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
330 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
331 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
332 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
333 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
334 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
335 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
336 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
337 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
338 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
340 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
341 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
342 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
343 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
344 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
345 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
346 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
347 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
348 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
349 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
351 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
352 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
353 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
354 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
355 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
356 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
357 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
358 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
359 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
360 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
361 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
362 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
363 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
364 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
365 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
366 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
368 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */
369 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
370 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
371 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
372 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
373 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
374 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */
375 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
376 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */
377 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
378 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */
379 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
380 __le32 mw_cnt /* reg0 */;
382 u8 ref_cnt_seq /* byte3 */;
383 u8 ctx_upd_seq /* byte4 */;
384 u8 e4_reserved7 /* byte5 */;
385 __le16 dif_flags /* regpair0 */;
386 __le16 tx_ref_count /* word2 */;
387 __le16 last_used_ltid /* word3 */;
388 __le16 parent_mr_lo /* word4 */;
389 __le16 parent_mr_hi /* regpair1 */;
390 __le16 e4_reserved8 /* word6 */;
391 __le32 fbo_lo /* reg1 */;
394 struct e5_ustorm_rdma_task_ag_ctx
396 u8 reserved /* cdu_validation */;
397 u8 byte1 /* state_and_core_id */;
398 __le16 icid /* icid */;
400 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
401 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
402 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
403 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
404 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */
405 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
406 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
407 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
409 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
410 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
411 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
412 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
413 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
414 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
415 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */
416 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
418 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */
419 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
420 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */
421 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
422 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */
423 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
424 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
425 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
426 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */
427 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
428 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
429 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
430 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
431 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
432 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
433 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
435 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
436 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
437 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
438 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
439 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
440 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
441 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
442 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
443 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
444 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4
445 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
446 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5
447 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */
448 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6
449 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */
450 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7
452 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */
453 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0
454 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */
455 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2
456 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */
457 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3
458 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */
459 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
460 u8 byte2 /* byte2 */;
461 u8 byte3 /* byte3 */;
462 u8 e4_reserved8 /* byte4 */;
463 __le32 dif_err_intervals /* dif_err_intervals */;
464 __le32 dif_error_1st_interval /* dif_error_1st_interval */;
465 __le32 reg2 /* reg2 */;
466 __le32 dif_runt_value /* reg3 */;
467 __le32 reg4 /* reg4 */;
473 struct e5_rdma_task_context
475 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
476 struct e5_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
477 struct tdif_task_context tdif_context /* tdif context */;
478 struct e5_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
479 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
480 struct rdif_task_context rdif_context /* rdif context */;
481 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
482 struct regpair ustorm_st_padding[2] /* padding */;
483 struct e5_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
489 * rdma function init ramrod data
491 struct rdma_close_func_ramrod_data
495 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
502 * rdma function init CNQ parameters
504 struct rdma_cnq_params
506 __le16 sb_num /* Status block number used by the queue */;
507 u8 sb_index /* Status block index used by the queue */;
508 u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
510 struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
511 __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
517 * rdma create cq ramrod data
519 struct rdma_create_cq_ramrod_data
521 struct regpair cq_handle;
522 struct regpair pbl_addr;
524 __le16 pbl_num_pages;
528 u8 pbl_log_page_size;
530 __le16 int_timeout /* Timeout used for interrupt moderation */;
536 * rdma deregister tid ramrod data
538 struct rdma_deregister_tid_ramrod_data
546 * rdma destroy cq output params
548 struct rdma_destroy_cq_output_params
550 __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
557 * rdma destroy cq ramrod data
559 struct rdma_destroy_cq_ramrod_data
561 struct regpair output_params_addr;
566 * RDMA slow path EQ cmd IDs
568 enum rdma_event_opcode
571 RDMA_EVENT_FUNC_INIT,
572 RDMA_EVENT_FUNC_CLOSE,
573 RDMA_EVENT_REGISTER_MR,
574 RDMA_EVENT_DEREGISTER_MR,
575 RDMA_EVENT_CREATE_CQ,
576 RDMA_EVENT_RESIZE_CQ,
577 RDMA_EVENT_DESTROY_CQ,
578 RDMA_EVENT_CREATE_SRQ,
579 RDMA_EVENT_MODIFY_SRQ,
580 RDMA_EVENT_DESTROY_SRQ,
581 MAX_RDMA_EVENT_OPCODE
586 * RDMA FW return code for slow path ramrods
588 enum rdma_fw_return_code
591 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
592 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
593 RDMA_RETURN_RESIZE_CQ_ERR,
594 RDMA_RETURN_NIG_DRAIN_REQ,
595 MAX_RDMA_FW_RETURN_CODE
600 * rdma function init header
602 struct rdma_init_func_hdr
604 u8 cnq_start_offset /* First RDMA CNQ */;
605 u8 num_cnqs /* Number of CNQs */;
606 u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
607 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
614 * rdma function init ramrod data
616 struct rdma_init_func_ramrod_data
618 struct rdma_init_func_hdr params_header;
619 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
624 * RDMA ramrod command IDs
626 enum rdma_ramrod_cmd_id
629 RDMA_RAMROD_FUNC_INIT,
630 RDMA_RAMROD_FUNC_CLOSE,
631 RDMA_RAMROD_REGISTER_MR,
632 RDMA_RAMROD_DEREGISTER_MR,
633 RDMA_RAMROD_CREATE_CQ,
634 RDMA_RAMROD_RESIZE_CQ,
635 RDMA_RAMROD_DESTROY_CQ,
636 RDMA_RAMROD_CREATE_SRQ,
637 RDMA_RAMROD_MODIFY_SRQ,
638 RDMA_RAMROD_DESTROY_SRQ,
639 MAX_RDMA_RAMROD_CMD_ID
644 * rdma register tid ramrod data
646 struct rdma_register_tid_ramrod_data
649 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF
650 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0
651 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
652 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18
653 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
654 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23
655 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
656 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24
657 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
658 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25
659 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
660 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26
661 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
662 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27
663 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
664 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28
665 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
666 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29
667 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
668 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30
669 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
670 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31
672 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
673 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
674 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
675 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
677 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
678 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
679 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */
680 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
681 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
682 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
685 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
688 __le32 length_lo /* lower 32 bits of the registered MR length. */;
692 struct regpair pbl_base;
693 struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
694 struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
700 * rdma resize cq output params
702 struct rdma_resize_cq_output_params
704 __le32 old_cq_cons /* cq consumer value on old PBL */;
705 __le32 old_cq_prod /* cq producer value on old PBL */;
710 * rdma resize cq ramrod data
712 struct rdma_resize_cq_ramrod_data
715 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
716 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
717 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
718 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
719 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
720 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
721 u8 pbl_log_page_size;
722 __le16 pbl_num_pages;
724 struct regpair pbl_addr;
725 struct regpair output_params_addr;
730 * The rdma storm context of Mstorm
732 struct rdma_srq_context
734 struct regpair temp[8];
739 * rdma create qp requester ramrod data
741 struct rdma_srq_create_ramrod_data
743 struct regpair pbl_base_addr /* SRQ PBL base address */;
744 __le16 pages_in_srq_pbl /* Number of pages in PBL */;
746 struct rdma_srq_id srq_id /* SRQ Index */;
747 __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
750 struct regpair producers_addr /* SRQ PBL base address */;
755 * rdma create qp requester ramrod data
757 struct rdma_srq_destroy_ramrod_data
759 struct rdma_srq_id srq_id /* SRQ Index */;
765 * rdma create qp requester ramrod data
767 struct rdma_srq_modify_ramrod_data
769 struct rdma_srq_id srq_id /* SRQ Index */;
775 * RDMA Tid type enumeration (for register_tid ramrod)
779 RDMA_TID_REGISTERED_MR,
789 struct E4XstormRoceConnAgCtxDqExtLdPart
791 u8 reserved0 /* cdu_validation */;
792 u8 state /* state */;
794 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
795 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
796 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */
797 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
798 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */
799 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
800 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
801 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
802 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */
803 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
804 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */
805 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
806 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */
807 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
808 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */
809 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
811 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */
812 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
813 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */
814 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
815 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */
816 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
817 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */
818 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
819 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */
820 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
821 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */
822 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
823 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */
824 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
825 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */
826 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
828 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */
829 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
830 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */
831 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
832 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */
833 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
834 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */
835 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
837 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */
838 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
839 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */
840 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
841 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */
842 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
843 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
844 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
846 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */
847 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
848 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */
849 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
850 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */
851 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
852 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */
853 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
855 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */
856 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
857 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */
858 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
859 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */
860 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
861 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */
862 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
864 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */
865 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
866 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */
867 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
868 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */
869 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
870 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */
871 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
873 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */
874 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
875 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */
876 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
877 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */
878 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
879 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */
880 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
881 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */
882 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
884 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */
885 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
886 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */
887 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
888 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */
889 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
890 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */
891 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
892 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */
893 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
894 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
895 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
896 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */
897 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
898 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */
899 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
901 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */
902 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
903 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */
904 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
905 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */
906 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
907 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */
908 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
909 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */
910 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
911 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */
912 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
913 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */
914 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
915 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */
916 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
918 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */
919 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
920 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */
921 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
922 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */
923 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
924 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */
925 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
926 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */
927 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
928 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */
929 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
930 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */
931 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
932 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */
933 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
935 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */
936 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
937 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */
938 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
939 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */
940 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
941 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */
942 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
943 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */
944 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
945 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */
946 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
947 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */
948 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
949 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */
950 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
952 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */
953 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
954 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */
955 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
956 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */
957 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
958 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */
959 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
960 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */
961 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
962 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */
963 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
964 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */
965 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
966 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */
967 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
969 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */
970 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
971 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */
972 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
973 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */
974 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
975 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */
976 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
977 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */
978 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
979 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */
980 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
981 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */
982 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
983 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */
984 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
986 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */
987 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
988 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */
989 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
990 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */
991 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
992 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */
993 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
994 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
995 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
996 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */
997 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
998 u8 byte2 /* byte2 */;
999 __le16 physical_q0 /* physical_q0 */;
1000 __le16 word1 /* physical_q1 */;
1001 __le16 word2 /* physical_q2 */;
1002 __le16 word3 /* word3 */;
1003 __le16 word4 /* word4 */;
1004 __le16 word5 /* word5 */;
1005 __le16 conn_dpi /* conn_dpi */;
1006 u8 byte3 /* byte3 */;
1007 u8 byte4 /* byte4 */;
1008 u8 byte5 /* byte5 */;
1009 u8 byte6 /* byte6 */;
1010 __le32 reg0 /* reg0 */;
1011 __le32 reg1 /* reg1 */;
1012 __le32 reg2 /* reg2 */;
1013 __le32 snd_nxt_psn /* reg3 */;
1014 __le32 reg4 /* reg4 */;
1018 struct e4_mstorm_rdma_conn_ag_ctx
1020 u8 byte0 /* cdu_validation */;
1021 u8 byte1 /* state */;
1023 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1024 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1025 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1026 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1027 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1028 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1029 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1030 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1031 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1032 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1034 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1035 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1036 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1037 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1038 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1039 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1040 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1041 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1042 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1043 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1044 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1045 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1046 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1047 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1048 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1049 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1050 __le16 word0 /* word0 */;
1051 __le16 word1 /* word1 */;
1052 __le32 reg0 /* reg0 */;
1053 __le32 reg1 /* reg1 */;
1058 struct e4_tstorm_rdma_conn_ag_ctx
1060 u8 reserved0 /* cdu_validation */;
1061 u8 byte1 /* state */;
1063 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1064 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1065 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1066 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1067 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1068 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1069 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1070 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
1071 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1072 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1073 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1074 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1075 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1076 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
1078 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1079 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
1080 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1081 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
1082 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
1083 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
1084 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1085 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1087 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1088 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1089 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1090 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
1091 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1092 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
1093 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1094 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
1096 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1097 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
1098 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1099 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
1100 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1101 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
1102 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1103 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
1104 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1105 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
1106 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1107 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1109 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1110 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1111 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1112 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1113 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1114 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
1115 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1116 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
1117 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1118 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
1119 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1120 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
1121 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1122 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
1123 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1124 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
1126 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1127 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
1128 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1129 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1130 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1131 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1132 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1133 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1134 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1135 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1136 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1137 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1138 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1139 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1140 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1141 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1142 __le32 reg0 /* reg0 */;
1143 __le32 reg1 /* reg1 */;
1144 __le32 reg2 /* reg2 */;
1145 __le32 reg3 /* reg3 */;
1146 __le32 reg4 /* reg4 */;
1147 __le32 reg5 /* reg5 */;
1148 __le32 reg6 /* reg6 */;
1149 __le32 reg7 /* reg7 */;
1150 __le32 reg8 /* reg8 */;
1151 u8 byte2 /* byte2 */;
1152 u8 byte3 /* byte3 */;
1153 __le16 word0 /* word0 */;
1154 u8 byte4 /* byte4 */;
1155 u8 byte5 /* byte5 */;
1156 __le16 word1 /* word1 */;
1157 __le16 word2 /* conn_dpi */;
1158 __le16 word3 /* word3 */;
1159 __le32 reg9 /* reg9 */;
1160 __le32 reg10 /* reg10 */;
1164 struct e4_tstorm_rdma_task_ag_ctx
1166 u8 byte0 /* cdu_validation */;
1167 u8 byte1 /* state */;
1168 __le16 word0 /* icid */;
1170 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */
1171 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1172 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1173 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
1174 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1175 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
1176 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1177 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
1178 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1179 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
1181 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1182 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
1183 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1184 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
1185 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1186 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
1187 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1188 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
1189 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1190 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
1192 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1193 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
1194 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */
1195 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
1196 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */
1197 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
1198 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */
1199 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
1201 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */
1202 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
1203 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1204 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
1205 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1206 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
1207 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1208 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
1209 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1210 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
1211 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1212 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
1213 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1214 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
1216 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1217 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
1218 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1219 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
1220 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1221 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1222 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1223 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1224 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1225 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1226 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1227 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1228 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1229 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1230 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1231 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1232 u8 byte2 /* byte2 */;
1233 __le16 word1 /* word1 */;
1234 __le32 reg0 /* reg0 */;
1235 u8 byte3 /* byte3 */;
1236 u8 byte4 /* byte4 */;
1237 __le16 word2 /* word2 */;
1238 __le16 word3 /* word3 */;
1239 __le16 word4 /* word4 */;
1240 __le32 reg1 /* reg1 */;
1241 __le32 reg2 /* reg2 */;
1245 struct e4_ustorm_rdma_conn_ag_ctx
1247 u8 reserved /* cdu_validation */;
1248 u8 byte1 /* state */;
1250 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1251 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1252 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1253 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1254 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */
1255 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
1256 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1257 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1258 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1259 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1261 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1262 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
1263 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1264 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
1265 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1266 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
1267 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1268 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
1270 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */
1271 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1272 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1273 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1274 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1275 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1276 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1277 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
1278 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
1279 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1280 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
1281 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
1282 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1283 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
1284 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
1285 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
1287 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
1288 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
1289 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1290 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1291 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1292 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1293 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1294 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1295 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1296 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1297 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1298 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1299 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1300 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1301 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1302 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1303 u8 byte2 /* byte2 */;
1304 u8 byte3 /* byte3 */;
1305 __le16 conn_dpi /* conn_dpi */;
1306 __le16 word1 /* word1 */;
1307 __le32 cq_cons /* reg0 */;
1308 __le32 cq_se_prod /* reg1 */;
1309 __le32 cq_prod /* reg2 */;
1310 __le32 reg3 /* reg3 */;
1311 __le16 int_timeout /* word2 */;
1312 __le16 word3 /* word3 */;
1317 struct e4_xstorm_rdma_conn_ag_ctx
1319 u8 reserved0 /* cdu_validation */;
1320 u8 state /* state */;
1322 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1323 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1324 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1325 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1326 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */
1327 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1328 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1329 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1330 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1331 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1332 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */
1333 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1334 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
1335 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
1336 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
1337 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
1339 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
1340 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
1341 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
1342 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
1343 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1344 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
1345 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1346 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
1347 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1348 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
1349 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */
1350 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
1351 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1352 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
1353 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1354 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
1356 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1357 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
1358 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1359 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
1360 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1361 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
1362 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1363 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
1365 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1366 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
1367 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1368 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
1369 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1370 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
1371 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
1372 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1374 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1375 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
1376 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1377 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
1378 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1379 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
1380 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1381 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
1383 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1384 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
1385 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1386 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
1387 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1388 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
1389 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1390 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
1392 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
1393 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
1394 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
1395 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
1396 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
1397 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
1398 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
1399 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
1401 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
1402 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
1403 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
1404 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
1405 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1406 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1407 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1408 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
1409 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1410 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
1412 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1413 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
1414 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1415 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
1416 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1417 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
1418 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1419 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
1420 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1421 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
1422 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
1423 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
1424 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1425 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
1426 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1427 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
1429 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1430 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
1431 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1432 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
1433 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1434 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
1435 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1436 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
1437 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
1438 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
1439 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1440 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
1441 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
1442 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
1443 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1444 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
1446 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1447 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
1448 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
1449 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
1450 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
1451 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
1452 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
1453 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
1454 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1455 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1456 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1457 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
1458 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1459 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
1460 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1461 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
1463 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1464 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
1465 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1466 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
1467 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1468 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
1469 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1470 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
1471 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1472 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
1473 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1474 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
1475 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1476 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1477 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
1478 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
1480 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
1481 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
1482 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
1483 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
1484 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1485 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1486 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1487 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1488 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
1489 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
1490 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1491 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
1492 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
1493 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
1494 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
1495 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
1497 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
1498 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
1499 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
1500 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
1501 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
1502 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1503 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
1504 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1505 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1506 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1507 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
1508 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1509 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1510 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1511 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1512 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1514 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */
1515 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
1516 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1517 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
1518 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1519 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
1520 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
1521 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
1522 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
1523 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1524 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
1525 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
1526 u8 byte2 /* byte2 */;
1527 __le16 physical_q0 /* physical_q0 */;
1528 __le16 word1 /* physical_q1 */;
1529 __le16 word2 /* physical_q2 */;
1530 __le16 word3 /* word3 */;
1531 __le16 word4 /* word4 */;
1532 __le16 word5 /* word5 */;
1533 __le16 conn_dpi /* conn_dpi */;
1534 u8 byte3 /* byte3 */;
1535 u8 byte4 /* byte4 */;
1536 u8 byte5 /* byte5 */;
1537 u8 byte6 /* byte6 */;
1538 __le32 reg0 /* reg0 */;
1539 __le32 reg1 /* reg1 */;
1540 __le32 reg2 /* reg2 */;
1541 __le32 snd_nxt_psn /* reg3 */;
1542 __le32 reg4 /* reg4 */;
1543 __le32 reg5 /* cf_array0 */;
1544 __le32 reg6 /* cf_array1 */;
1548 struct e4_ystorm_rdma_conn_ag_ctx
1550 u8 byte0 /* cdu_validation */;
1551 u8 byte1 /* state */;
1553 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1554 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1555 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1556 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1557 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1558 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1559 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1560 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1561 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1562 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1564 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1565 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1566 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1567 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1568 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1569 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1570 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1571 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1572 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1573 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1574 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1575 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1576 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1577 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1578 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1579 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1580 u8 byte2 /* byte2 */;
1581 u8 byte3 /* byte3 */;
1582 __le16 word0 /* word0 */;
1583 __le32 reg0 /* reg0 */;
1584 __le32 reg1 /* reg1 */;
1585 __le16 word1 /* word1 */;
1586 __le16 word2 /* word2 */;
1587 __le16 word3 /* word3 */;
1588 __le16 word4 /* word4 */;
1589 __le32 reg2 /* reg2 */;
1590 __le32 reg3 /* reg3 */;
1595 struct e5_mstorm_rdma_conn_ag_ctx
1597 u8 byte0 /* cdu_validation */;
1598 u8 byte1 /* state_and_core_id */;
1600 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1601 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1602 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1603 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1604 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1605 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1606 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1607 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1608 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1609 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1611 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1612 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1613 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1614 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1615 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1616 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1617 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1618 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1619 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1620 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1621 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1622 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1623 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1624 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1625 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1626 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1627 __le16 word0 /* word0 */;
1628 __le16 word1 /* word1 */;
1629 __le32 reg0 /* reg0 */;
1630 __le32 reg1 /* reg1 */;
1635 struct e5_tstorm_rdma_conn_ag_ctx
1637 u8 reserved0 /* cdu_validation */;
1638 u8 byte1 /* state_and_core_id */;
1640 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1641 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1642 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1643 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1644 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1645 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1646 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1647 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
1648 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1649 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1650 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1651 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1652 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1653 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
1655 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1656 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
1657 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1658 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
1659 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
1660 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
1661 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1662 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1664 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1665 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1666 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1667 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
1668 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1669 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
1670 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1671 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
1673 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1674 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
1675 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1676 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
1677 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1678 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
1679 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1680 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
1681 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1682 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
1683 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1684 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1686 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1687 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1688 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1689 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1690 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1691 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
1692 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1693 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
1694 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1695 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
1696 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1697 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
1698 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1699 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
1700 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1701 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
1703 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1704 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
1705 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1706 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1707 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1708 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1709 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1710 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1711 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1712 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1713 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1714 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1715 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1716 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1717 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1718 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1720 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
1721 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1722 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
1723 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1724 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
1725 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1726 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
1727 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
1728 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
1729 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
1730 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
1731 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
1732 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
1733 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
1734 u8 byte2 /* byte2 */;
1735 __le16 word0 /* word0 */;
1736 __le32 reg0 /* reg0 */;
1737 __le32 reg1 /* reg1 */;
1738 __le32 reg2 /* reg2 */;
1739 __le32 reg3 /* reg3 */;
1740 __le32 reg4 /* reg4 */;
1741 __le32 reg5 /* reg5 */;
1742 __le32 reg6 /* reg6 */;
1743 __le32 reg7 /* reg7 */;
1744 __le32 reg8 /* reg8 */;
1745 u8 byte3 /* byte3 */;
1746 u8 byte4 /* byte4 */;
1747 u8 byte5 /* byte5 */;
1748 u8 e4_reserved8 /* byte6 */;
1749 __le16 word1 /* word1 */;
1750 __le16 word2 /* conn_dpi */;
1751 __le32 reg9 /* reg9 */;
1752 __le16 word3 /* word3 */;
1753 __le16 e4_reserved9 /* word4 */;
1757 struct e5_tstorm_rdma_task_ag_ctx
1759 u8 byte0 /* cdu_validation */;
1760 u8 byte1 /* state_and_core_id */;
1761 __le16 word0 /* icid */;
1763 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */
1764 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1765 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1766 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
1767 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1768 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
1769 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1770 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
1771 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1772 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
1774 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1775 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
1776 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1777 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
1778 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1779 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
1780 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1781 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
1782 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1783 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
1785 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1786 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
1787 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */
1788 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
1789 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */
1790 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
1791 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */
1792 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
1794 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */
1795 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
1796 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1797 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
1798 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1799 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
1800 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1801 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
1802 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1803 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
1804 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1805 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
1806 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1807 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
1809 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1810 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
1811 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1812 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
1813 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1814 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1815 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1816 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1817 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1818 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1819 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1820 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1821 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1822 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1823 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1824 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1825 u8 byte2 /* byte2 */;
1826 __le16 word1 /* word1 */;
1827 __le32 reg0 /* reg0 */;
1828 u8 byte3 /* regpair0 */;
1829 u8 byte4 /* byte4 */;
1830 __le16 word2 /* word2 */;
1831 __le16 word3 /* word3 */;
1832 __le16 word4 /* word4 */;
1833 __le32 reg1 /* regpair1 */;
1834 __le32 reg2 /* reg2 */;
1838 struct e5_ustorm_rdma_conn_ag_ctx
1840 u8 reserved /* cdu_validation */;
1841 u8 byte1 /* state_and_core_id */;
1843 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1844 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1845 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1846 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1847 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */
1848 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
1849 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1850 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1851 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1852 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1854 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1855 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
1856 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1857 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
1858 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1859 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
1860 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1861 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
1863 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */
1864 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1865 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1866 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1867 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1868 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1869 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1870 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
1871 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
1872 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1873 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
1874 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
1875 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1876 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
1877 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
1878 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
1880 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
1881 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
1882 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1883 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1884 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1885 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1886 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1887 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1888 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1889 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1890 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1891 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1892 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1893 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1894 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1895 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1897 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
1898 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1899 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
1900 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1901 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
1902 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1903 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
1904 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
1905 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
1906 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
1907 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
1908 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
1909 u8 byte2 /* byte2 */;
1910 __le16 conn_dpi /* conn_dpi */;
1911 __le16 word1 /* word1 */;
1912 __le32 cq_cons /* reg0 */;
1913 __le32 cq_se_prod /* reg1 */;
1914 __le32 cq_prod /* reg2 */;
1915 __le32 reg3 /* reg3 */;
1916 __le16 int_timeout /* word2 */;
1917 __le16 word3 /* word3 */;
1922 struct e5_xstorm_rdma_conn_ag_ctx
1924 u8 reserved0 /* cdu_validation */;
1925 u8 state_and_core_id /* state_and_core_id */;
1927 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1928 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1929 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1930 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1931 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */
1932 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1933 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1934 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1935 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1936 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1937 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */
1938 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1939 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
1940 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
1941 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
1942 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
1944 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
1945 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
1946 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
1947 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
1948 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1949 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
1950 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1951 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
1952 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1953 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
1954 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
1955 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5
1956 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1957 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
1958 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1959 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
1961 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1962 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
1963 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1964 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
1965 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1966 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
1967 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1968 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
1970 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1971 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
1972 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1973 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
1974 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1975 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
1976 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
1977 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1979 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1980 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
1981 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1982 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
1983 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1984 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
1985 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1986 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
1988 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1989 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
1990 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1991 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
1992 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1993 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
1994 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1995 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
1997 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
1998 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
1999 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
2000 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
2001 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
2002 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
2003 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
2004 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
2006 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
2007 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
2008 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
2009 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
2010 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2011 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2012 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2013 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
2014 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2015 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
2017 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2018 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
2019 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2020 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
2021 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2022 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
2023 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2024 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
2025 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2026 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
2027 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
2028 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
2029 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2030 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
2031 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2032 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
2034 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2035 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
2036 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2037 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
2038 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2039 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
2040 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2041 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
2042 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2043 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
2044 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2045 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
2046 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
2047 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
2048 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
2049 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
2051 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
2052 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
2053 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
2054 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
2055 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
2056 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
2057 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
2058 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
2059 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2060 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2061 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
2062 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
2063 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2064 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
2065 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2066 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
2068 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2069 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
2070 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2071 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
2072 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2073 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
2074 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2075 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
2076 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2077 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
2078 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2079 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
2080 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2081 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2082 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2083 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
2085 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2086 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
2087 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2088 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
2089 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2090 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2091 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2092 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2093 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2094 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
2095 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2096 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
2097 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2098 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
2099 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2100 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
2102 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2103 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
2104 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2105 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
2106 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2107 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2108 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2109 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2110 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2111 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2112 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2113 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2114 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2115 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2116 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2117 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2119 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */
2120 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
2121 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
2122 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
2123 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
2124 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
2125 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
2126 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
2127 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2128 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2129 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
2130 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
2131 u8 byte2 /* byte2 */;
2132 __le16 physical_q0 /* physical_q0 */;
2133 __le16 word1 /* physical_q1 */;
2134 __le16 word2 /* physical_q2 */;
2135 __le16 word3 /* word3 */;
2136 __le16 word4 /* word4 */;
2137 __le16 word5 /* word5 */;
2138 __le16 conn_dpi /* conn_dpi */;
2139 u8 byte3 /* byte3 */;
2140 u8 byte4 /* byte4 */;
2141 u8 byte5 /* byte5 */;
2142 u8 byte6 /* byte6 */;
2143 __le32 reg0 /* reg0 */;
2144 __le32 reg1 /* reg1 */;
2145 __le32 reg2 /* reg2 */;
2146 __le32 snd_nxt_psn /* reg3 */;
2147 __le32 reg4 /* reg4 */;
2148 __le32 reg5 /* cf_array0 */;
2149 __le32 reg6 /* cf_array1 */;
2153 struct e5_ystorm_rdma_conn_ag_ctx
2155 u8 byte0 /* cdu_validation */;
2156 u8 byte1 /* state_and_core_id */;
2158 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2159 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
2160 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2161 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
2162 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2163 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
2164 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2165 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
2166 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2167 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
2169 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2170 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
2171 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2172 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
2173 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2174 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
2175 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2176 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
2177 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2178 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
2179 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2180 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
2181 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2182 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
2183 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2184 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
2185 u8 byte2 /* byte2 */;
2186 u8 byte3 /* byte3 */;
2187 __le16 word0 /* word0 */;
2188 __le32 reg0 /* reg0 */;
2189 __le32 reg1 /* reg1 */;
2190 __le16 word1 /* word1 */;
2191 __le16 word2 /* word2 */;
2192 __le16 word3 /* word3 */;
2193 __le16 word4 /* word4 */;
2194 __le32 reg2 /* reg2 */;
2195 __le32 reg3 /* reg3 */;
2199 #endif /* __ECORE_HSI_RDMA__ */