2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __ECORE_HSI_RDMA__
32 #define __ECORE_HSI_RDMA__
33 /************************************************************************/
34 /* Add include to common rdma target for both eCore and protocol rdma driver */
35 /************************************************************************/
36 #include "rdma_common.h"
39 * The rdma task context of Mstorm
41 struct ystorm_rdma_task_st_ctx
43 struct regpair temp[4];
46 struct e4_ystorm_rdma_task_ag_ctx
48 u8 reserved /* cdu_validation */;
50 __le16 msem_ctx_upd_seq /* icid */;
52 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
53 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
54 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
55 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
56 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
57 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
58 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
59 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
60 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */
61 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
64 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
66 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
67 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
68 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
69 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
70 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
71 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
72 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
74 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
75 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
76 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
77 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
78 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
79 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
80 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
81 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
82 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
83 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
84 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
85 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
86 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
87 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
88 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
89 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
91 __le32 mw_cnt /* reg0 */;
92 u8 ref_cnt_seq /* byte3 */;
93 u8 ctx_upd_seq /* byte4 */;
94 __le16 dif_flags /* word1 */;
95 __le16 tx_ref_count /* word2 */;
96 __le16 last_used_ltid /* word3 */;
97 __le16 parent_mr_lo /* word4 */;
98 __le16 parent_mr_hi /* word5 */;
99 __le32 fbo_lo /* reg1 */;
100 __le32 fbo_hi /* reg2 */;
103 struct e4_mstorm_rdma_task_ag_ctx
105 u8 reserved /* cdu_validation */;
106 u8 byte1 /* state */;
107 __le16 icid /* icid */;
109 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
110 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
111 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
112 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
113 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
114 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
115 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
116 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
117 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */
118 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
121 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
123 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
124 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
125 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
126 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
127 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
128 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
129 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
131 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
132 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
133 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
134 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
135 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
136 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
137 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
138 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
139 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
140 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
141 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
142 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
143 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
144 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
145 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
146 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
148 __le32 mw_cnt /* reg0 */;
149 u8 ref_cnt_seq /* byte3 */;
150 u8 ctx_upd_seq /* byte4 */;
151 __le16 dif_flags /* word1 */;
152 __le16 tx_ref_count /* word2 */;
153 __le16 last_used_ltid /* word3 */;
154 __le16 parent_mr_lo /* word4 */;
155 __le16 parent_mr_hi /* word5 */;
156 __le32 fbo_lo /* reg1 */;
157 __le32 fbo_hi /* reg2 */;
161 * The roce task context of Mstorm
163 struct mstorm_rdma_task_st_ctx
165 struct regpair temp[4];
169 * The roce task context of Ustorm
171 struct ustorm_rdma_task_st_ctx
173 struct regpair temp[2];
176 struct e4_ustorm_rdma_task_ag_ctx
178 u8 reserved /* cdu_validation */;
179 u8 byte1 /* state */;
180 __le16 icid /* icid */;
182 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
183 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
184 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
185 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
186 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */
187 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
188 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
192 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
194 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
195 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
196 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
197 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */
198 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
200 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */
201 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
202 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */
203 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
204 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */
205 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
206 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
207 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
208 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */
209 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
210 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
211 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
212 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
213 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
214 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
215 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
217 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
218 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
219 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
220 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
221 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
222 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
223 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
224 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
225 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */
226 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
227 __le32 dif_err_intervals /* reg0 */;
228 __le32 dif_error_1st_interval /* reg1 */;
229 __le32 reg2 /* reg2 */;
230 __le32 dif_runt_value /* reg3 */;
231 __le32 reg4 /* reg4 */;
232 __le32 reg5 /* reg5 */;
238 struct e4_rdma_task_context
240 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
241 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
242 struct tdif_task_context tdif_context /* tdif context */;
243 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
244 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
245 struct rdif_task_context rdif_context /* rdif context */;
246 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
247 struct regpair ustorm_st_padding[2] /* padding */;
248 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
252 struct e5_ystorm_rdma_task_ag_ctx
254 u8 reserved /* cdu_validation */;
255 u8 byte1 /* state_and_core_id */;
256 __le16 msem_ctx_upd_seq /* icid */;
258 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
259 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
260 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
261 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
262 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
263 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
264 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
265 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
266 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
267 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
269 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
270 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
271 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
272 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
273 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
274 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
275 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
276 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
277 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
278 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
280 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
281 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
282 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
283 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
284 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
285 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
286 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
287 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
288 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
289 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
290 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
291 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
292 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
293 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
294 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
295 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
297 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */
298 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
299 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
300 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
301 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
302 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
303 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */
304 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
305 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */
306 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
307 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */
308 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
309 __le32 mw_cnt /* reg0 */;
311 u8 ref_cnt_seq /* byte3 */;
312 u8 ctx_upd_seq /* byte4 */;
313 u8 e4_reserved7 /* byte5 */;
314 __le16 dif_flags /* word1 */;
315 __le16 tx_ref_count /* word2 */;
316 __le16 last_used_ltid /* word3 */;
317 __le16 parent_mr_lo /* word4 */;
318 __le16 parent_mr_hi /* word5 */;
319 __le16 e4_reserved8 /* word6 */;
320 __le32 fbo_lo /* reg1 */;
323 struct e5_mstorm_rdma_task_ag_ctx
325 u8 reserved /* cdu_validation */;
326 u8 byte1 /* state_and_core_id */;
327 __le16 icid /* icid */;
329 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
330 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
331 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
332 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
333 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
334 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
335 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
336 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
337 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
338 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
340 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
341 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
342 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
343 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
344 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
345 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
346 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
347 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
348 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
349 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
351 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
352 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
353 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
354 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
355 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
356 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
357 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
358 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
359 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
360 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
361 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
362 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
363 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
364 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
365 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
366 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
368 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */
369 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
370 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
371 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
372 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
373 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
374 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */
375 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
376 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */
377 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
378 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */
379 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
380 __le32 mw_cnt /* reg0 */;
382 u8 ref_cnt_seq /* byte3 */;
383 u8 ctx_upd_seq /* byte4 */;
384 u8 e4_reserved7 /* byte5 */;
385 __le16 dif_flags /* regpair0 */;
386 __le16 tx_ref_count /* word2 */;
387 __le16 last_used_ltid /* word3 */;
388 __le16 parent_mr_lo /* word4 */;
389 __le16 parent_mr_hi /* regpair1 */;
390 __le16 e4_reserved8 /* word6 */;
391 __le32 fbo_lo /* reg1 */;
394 struct e5_ustorm_rdma_task_ag_ctx
396 u8 reserved /* cdu_validation */;
397 u8 byte1 /* state_and_core_id */;
398 __le16 icid /* icid */;
400 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
401 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
402 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
403 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
404 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */
405 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
406 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
407 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
409 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
410 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
411 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
412 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
413 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
414 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
415 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */
416 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
418 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */
419 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
420 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */
421 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
422 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */
423 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
424 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
425 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
426 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */
427 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
428 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
429 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
430 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
431 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
432 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
433 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
435 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
436 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
437 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
438 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
439 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
440 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
441 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
442 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
443 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
444 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4
445 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
446 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5
447 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */
448 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6
449 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */
450 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7
452 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */
453 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0
454 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */
455 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2
456 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */
457 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3
458 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */
459 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
460 u8 byte2 /* byte2 */;
461 u8 byte3 /* byte3 */;
462 u8 e4_reserved8 /* byte4 */;
463 __le32 dif_err_intervals /* dif_err_intervals */;
464 __le32 dif_error_1st_interval /* dif_error_1st_interval */;
465 __le32 reg2 /* reg2 */;
466 __le32 dif_runt_value /* reg3 */;
467 __le32 reg4 /* reg4 */;
473 struct e5_rdma_task_context
475 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
476 struct e5_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
477 struct tdif_task_context tdif_context /* tdif context */;
478 struct e5_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
479 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
480 struct rdif_task_context rdif_context /* rdif context */;
481 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
482 struct regpair ustorm_st_padding[2] /* padding */;
483 struct e5_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
489 * rdma function init ramrod data
491 struct rdma_close_func_ramrod_data
495 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
502 * rdma function init CNQ parameters
504 struct rdma_cnq_params
506 __le16 sb_num /* Status block number used by the queue */;
507 u8 sb_index /* Status block index used by the queue */;
508 u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
510 struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
511 __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
517 * rdma create cq ramrod data
519 struct rdma_create_cq_ramrod_data
521 struct regpair cq_handle;
522 struct regpair pbl_addr;
524 __le16 pbl_num_pages;
528 u8 pbl_log_page_size;
530 __le16 int_timeout /* Timeout used for interrupt moderation */;
536 * rdma deregister tid ramrod data
538 struct rdma_deregister_tid_ramrod_data
546 * rdma destroy cq output params
548 struct rdma_destroy_cq_output_params
550 __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
557 * rdma destroy cq ramrod data
559 struct rdma_destroy_cq_ramrod_data
561 struct regpair output_params_addr;
566 * RDMA slow path EQ cmd IDs
568 enum rdma_event_opcode
571 RDMA_EVENT_FUNC_INIT,
572 RDMA_EVENT_FUNC_CLOSE,
573 RDMA_EVENT_REGISTER_MR,
574 RDMA_EVENT_DEREGISTER_MR,
575 RDMA_EVENT_CREATE_CQ,
576 RDMA_EVENT_RESIZE_CQ,
577 RDMA_EVENT_DESTROY_CQ,
578 RDMA_EVENT_CREATE_SRQ,
579 RDMA_EVENT_MODIFY_SRQ,
580 RDMA_EVENT_DESTROY_SRQ,
581 MAX_RDMA_EVENT_OPCODE
586 * RDMA FW return code for slow path ramrods
588 enum rdma_fw_return_code
591 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
592 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
593 RDMA_RETURN_RESIZE_CQ_ERR,
594 RDMA_RETURN_NIG_DRAIN_REQ,
595 MAX_RDMA_FW_RETURN_CODE
600 * rdma function init header
602 struct rdma_init_func_hdr
604 u8 cnq_start_offset /* First RDMA CNQ */;
605 u8 num_cnqs /* Number of CNQs */;
606 u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
607 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
609 u8 relaxed_ordering /* 1 for using relaxed ordering PCI writes */;
610 __le16 first_reg_srq_id /* The SRQ ID of thr first regular (non XRC) SRQ */;
611 __le32 reg_srq_base_addr /* Logical base address of first regular (non XRC) SRQ */;
617 * rdma function init ramrod data
619 struct rdma_init_func_ramrod_data
621 struct rdma_init_func_hdr params_header;
622 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
627 * RDMA ramrod command IDs
629 enum rdma_ramrod_cmd_id
632 RDMA_RAMROD_FUNC_INIT,
633 RDMA_RAMROD_FUNC_CLOSE,
634 RDMA_RAMROD_REGISTER_MR,
635 RDMA_RAMROD_DEREGISTER_MR,
636 RDMA_RAMROD_CREATE_CQ,
637 RDMA_RAMROD_RESIZE_CQ,
638 RDMA_RAMROD_DESTROY_CQ,
639 RDMA_RAMROD_CREATE_SRQ,
640 RDMA_RAMROD_MODIFY_SRQ,
641 RDMA_RAMROD_DESTROY_SRQ,
642 MAX_RDMA_RAMROD_CMD_ID
647 * rdma register tid ramrod data
649 struct rdma_register_tid_ramrod_data
652 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
653 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
654 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
655 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
656 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
657 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
658 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
659 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
660 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
661 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
662 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
663 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
664 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
665 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
666 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
667 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
668 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
669 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
670 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
671 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
672 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
673 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
675 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
676 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
677 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
678 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
680 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
681 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
682 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */
683 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
684 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
685 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
688 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
692 __le32 length_lo /* lower 32 bits of the registered MR length. */;
696 struct regpair pbl_base;
697 struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
698 struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
704 * rdma resize cq output params
706 struct rdma_resize_cq_output_params
708 __le32 old_cq_cons /* cq consumer value on old PBL */;
709 __le32 old_cq_prod /* cq producer value on old PBL */;
714 * rdma resize cq ramrod data
716 struct rdma_resize_cq_ramrod_data
719 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
720 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
721 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
722 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
723 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
724 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
725 u8 pbl_log_page_size;
726 __le16 pbl_num_pages;
728 struct regpair pbl_addr;
729 struct regpair output_params_addr;
734 * The rdma SRQ context
736 struct rdma_srq_context
738 struct regpair temp[8];
743 * rdma create qp requester ramrod data
745 struct rdma_srq_create_ramrod_data
748 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
749 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
750 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 /* Only applicable when xrc_flag is set */
751 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
752 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
753 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2
755 __le16 xrc_domain /* Only applicable when xrc_flag is set */;
756 __le32 xrc_srq_cq_cid /* Only applicable when xrc_flag is set */;
757 struct regpair pbl_base_addr /* SRQ PBL base address */;
758 __le16 pages_in_srq_pbl /* Number of pages in PBL */;
760 struct rdma_srq_id srq_id /* SRQ Index */;
761 __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
764 struct regpair producers_addr /* SRQ PBL base address */;
769 * rdma create qp requester ramrod data
771 struct rdma_srq_destroy_ramrod_data
773 struct rdma_srq_id srq_id /* SRQ Index */;
779 * rdma create qp requester ramrod data
781 struct rdma_srq_modify_ramrod_data
783 struct rdma_srq_id srq_id /* SRQ Index */;
789 * RDMA Tid type enumeration (for register_tid ramrod)
793 RDMA_TID_REGISTERED_MR,
802 * The rdma XRC SRQ context
804 struct rdma_xrc_srq_context
806 struct regpair temp[9];
812 struct E4XstormRoceConnAgCtxDqExtLdPart
814 u8 reserved0 /* cdu_validation */;
815 u8 state /* state */;
817 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
818 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
819 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */
820 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
821 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */
822 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
823 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
824 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
825 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */
826 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
827 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */
828 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
829 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */
830 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
831 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */
832 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
834 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */
835 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
836 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */
837 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
838 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */
839 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
840 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */
841 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
842 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */
843 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
844 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */
845 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
846 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */
847 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
848 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */
849 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
851 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */
852 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
853 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */
854 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
855 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */
856 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
857 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */
858 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
860 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */
861 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
862 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */
863 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
864 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */
865 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
866 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
867 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
869 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */
870 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
871 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */
872 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
873 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */
874 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
875 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */
876 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
878 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */
879 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
880 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */
881 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
882 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */
883 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
884 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */
885 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
887 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */
888 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
889 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */
890 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
891 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */
892 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
893 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */
894 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
896 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */
897 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
898 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */
899 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
900 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */
901 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
902 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */
903 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
904 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */
905 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
907 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */
908 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
909 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */
910 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
911 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */
912 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
913 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */
914 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
915 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */
916 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
917 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
918 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
919 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */
920 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
921 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */
922 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
924 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */
925 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
926 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */
927 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
928 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */
929 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
930 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */
931 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
932 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */
933 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
934 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */
935 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
936 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */
937 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
938 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */
939 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
941 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */
942 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
943 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */
944 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
945 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */
946 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
947 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */
948 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
949 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */
950 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
951 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */
952 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
953 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */
954 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
955 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */
956 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
958 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */
959 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
960 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */
961 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
962 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */
963 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
964 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */
965 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
966 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */
967 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
968 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */
969 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
970 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */
971 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
972 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */
973 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
975 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */
976 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
977 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */
978 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
979 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */
980 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
981 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */
982 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
983 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */
984 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
985 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */
986 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
987 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */
988 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
989 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */
990 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
992 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */
993 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
994 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */
995 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
996 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */
997 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
998 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */
999 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1000 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */
1001 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1002 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */
1003 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1004 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */
1005 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1006 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */
1007 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1009 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */
1010 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
1011 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */
1012 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
1013 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1014 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
1015 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */
1016 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
1017 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
1018 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1019 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */
1020 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
1021 u8 byte2 /* byte2 */;
1022 __le16 physical_q0 /* physical_q0 */;
1023 __le16 word1 /* physical_q1 */;
1024 __le16 word2 /* physical_q2 */;
1025 __le16 word3 /* word3 */;
1026 __le16 word4 /* word4 */;
1027 __le16 word5 /* word5 */;
1028 __le16 conn_dpi /* conn_dpi */;
1029 u8 byte3 /* byte3 */;
1030 u8 byte4 /* byte4 */;
1031 u8 byte5 /* byte5 */;
1032 u8 byte6 /* byte6 */;
1033 __le32 reg0 /* reg0 */;
1034 __le32 reg1 /* reg1 */;
1035 __le32 reg2 /* reg2 */;
1036 __le32 snd_nxt_psn /* reg3 */;
1037 __le32 reg4 /* reg4 */;
1041 struct e4_mstorm_rdma_conn_ag_ctx
1043 u8 byte0 /* cdu_validation */;
1044 u8 byte1 /* state */;
1046 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1047 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1048 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1049 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1050 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1051 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1052 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1053 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1054 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1055 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1057 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1058 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1059 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1060 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1061 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1062 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1063 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1064 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1065 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1066 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1067 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1068 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1069 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1070 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1071 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1072 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1073 __le16 word0 /* word0 */;
1074 __le16 word1 /* word1 */;
1075 __le32 reg0 /* reg0 */;
1076 __le32 reg1 /* reg1 */;
1081 struct e4_tstorm_rdma_conn_ag_ctx
1083 u8 reserved0 /* cdu_validation */;
1084 u8 byte1 /* state */;
1086 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1087 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1088 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1089 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1090 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1091 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1092 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1093 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
1094 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1095 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1096 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1097 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1098 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1099 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
1101 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1102 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
1103 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1104 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
1105 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
1106 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
1107 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1108 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1110 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1111 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1112 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1113 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
1114 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1115 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
1116 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1117 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
1119 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1120 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
1121 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1122 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
1123 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1124 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
1125 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1126 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
1127 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1128 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
1129 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1130 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1132 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1133 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1134 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1135 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1136 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1137 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
1138 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1139 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
1140 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1141 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
1142 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1143 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
1144 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1145 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
1146 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1147 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
1149 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1150 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
1151 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1152 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1153 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1154 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1155 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1156 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1157 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1158 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1159 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1160 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1161 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1162 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1163 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1164 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1165 __le32 reg0 /* reg0 */;
1166 __le32 reg1 /* reg1 */;
1167 __le32 reg2 /* reg2 */;
1168 __le32 reg3 /* reg3 */;
1169 __le32 reg4 /* reg4 */;
1170 __le32 reg5 /* reg5 */;
1171 __le32 reg6 /* reg6 */;
1172 __le32 reg7 /* reg7 */;
1173 __le32 reg8 /* reg8 */;
1174 u8 byte2 /* byte2 */;
1175 u8 byte3 /* byte3 */;
1176 __le16 word0 /* word0 */;
1177 u8 byte4 /* byte4 */;
1178 u8 byte5 /* byte5 */;
1179 __le16 word1 /* word1 */;
1180 __le16 word2 /* conn_dpi */;
1181 __le16 word3 /* word3 */;
1182 __le32 reg9 /* reg9 */;
1183 __le32 reg10 /* reg10 */;
1187 struct e4_tstorm_rdma_task_ag_ctx
1189 u8 byte0 /* cdu_validation */;
1190 u8 byte1 /* state */;
1191 __le16 word0 /* icid */;
1193 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */
1194 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1195 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1196 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
1197 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1198 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
1199 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1200 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
1201 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1202 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
1204 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1205 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
1206 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1207 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
1208 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1209 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
1210 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1211 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
1212 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1213 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
1215 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1216 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
1217 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */
1218 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
1219 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */
1220 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
1221 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */
1222 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
1224 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */
1225 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
1226 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1227 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
1228 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1229 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
1230 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1231 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
1232 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1233 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
1234 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1235 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
1236 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1237 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
1239 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1240 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
1241 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1242 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
1243 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1244 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1245 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1246 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1247 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1248 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1249 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1250 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1251 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1252 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1253 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1254 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1255 u8 byte2 /* byte2 */;
1256 __le16 word1 /* word1 */;
1257 __le32 reg0 /* reg0 */;
1258 u8 byte3 /* byte3 */;
1259 u8 byte4 /* byte4 */;
1260 __le16 word2 /* word2 */;
1261 __le16 word3 /* word3 */;
1262 __le16 word4 /* word4 */;
1263 __le32 reg1 /* reg1 */;
1264 __le32 reg2 /* reg2 */;
1268 struct e4_ustorm_rdma_conn_ag_ctx
1270 u8 reserved /* cdu_validation */;
1271 u8 byte1 /* state */;
1273 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1274 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1275 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1276 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1277 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */
1278 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
1279 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1280 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1281 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1282 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1284 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1285 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
1286 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1287 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
1288 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1289 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
1290 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1291 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
1293 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */
1294 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1295 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1296 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1297 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1298 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1299 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1300 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
1301 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
1302 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1303 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
1304 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
1305 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1306 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
1307 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
1308 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
1310 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
1311 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
1312 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1313 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1314 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1315 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1316 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1317 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1318 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1319 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1320 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1321 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1322 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1323 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1324 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1325 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1326 u8 byte2 /* byte2 */;
1327 u8 byte3 /* byte3 */;
1328 __le16 conn_dpi /* conn_dpi */;
1329 __le16 word1 /* word1 */;
1330 __le32 cq_cons /* reg0 */;
1331 __le32 cq_se_prod /* reg1 */;
1332 __le32 cq_prod /* reg2 */;
1333 __le32 reg3 /* reg3 */;
1334 __le16 int_timeout /* word2 */;
1335 __le16 word3 /* word3 */;
1340 struct e4_xstorm_rdma_conn_ag_ctx
1342 u8 reserved0 /* cdu_validation */;
1343 u8 state /* state */;
1345 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1346 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1347 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1348 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1349 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */
1350 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1351 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1352 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1353 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1354 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1355 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */
1356 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1357 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
1358 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
1359 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
1360 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
1362 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
1363 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
1364 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
1365 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
1366 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1367 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
1368 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1369 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
1370 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1371 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
1372 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */
1373 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
1374 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1375 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
1376 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1377 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
1379 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1380 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
1381 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1382 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
1383 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1384 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
1385 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1386 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
1388 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1389 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
1390 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1391 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
1392 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1393 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
1394 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
1395 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1397 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1398 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
1399 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1400 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
1401 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1402 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
1403 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1404 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
1406 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1407 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
1408 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1409 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
1410 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1411 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
1412 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1413 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
1415 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
1416 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
1417 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
1418 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
1419 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
1420 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
1421 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
1422 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
1424 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
1425 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
1426 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
1427 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
1428 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1429 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1430 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1431 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
1432 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1433 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
1435 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1436 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
1437 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1438 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
1439 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1440 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
1441 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1442 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
1443 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1444 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
1445 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
1446 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
1447 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1448 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
1449 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1450 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
1452 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1453 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
1454 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1455 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
1456 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1457 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
1458 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1459 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
1460 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
1461 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
1462 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1463 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
1464 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
1465 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
1466 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1467 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
1469 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1470 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
1471 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
1472 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
1473 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
1474 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
1475 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
1476 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
1477 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1478 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1479 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1480 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
1481 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1482 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
1483 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1484 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
1486 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1487 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
1488 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1489 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
1490 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1491 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
1492 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1493 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
1494 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1495 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
1496 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1497 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
1498 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1499 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1500 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
1501 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
1503 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
1504 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
1505 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
1506 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
1507 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1508 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1509 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1510 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1511 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
1512 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
1513 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1514 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
1515 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
1516 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
1517 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
1518 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
1520 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
1521 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
1522 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
1523 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
1524 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
1525 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1526 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
1527 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1528 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1529 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1530 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
1531 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1532 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1533 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1534 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1535 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1537 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */
1538 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
1539 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1540 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
1541 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1542 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
1543 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
1544 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
1545 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
1546 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1547 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
1548 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
1549 u8 byte2 /* byte2 */;
1550 __le16 physical_q0 /* physical_q0 */;
1551 __le16 word1 /* physical_q1 */;
1552 __le16 word2 /* physical_q2 */;
1553 __le16 word3 /* word3 */;
1554 __le16 word4 /* word4 */;
1555 __le16 word5 /* word5 */;
1556 __le16 conn_dpi /* conn_dpi */;
1557 u8 byte3 /* byte3 */;
1558 u8 byte4 /* byte4 */;
1559 u8 byte5 /* byte5 */;
1560 u8 byte6 /* byte6 */;
1561 __le32 reg0 /* reg0 */;
1562 __le32 reg1 /* reg1 */;
1563 __le32 reg2 /* reg2 */;
1564 __le32 snd_nxt_psn /* reg3 */;
1565 __le32 reg4 /* reg4 */;
1566 __le32 reg5 /* cf_array0 */;
1567 __le32 reg6 /* cf_array1 */;
1571 struct e4_ystorm_rdma_conn_ag_ctx
1573 u8 byte0 /* cdu_validation */;
1574 u8 byte1 /* state */;
1576 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1577 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1578 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1579 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1580 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1581 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1582 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1583 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1584 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1585 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1587 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1588 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1589 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1590 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1591 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1592 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1593 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1594 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1595 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1596 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1597 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1598 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1599 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1600 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1601 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1602 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1603 u8 byte2 /* byte2 */;
1604 u8 byte3 /* byte3 */;
1605 __le16 word0 /* word0 */;
1606 __le32 reg0 /* reg0 */;
1607 __le32 reg1 /* reg1 */;
1608 __le16 word1 /* word1 */;
1609 __le16 word2 /* word2 */;
1610 __le16 word3 /* word3 */;
1611 __le16 word4 /* word4 */;
1612 __le32 reg2 /* reg2 */;
1613 __le32 reg3 /* reg3 */;
1618 struct e5_mstorm_rdma_conn_ag_ctx
1620 u8 byte0 /* cdu_validation */;
1621 u8 byte1 /* state_and_core_id */;
1623 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1624 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
1625 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1626 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1627 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1628 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
1629 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1630 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1631 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1632 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1634 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1635 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
1636 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1637 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1638 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1639 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1640 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1641 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1642 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1643 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1644 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1645 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1646 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1647 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1648 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1649 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1650 __le16 word0 /* word0 */;
1651 __le16 word1 /* word1 */;
1652 __le32 reg0 /* reg0 */;
1653 __le32 reg1 /* reg1 */;
1658 struct e5_tstorm_rdma_conn_ag_ctx
1660 u8 reserved0 /* cdu_validation */;
1661 u8 byte1 /* state_and_core_id */;
1663 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1664 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1665 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1666 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1667 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1668 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1669 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1670 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
1671 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1672 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1673 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1674 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1675 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1676 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
1678 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1679 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
1680 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1681 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
1682 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
1683 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
1684 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1685 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1687 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1688 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1689 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1690 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
1691 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1692 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
1693 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1694 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
1696 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1697 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
1698 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1699 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
1700 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1701 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
1702 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1703 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
1704 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1705 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
1706 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1707 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1709 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1710 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1711 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1712 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1713 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1714 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
1715 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1716 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
1717 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1718 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
1719 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1720 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
1721 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1722 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
1723 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1724 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
1726 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1727 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
1728 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1729 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1730 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1731 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1732 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1733 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1734 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1735 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1736 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1737 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1738 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1739 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1740 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1741 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1743 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
1744 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1745 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
1746 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1747 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
1748 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1749 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
1750 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
1751 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
1752 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
1753 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
1754 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
1755 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
1756 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
1757 u8 byte2 /* byte2 */;
1758 __le16 word0 /* word0 */;
1759 __le32 reg0 /* reg0 */;
1760 __le32 reg1 /* reg1 */;
1761 __le32 reg2 /* reg2 */;
1762 __le32 reg3 /* reg3 */;
1763 __le32 reg4 /* reg4 */;
1764 __le32 reg5 /* reg5 */;
1765 __le32 reg6 /* reg6 */;
1766 __le32 reg7 /* reg7 */;
1767 __le32 reg8 /* reg8 */;
1768 u8 byte3 /* byte3 */;
1769 u8 byte4 /* byte4 */;
1770 u8 byte5 /* byte5 */;
1771 u8 e4_reserved8 /* byte6 */;
1772 __le16 word1 /* word1 */;
1773 __le16 word2 /* conn_dpi */;
1774 __le32 reg9 /* reg9 */;
1775 __le16 word3 /* word3 */;
1776 __le16 e4_reserved9 /* word4 */;
1780 struct e5_tstorm_rdma_task_ag_ctx
1782 u8 byte0 /* cdu_validation */;
1783 u8 byte1 /* state_and_core_id */;
1784 __le16 word0 /* icid */;
1786 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */
1787 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1788 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1789 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
1790 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1791 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
1792 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1793 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
1794 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1795 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
1797 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1798 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
1799 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1800 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
1801 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1802 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
1803 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1804 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
1805 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1806 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
1808 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1809 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
1810 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */
1811 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
1812 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */
1813 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
1814 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */
1815 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
1817 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */
1818 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
1819 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1820 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
1821 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1822 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
1823 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1824 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
1825 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1826 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
1827 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1828 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
1829 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1830 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
1832 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1833 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
1834 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1835 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
1836 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1837 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1838 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1839 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1840 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1841 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1842 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1843 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1844 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1845 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1846 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1847 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1848 u8 byte2 /* byte2 */;
1849 __le16 word1 /* word1 */;
1850 __le32 reg0 /* reg0 */;
1851 u8 byte3 /* regpair0 */;
1852 u8 byte4 /* byte4 */;
1853 __le16 word2 /* word2 */;
1854 __le16 word3 /* word3 */;
1855 __le16 word4 /* word4 */;
1856 __le32 reg1 /* regpair1 */;
1857 __le32 reg2 /* reg2 */;
1861 struct e5_ustorm_rdma_conn_ag_ctx
1863 u8 reserved /* cdu_validation */;
1864 u8 byte1 /* state_and_core_id */;
1866 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1867 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1868 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1869 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1870 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */
1871 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
1872 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1873 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
1874 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1875 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
1877 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1878 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
1879 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1880 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
1881 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1882 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
1883 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1884 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
1886 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */
1887 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1888 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1889 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
1890 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1891 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
1892 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1893 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
1894 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */
1895 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1896 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */
1897 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
1898 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1899 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
1900 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */
1901 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
1903 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */
1904 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
1905 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1906 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
1907 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1908 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
1909 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1910 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
1911 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1912 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
1913 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1914 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
1915 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1916 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
1917 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1918 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
1920 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
1921 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1922 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
1923 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1924 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
1925 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1926 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
1927 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
1928 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
1929 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
1930 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
1931 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
1932 u8 byte2 /* byte2 */;
1933 __le16 conn_dpi /* conn_dpi */;
1934 __le16 word1 /* word1 */;
1935 __le32 cq_cons /* reg0 */;
1936 __le32 cq_se_prod /* reg1 */;
1937 __le32 cq_prod /* reg2 */;
1938 __le32 reg3 /* reg3 */;
1939 __le16 int_timeout /* word2 */;
1940 __le16 word3 /* word3 */;
1945 struct e5_xstorm_rdma_conn_ag_ctx
1947 u8 reserved0 /* cdu_validation */;
1948 u8 state_and_core_id /* state_and_core_id */;
1950 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1951 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1952 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1953 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
1954 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */
1955 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
1956 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1957 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1958 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
1959 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
1960 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */
1961 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
1962 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
1963 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
1964 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
1965 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
1967 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
1968 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
1969 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */
1970 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
1971 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1972 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
1973 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1974 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
1975 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1976 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
1977 #define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */
1978 #define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
1979 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1980 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
1981 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1982 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
1984 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1985 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
1986 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1987 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
1988 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1989 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
1990 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1991 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
1993 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1994 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
1995 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1996 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
1997 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1998 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
1999 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
2000 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
2002 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2003 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
2004 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2005 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
2006 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2007 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
2008 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2009 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
2011 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2012 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
2013 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2014 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
2015 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2016 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
2017 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2018 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
2020 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
2021 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
2022 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
2023 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
2024 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
2025 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
2026 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
2027 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
2029 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
2030 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
2031 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
2032 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
2033 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2034 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2035 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2036 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
2037 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2038 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
2040 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2041 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
2042 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2043 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
2044 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2045 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
2046 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2047 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
2048 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2049 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
2050 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
2051 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
2052 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2053 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
2054 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2055 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
2057 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2058 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
2059 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2060 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
2061 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2062 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
2063 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2064 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
2065 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2066 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
2067 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2068 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
2069 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
2070 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
2071 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
2072 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
2074 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
2075 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
2076 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
2077 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
2078 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
2079 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
2080 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
2081 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
2082 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2083 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2084 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
2085 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
2086 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2087 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
2088 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2089 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
2091 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2092 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
2093 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2094 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
2095 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2096 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
2097 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2098 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
2099 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2100 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
2101 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2102 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
2103 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2104 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2105 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2106 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
2108 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2109 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
2110 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2111 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
2112 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2113 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2114 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2115 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2116 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2117 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
2118 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2119 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
2120 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2121 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
2122 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2123 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
2125 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2126 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
2127 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2128 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
2129 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2130 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2131 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2132 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2133 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2134 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2135 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2136 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2137 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2138 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2139 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2140 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2142 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */
2143 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
2144 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
2145 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
2146 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
2147 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
2148 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
2149 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
2150 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2151 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2152 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
2153 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
2154 u8 byte2 /* byte2 */;
2155 __le16 physical_q0 /* physical_q0 */;
2156 __le16 word1 /* physical_q1 */;
2157 __le16 word2 /* physical_q2 */;
2158 __le16 word3 /* word3 */;
2159 __le16 word4 /* word4 */;
2160 __le16 word5 /* word5 */;
2161 __le16 conn_dpi /* conn_dpi */;
2162 u8 byte3 /* byte3 */;
2163 u8 byte4 /* byte4 */;
2164 u8 byte5 /* byte5 */;
2165 u8 byte6 /* byte6 */;
2166 __le32 reg0 /* reg0 */;
2167 __le32 reg1 /* reg1 */;
2168 __le32 reg2 /* reg2 */;
2169 __le32 snd_nxt_psn /* reg3 */;
2170 __le32 reg4 /* reg4 */;
2171 __le32 reg5 /* cf_array0 */;
2172 __le32 reg6 /* cf_array1 */;
2176 struct e5_ystorm_rdma_conn_ag_ctx
2178 u8 byte0 /* cdu_validation */;
2179 u8 byte1 /* state_and_core_id */;
2181 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2182 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
2183 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2184 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
2185 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2186 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
2187 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2188 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
2189 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2190 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
2192 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2193 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
2194 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2195 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
2196 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2197 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
2198 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2199 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
2200 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2201 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
2202 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2203 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
2204 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2205 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
2206 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2207 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
2208 u8 byte2 /* byte2 */;
2209 u8 byte3 /* byte3 */;
2210 __le16 word0 /* word0 */;
2211 __le32 reg0 /* reg0 */;
2212 __le32 reg1 /* reg1 */;
2213 __le16 word1 /* word1 */;
2214 __le16 word2 /* word2 */;
2215 __le16 word3 /* word3 */;
2216 __le16 word4 /* word4 */;
2217 __le32 reg2 /* reg2 */;
2218 __le32 reg3 /* reg3 */;
2222 #endif /* __ECORE_HSI_RDMA__ */