2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef _ECORE_IGU_DEF_H_
32 #define _ECORE_IGU_DEF_H_
34 /* Fields of IGU PF CONFIGRATION REGISTER */
35 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
36 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
37 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
38 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
39 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
40 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
42 /* Fields of IGU VF CONFIGRATION REGISTER */
43 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
44 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
45 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
46 #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */
47 #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */
49 /* Igu control commands
58 /* Control register for the IGU command register
63 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
64 #define IGU_CTRL_REG_FID_SHIFT 0
65 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
66 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
67 #define IGU_CTRL_REG_RESERVED_MASK 0x1
68 #define IGU_CTRL_REG_RESERVED_SHIFT 28
69 #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */
70 #define IGU_CTRL_REG_TYPE_SHIFT 31