sys/dev/qlnx/qlnxe/ecore_int.c

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27 /*
  28  * File : ecore_int.c
  29  */
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "bcm_osal.h"
  34 #include "ecore.h"
  35 #include "ecore_spq.h"
  36 #include "reg_addr.h"
  37 #include "ecore_gtt_reg_addr.h"
  38 #include "ecore_init_ops.h"
  39 #include "ecore_rt_defs.h"
  40 #include "ecore_int.h"
  41 #include "reg_addr.h"
  42 #include "ecore_hw.h"
  43 #include "ecore_sriov.h"
  44 #include "ecore_vf.h"
  45 #include "ecore_hw_defs.h"
  46 #include "ecore_hsi_common.h"
  47 #include "ecore_mcp.h"
  48 #include "ecore_dbg_fw_funcs.h"
  49
  50 #ifdef DIAG
  51 /* This is nasty, but diag is using the drv_dbg_fw_funcs.c [non-ecore flavor],
  52  * and so the functions are lacking ecore prefix.
  53  * If there would be other clients needing this [or if the content that isn't
  54  * really optional there would increase], we'll need to re-think this.
  55  */
  56 enum dbg_status dbg_read_attn(struct ecore_hwfn *dev,
  57                                                           struct ecore_ptt *ptt,
  58                                                           enum block_id block,
  59                                                           enum dbg_attn_type attn_type,
  60                                                           bool clear_status,
  61                                                           struct dbg_attn_block_result *results);
  62
  63 enum dbg_status dbg_parse_attn(struct ecore_hwfn *dev,
  64                                                            struct dbg_attn_block_result *results);
  65
  66 const char* dbg_get_status_str(enum dbg_status status);
  67
  68 #define ecore_dbg_read_attn(hwfn, ptt, id, type, clear, results) \
  69         dbg_read_attn(hwfn, ptt, id, type, clear, results)
  70 #define ecore_dbg_parse_attn(hwfn, results) \
  71         dbg_parse_attn(hwfn, results)
  72 #define ecore_dbg_get_status_str(status) \
  73         dbg_get_status_str(status)
  74 #endif
  75
  76 struct ecore_pi_info {
  77         ecore_int_comp_cb_t comp_cb;
  78         void *cookie; /* Will be sent to the completion callback function */
  79 };
  80
  81 struct ecore_sb_sp_info {
  82         struct ecore_sb_info sb_info;
  83         /* per protocol index data */
  84         struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
  85 };
  86
  87 enum ecore_attention_type {
  88         ECORE_ATTN_TYPE_ATTN,
  89         ECORE_ATTN_TYPE_PARITY,
  90 };
  91
  92 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  93         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  94
  95 struct aeu_invert_reg_bit {
  96         char bit_name[30];
  97
  98 #define ATTENTION_PARITY                (1 << 0)
  99
 100 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
 101 #define ATTENTION_LENGTH_SHIFT          (4)
 102 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
 103                                          ATTENTION_LENGTH_SHIFT)
 104 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
 105 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
 106 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
 107                                          ATTENTION_PARITY)
 108
 109 /* Multiple bits start with this offset */
 110 #define ATTENTION_OFFSET_MASK           (0x000ff000)
 111 #define ATTENTION_OFFSET_SHIFT          (12)
 112
 113 #define ATTENTION_BB_MASK               (0x00700000)
 114 #define ATTENTION_BB_SHIFT              (20)
 115 #define ATTENTION_BB(value)             (value << ATTENTION_BB_SHIFT)
 116 #define ATTENTION_BB_DIFFERENT          (1 << 23)
 117
 118 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
 119         unsigned int flags;
 120
 121         /* Callback to call if attention will be triggered */
 122         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
 123
 124         enum block_id block_index;
 125 };
 126
 127 struct aeu_invert_reg {
 128         struct aeu_invert_reg_bit bits[32];
 129 };
 130
 131 #define MAX_ATTN_GRPS           (8)
 132 #define NUM_ATTN_REGS           (9)
 133
 134 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
 135 {
 136         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
 137
 138         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
 139                 tmp);
 140         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
 141                  0xffffffff);
 142
 143         return ECORE_SUCCESS;
 144 }
 145
 146 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
 147 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
 148 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
 149 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
 150 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
 151 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
 152 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
 153 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 154 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 155 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 156 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 157 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 158 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 159 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 160 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 161 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 162 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 163 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 164 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 165 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 166 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 167 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 168 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 169 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 170 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 171 {
 172         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID);
 173
 174         /* Disabled VF access */
 175         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 176                 u32 addr, data;
 177
 178                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 179                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 180                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 181                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 182                 DP_INFO(p_hwfn->p_dev, "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x] Write [0x%02x] Addr [0x%08x]\n",
 183                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK) >>
 184                              ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 185                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK) >>
 186                              ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 187                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 188                              ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 189                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 190                              ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 191                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 192                              ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 193                         addr);
 194         }
 195
 196         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 197                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 198         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 199                 u32 addr, data, length;
 200
 201                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 202                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 203                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 204                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 205                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 206                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 207
 208                 DP_INFO(p_hwfn->p_dev, "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
 209                         addr, length,
 210                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 211                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 212                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 213                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 214                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 215                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 216                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 217                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 218                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 219                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 220                         (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 221                              ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 222                         data);
 223         }
 224
 225         /* TODO - We know 'some' of these are legal due to virtualization,
 226          * but is it true for all of them?
 227          */
 228         return ECORE_SUCCESS;
 229 }
 230
 231 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 232 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 233 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 234 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 235 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 236 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 237 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 238 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 239 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 240 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 241 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 242 static const char* grc_timeout_attn_master_to_str(u8 master)
 243 {
 244         switch(master) {
 245         case 1: return "PXP";
 246         case 2: return "MCP";
 247         case 3: return "MSDM";
 248         case 4: return "PSDM";
 249         case 5: return "YSDM";
 250         case 6: return "USDM";
 251         case 7: return "TSDM";
 252         case 8: return "XSDM";
 253         case 9: return "DBU";
 254         case 10: return "DMAE";
 255         default:
 256                 return "Unkown";
 257         }
 258 }
 259
 260 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 261 {
 262         u32 tmp, tmp2;
 263
 264         /* We've already cleared the timeout interrupt register, so we learn
 265          * of interrupts via the validity register
 266          */
 267         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 268                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 269         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
 270                 goto out;
 271
 272         /* Read the GRC timeout information */
 273         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 274                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 275         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 276                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 277
 278         DP_NOTICE(p_hwfn->p_dev, false,
 279                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 280                   tmp2, tmp,
 281                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 282                                                        : "Read from",
 283                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 284                   grc_timeout_attn_master_to_str((tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 285                                                  ECORE_GRC_ATTENTION_MASTER_SHIFT),
 286                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 287                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 288                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 289                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 290                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 291                   ECORE_GRC_ATTENTION_VF_SHIFT);
 292
 293 out:
 294         /* Regardles of anything else, clean the validity bit */
 295         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 296                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 297         return ECORE_SUCCESS;
 298 }
 299
 300 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 301 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 302 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 303 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 304 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 305 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 306 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 307 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 308 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 309 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 310 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 311 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 312 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 313
 314 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 315                                                    struct ecore_ptt *p_ptt)
 316 {
 317         u32 tmp;
 318
 319         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 320         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 321                 u32 addr_lo, addr_hi, details;
 322
 323                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 324                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 325                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 326                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 327                 details = ecore_rd(p_hwfn, p_ptt,
 328                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 329
 330                 DP_NOTICE(p_hwfn, false,
 331                           "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 332                           addr_hi, addr_lo, details,
 333                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 334                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 335                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 336                           tmp,
 337                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
 338                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
 339                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
 340         }
 341
 342         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 343         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 344                 u32 addr_lo, addr_hi, details;
 345
 346                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 347                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 348                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 349                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 350                 details = ecore_rd(p_hwfn, p_ptt,
 351                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 352
 353                 DP_NOTICE(p_hwfn, false,
 354                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 355                           addr_hi, addr_lo, details,
 356                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 357                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 358                           (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 359                           tmp,
 360                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
 361                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
 362                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
 363         }
 364
 365         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 366         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 367                 DP_NOTICE(p_hwfn, false, "ICPL eror - %08x\n", tmp);
 368
 369         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 370         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 371                 u32 addr_hi, addr_lo;
 372
 373                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 374                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 375                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 376                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 377
 378                 DP_NOTICE(p_hwfn, false,
 379                           "ICPL eror - %08x [Address %08x:%08x]\n",
 380                           tmp, addr_hi, addr_lo);
 381         }
 382
 383         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 384         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 385                 u32 addr_hi, addr_lo, details;
 386
 387                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 388                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 389                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 390                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 391                 details = ecore_rd(p_hwfn, p_ptt,
 392                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 393
 394                 DP_NOTICE(p_hwfn, false,
 395                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 396                           details, tmp, addr_hi, addr_lo);
 397         }
 398
 399         /* Clear the indications */
 400         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 401
 402         return ECORE_SUCCESS;
 403 }
 404
 405 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 406 {
 407         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
 408 }
 409
 410 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 411 {
 412         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 413
 414         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 415
 416         return ECORE_INVAL;
 417 }
 418
 419 static enum _ecore_status_t
 420 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 421 {
 422         DP_INFO(p_hwfn, "General attention 35!\n");
 423
 424         return ECORE_SUCCESS;
 425 }
 426
 427 #define ECORE_DORQ_ATTENTION_REASON_MASK        (0xfffff)
 428 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK        (0xffff)
 429 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT       (0x0)
 430 #define ECORE_DORQ_ATTENTION_SIZE_MASK          (0x7f)
 431 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT         (16)
 432
 433 #define ECORE_DB_REC_COUNT                      10
 434 #define ECORE_DB_REC_INTERVAL                   100
 435
 436 /* assumes sticky overflow indication was set for this PF */
 437 static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn,
 438                                               struct ecore_ptt *p_ptt)
 439 {
 440         u8 count = ECORE_DB_REC_COUNT;
 441         u32 usage = 1;
 442
 443         /* wait for usage to zero or count to run out. This is necessary since
 444          * EDPM doorbell transactions can take multiple 64b cycles, and as such
 445          * can "split" over the pci. Possibly, the doorbell drop can happen with
 446          * half an EDPM in the queue and other half dropped. Another EDPM
 447          * doorbell to the same address (from doorbell recovery mechanism or
 448          * from the doorbelling entity) could have first half dropped and second
 449          * half interperted as continuation of the first. To prevent such
 450          * malformed doorbells from reaching the device, flush the queue before
 451          * releaseing the overflow sticky indication.
 452          */
 453         while (count-- && usage) {
 454                 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
 455                 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
 456         }
 457
 458         /* should have been depleted by now */
 459         if (usage) {
 460                 DP_NOTICE(p_hwfn->p_dev, false,
 461                           "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
 462                           ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
 463                 return ECORE_TIMEOUT;
 464         }
 465
 466         /* flush any pedning (e)dpm as they may never arrive */
 467         ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
 468
 469         /* release overflow sticky indication (stop silently dropping everything) */
 470         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
 471
 472         /* repeat all last doorbells (doorbell drop recovery) */
 473         ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
 474
 475         return ECORE_SUCCESS;
 476 }
 477
 478 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 479 {
 480         u32 int_sts, first_drop_reason, details, address, overflow,
 481                 all_drops_reason;
 482         struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
 483         enum _ecore_status_t rc;
 484
 485         int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
 486         DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
 487                   int_sts);
 488
 489         /* int_sts may be zero since all PFs were interrupted for doorbell
 490          * overflow but another one already handled it. Can abort here. If
 491          * This PF also requires overflow recovery we will be interrupted again.
 492          * The masked almost full indication may also be set. Ignoring.
 493          */
 494         if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL))
 495                 return ECORE_SUCCESS;
 496
 497         /* check if db_drop or overflow happened */
 498         if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
 499                        DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
 500                 /* obtain data about db drop/overflow */
 501                 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
 502                                   DORQ_REG_DB_DROP_REASON) &
 503                                   ECORE_DORQ_ATTENTION_REASON_MASK;
 504                 details = ecore_rd(p_hwfn, p_ptt,
 505                                    DORQ_REG_DB_DROP_DETAILS);
 506                 address = ecore_rd(p_hwfn, p_ptt,
 507                                    DORQ_REG_DB_DROP_DETAILS_ADDRESS);
 508                 overflow = ecore_rd(p_hwfn, p_ptt,
 509                                     DORQ_REG_PF_OVFL_STICKY);
 510                 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
 511                                             DORQ_REG_DB_DROP_DETAILS_REASON);
 512
 513                 /* log info */
 514                 DP_NOTICE(p_hwfn->p_dev, false,
 515                           "Doorbell drop occurred\n"
 516                           "Address\t\t0x%08x\t(second BAR address)\n"
 517                           "FID\t\t0x%04x\t\t(Opaque FID)\n"
 518                           "Size\t\t0x%04x\t\t(in bytes)\n"
 519                           "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
 520                           "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n"
 521                           "Overflow\t0x%x\t\t(a per PF indication)\n",
 522                           address, GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
 523                           GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
 524                           first_drop_reason, all_drops_reason, overflow);
 525
 526                 /* if this PF caused overflow, initiate recovery */
 527                 if (overflow) {
 528                         rc = ecore_db_rec_attn(p_hwfn, p_ptt);
 529                         if (rc != ECORE_SUCCESS)
 530                                 return rc;
 531                 }
 532
 533                 /* clear the doorbell drop details and prepare for next drop */
 534                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
 535
 536                 /* mark interrupt as handeld (note: even if drop was due to a diffrent
 537                  * reason than overflow we mark as handled)
 538                  */
 539                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
 540                          DORQ_REG_INT_STS_DB_DROP | DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
 541
 542                 /* if there are no indications otherthan drop indications, success */
 543                 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
 544                                  DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
 545                                  DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
 546                         return ECORE_SUCCESS;
 547         }
 548
 549         /* some other indication was present - non recoverable */
 550         DP_INFO(p_hwfn, "DORQ fatal attention\n");
 551
 552         return ECORE_INVAL;
 553 }
 554
 555 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 556 {
 557 #ifndef ASIC_ONLY
 558         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 559                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 560                                    TM_REG_INT_STS_1);
 561
 562                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 563                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 564                         return ECORE_INVAL;
 565
 566                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 567                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 568                         DP_INFO(p_hwfn, "TM attention on emulation - most likely results of clock-ratios\n");
 569                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 570                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 571                        TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 572                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 573
 574                 return ECORE_SUCCESS;
 575         }
 576 #endif
 577
 578         return ECORE_INVAL;
 579 }
 580
 581 /* Instead of major changes to the data-structure, we have a some 'special'
 582  * identifiers for sources that changed meaning between adapters.
 583  */
 584 enum aeu_invert_reg_special_type {
 585         AEU_INVERT_REG_SPECIAL_CNIG_0,
 586         AEU_INVERT_REG_SPECIAL_CNIG_1,
 587         AEU_INVERT_REG_SPECIAL_CNIG_2,
 588         AEU_INVERT_REG_SPECIAL_CNIG_3,
 589         AEU_INVERT_REG_SPECIAL_MAX,
 590 };
 591
 592 static struct aeu_invert_reg_bit
 593 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 594         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 595         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 596         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 597         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 598 };
 599
 600 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 601 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] =
 602 {
 603         {
 604                 {       /* After Invert 1 */
 605                         {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
 606                 }
 607         },
 608
 609         {
 610                 {       /* After Invert 2 */
 611                         {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 612                         {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 613                         {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb, BLOCK_PGLUE_B},
 614                         {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 615                         {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 616                         {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 617                         {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 618                         {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
 619                         {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, BLOCK_PGLCS},
 620                 }
 621         },
 622
 623         {
 624                 {       /* After Invert 3 */
 625                         {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
 626                 }
 627         },
 628
 629         {
 630                 {       /* After Invert 4 */
 631                         {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_fw_assertion, MAX_BLOCK_ID},
 632                         {"General Attention %d", (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
 633                         {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_general_attention_35, MAX_BLOCK_ID},
 634                         {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 635                                        ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0) , OSAL_NULL, BLOCK_NWS},
 636                         {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 637                                           ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), OSAL_NULL, BLOCK_NWS},
 638                         {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 639                                        ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), OSAL_NULL, BLOCK_NWM},
 640                         {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 641                                           ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), OSAL_NULL, BLOCK_NWM},
 642                         {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 643                         {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 644                         {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 645                         {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 646                         {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 647                         {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 648                         {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
 649                         {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 650                         {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 651                         {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 652                         {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 653                         {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 654                 }
 655         },
 656
 657         {
 658                 {       /* After Invert 5 */
 659                         {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 660                         {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 661                         {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 662                         {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 663                         {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 664                         {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 665                         {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 666                         {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 667                         {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 668                         {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 669                         {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 670                         {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 671                         {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 672                         {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 673                         {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 674                         {"TSEM", ATTENTION_PAR_INT,  OSAL_NULL, BLOCK_TSEM},
 675                 }
 676         },
 677
 678         {
 679                 {       /* After Invert 6 */
 680                         {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 681                         {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 682                         {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 683                         {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 684                         {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 685                         {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 686                         {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 687                         {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 688                         {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 689                         {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 690                         {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 691                         {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 692                         {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 693                         {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 694                         {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 695                         {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 696                 }
 697         },
 698
 699         {
 700                 {       /* After Invert 7 */
 701                         {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 702                         {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 703                         {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 704                         {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 705                         {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 706                         {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 707                         {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 708                         {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 709                         {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 710                         {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 711                         {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 712                         {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 713                         {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 714                         {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 715                         {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 716                         {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 717                         {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 718                 }
 719         },
 720
 721         {
 722                 {       /* After Invert 8 */
 723                         {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 724                         {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 725                         {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 726                         {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 727                         {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 728                         {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 729                         {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 730                         {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 731                         {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 732                         {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 733                         {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 734                         {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 735                         {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 736                         {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 737                         {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 738                         {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 739                         {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 740                         {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 741                         {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 742                         {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 743                         {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
 744                 }
 745         },
 746
 747         {
 748                 {       /* After Invert 9 */
 749                         {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 750                         {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 751                         {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 752                         {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 753                         {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
 754                 }
 755         },
 756
 757 };
 758
 759 static struct aeu_invert_reg_bit *
 760 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 761                         struct aeu_invert_reg_bit *p_bit)
 762 {
 763         if (!ECORE_IS_BB(p_hwfn->p_dev))
 764                 return p_bit;
 765
 766         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 767                 return p_bit;
 768
 769         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 770                                   ATTENTION_BB_SHIFT];
 771 }
 772
 773 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 774                                      struct aeu_invert_reg_bit *p_bit)
 775 {
 776         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 777                   ATTENTION_PARITY);
 778 }
 779
 780 #define ATTN_STATE_BITS         (0xfff)
 781 #define ATTN_BITS_MASKABLE      (0x3ff)
 782 struct ecore_sb_attn_info {
 783         /* Virtual & Physical address of the SB */
 784         struct atten_status_block       *sb_attn;
 785         dma_addr_t                      sb_phys;
 786
 787         /* Last seen running index */
 788         u16                             index;
 789
 790         /* A mask of the AEU bits resulting in a parity error */
 791         u32                             parity_mask[NUM_ATTN_REGS];
 792
 793         /* A pointer to the attention description structure */
 794         struct aeu_invert_reg           *p_aeu_desc;
 795
 796         /* Previously asserted attentions, which are still unasserted */
 797         u16                             known_attn;
 798
 799         /* Cleanup address for the link's general hw attention */
 800         u32                             mfw_attn_addr;
 801 };
 802
 803 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 804                                  struct ecore_sb_attn_info *p_sb_desc)
 805 {
 806         u16 rc = 0, index;
 807
 808         OSAL_MMIOWB(p_hwfn->p_dev);
 809
 810         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 811         if (p_sb_desc->index != index) {
 812                 p_sb_desc->index = index;
 813                 rc = ECORE_SB_ATT_IDX;
 814         }
 815
 816         OSAL_MMIOWB(p_hwfn->p_dev);
 817
 818         return rc;
 819 }
 820
 821 /**
 822  * @brief ecore_int_assertion - handles asserted attention bits
 823  *
 824  * @param p_hwfn
 825  * @param asserted_bits newly asserted bits
 826  * @return enum _ecore_status_t
 827  */
 828 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 829                                                 u16 asserted_bits)
 830 {
 831         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 832         u32 igu_mask;
 833
 834         /* Mask the source of the attention in the IGU */
 835         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 836                             IGU_REG_ATTENTION_ENABLE);
 837         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 838                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 839         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 840         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 841
 842         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 843                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 844                    sb_attn_sw->known_attn,
 845                    sb_attn_sw->known_attn | asserted_bits);
 846         sb_attn_sw->known_attn |= asserted_bits;
 847
 848         /* Handle MCP events */
 849         if (asserted_bits & 0x100) {
 850                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 851                 /* Clean the MCP attention */
 852                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 853                          sb_attn_sw->mfw_attn_addr, 0);
 854         }
 855
 856         /* FIXME - this will change once we'll have GOOD gtt definitions */
 857         DIRECT_REG_WR(p_hwfn,
 858                       (u8 OSAL_IOMEM*)p_hwfn->regview +
 859                       GTT_BAR0_MAP_REG_IGU_CMD +
 860                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 861                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 862
 863         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 864                    asserted_bits);
 865
 866         return ECORE_SUCCESS;
 867 }
 868
 869 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 870                                  enum block_id id, enum dbg_attn_type type,
 871                                  bool b_clear)
 872 {
 873         struct dbg_attn_block_result attn_results;
 874         enum dbg_status status;
 875
 876         OSAL_MEMSET(&attn_results, 0, sizeof(attn_results));
 877
 878         status = ecore_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
 879                                      b_clear, &attn_results);
 880 #ifdef ATTN_DESC
 881         if (status != DBG_STATUS_OK)
 882                 DP_NOTICE(p_hwfn, true,
 883                           "Failed to parse attention information [status: %s]\n",
 884                           ecore_dbg_get_status_str(status));
 885         else
 886                 ecore_dbg_parse_attn(p_hwfn, &attn_results);
 887 #else
 888         if (status != DBG_STATUS_OK)
 889                 DP_NOTICE(p_hwfn, true,
 890                           "Failed to parse attention information [status: %d]\n",
 891                           status);
 892         else
 893                 ecore_dbg_print_attn(p_hwfn, &attn_results);
 894 #endif
 895 }
 896
 897 /**
 898  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 899  * cause of the attention
 900  *
 901  * @param p_hwfn
 902  * @param p_aeu - descriptor of an AEU bit which caused the attention
 903  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 904  *  this bit to this group.
 905  * @param bit_index - index of this bit in the aeu_en_reg
 906  *
 907  * @return enum _ecore_status_t
 908  */
 909 static enum _ecore_status_t
 910 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 911                               struct aeu_invert_reg_bit *p_aeu,
 912                               u32 aeu_en_reg,
 913                               const char *p_bit_name,
 914                               u32 bitmask)
 915 {
 916         enum _ecore_status_t rc = ECORE_INVAL;
 917         bool b_fatal = false;
 918
 919         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 920                 p_bit_name, bitmask);
 921
 922         /* Call callback before clearing the interrupt status */
 923         if (p_aeu->cb) {
 924                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 925                         p_bit_name);
 926                 rc = p_aeu->cb(p_hwfn);
 927         }
 928
 929         if (rc != ECORE_SUCCESS)
 930                 b_fatal = true;
 931
 932         /* Print HW block interrupt registers */
 933         if (p_aeu->block_index != MAX_BLOCK_ID)
 934                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 935                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 936
 937         /* Reach assertion if attention is fatal */
 938         if (b_fatal) {
 939                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 940                           p_bit_name);
 941
 942                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 943         }
 944
 945         /* Prevent this Attention from being asserted in the future */
 946         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 947             p_hwfn->p_dev->attn_clr_en) {
 948                 u32 val;
 949                 u32 mask = ~bitmask;
 950                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 951                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 952                 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
 953                         p_bit_name);
 954         }
 955
 956         return rc;
 957 }
 958
 959 /**
 960  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 961  *
 962  * @param p_hwfn
 963  * @param p_aeu - descriptor of an AEU bit which caused the parity
 964  * @param aeu_en_reg - address of the AEU enable register
 965  * @param bit_index
 966  */
 967 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 968                                          struct aeu_invert_reg_bit *p_aeu,
 969                                          u32 aeu_en_reg, u8 bit_index)
 970 {
 971         u32 block_id = p_aeu->block_index, mask, val;
 972
 973         DP_NOTICE(p_hwfn->p_dev, false,
 974                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 975                   p_aeu->bit_name, aeu_en_reg, bit_index);
 976
 977         if (block_id != MAX_BLOCK_ID) {
 978                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 979
 980                 /* In A0, there's a single parity bit for several blocks */
 981                 if (block_id == BLOCK_BTB) {
 982                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
 983                                              ATTN_TYPE_PARITY, false);
 984                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
 985                                              ATTN_TYPE_PARITY, false);
 986                 }
 987         }
 988
 989         /* Prevent this parity error from being re-asserted */
 990         mask = ~(0x1 << bit_index);
 991         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 992         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
 993         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
 994                 p_aeu->bit_name);
 995 }
 996
 997 /**
 998  * @brief - handles deassertion of previously asserted attentions.
 999  *
1000  * @param p_hwfn
1001  * @param deasserted_bits - newly deasserted bits
1002  * @return enum _ecore_status_t
1003  *
1004  */
1005 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1006                                                   u16 deasserted_bits)
1007 {
1008         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1009         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1010         u8 i, j, k, bit_idx;
1011         enum _ecore_status_t rc = ECORE_SUCCESS;
1012
1013         /* Read the attention registers in the AEU */
1014         for (i = 0; i < NUM_ATTN_REGS; i++) {
1015                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1016                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
1017                                           i * 0x4);
1018                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1019                            "Deasserted bits [%d]: %08x\n",
1020                            i, aeu_inv_arr[i]);
1021         }
1022
1023         /* Handle parity attentions first */
1024         for (i = 0; i < NUM_ATTN_REGS; i++)
1025         {
1026                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1027                 u32 parities;
1028
1029                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1030                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1031                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1032
1033                 /* Skip register in which no parity bit is currently set */
1034                 if (!parities)
1035                         continue;
1036
1037                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1038                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1039
1040                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1041                             !!(parities & (1 << bit_idx)))
1042                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
1043                                                              aeu_en, bit_idx);
1044
1045                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
1046                 }
1047         }
1048
1049         /* Find non-parity cause for attention and act */
1050         for (k = 0; k < MAX_ATTN_GRPS; k++) {
1051                 struct aeu_invert_reg_bit *p_aeu;
1052
1053                 /* Handle only groups whose attention is currently deasserted */
1054                 if (!(deasserted_bits & (1 << k)))
1055                         continue;
1056
1057                 for (i = 0; i < NUM_ATTN_REGS; i++) {
1058                         u32 bits;
1059
1060                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1061                                  i * sizeof(u32) +
1062                                  k * sizeof(u32) * NUM_ATTN_REGS;
1063                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1064                         bits = aeu_inv_arr[i] & en;
1065
1066                         /* Skip if no bit from this group is currently set */
1067                         if (!bits)
1068                                 continue;
1069
1070                         /* Find all set bits from current register which belong
1071                          * to current group, making them responsible for the
1072                          * previous assertion.
1073                          */
1074                         for (j = 0, bit_idx = 0; bit_idx < 32; j++)
1075                         {
1076                                 long unsigned int bitmask;
1077                                 u8 bit, bit_len;
1078
1079                                 /* Need to account bits with changed meaning */
1080                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1081                                 p_aeu = ecore_int_aeu_translate(p_hwfn, p_aeu);
1082
1083                                 bit = bit_idx;
1084                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1085                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1086                                         /* Skip Parity */
1087                                         bit++;
1088                                         bit_len--;
1089                                 }
1090
1091                                 /* Find the bits relating to HW-block, then
1092                                  * shift so they'll become LSB.
1093                                  */
1094                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
1095                                 bitmask >>= bit;
1096
1097                                 if (bitmask) {
1098                                         u32 flags = p_aeu->flags;
1099                                         char bit_name[30];
1100                                         u8 num;
1101
1102                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1103                                                                 bit_len);
1104
1105                                         /* Some bits represent more than a
1106                                          * a single interrupt. Correctly print
1107                                          * their name.
1108                                          */
1109                                         if (ATTENTION_LENGTH(flags) > 2 ||
1110                                             ((flags & ATTENTION_PAR_INT) &&
1111                                             ATTENTION_LENGTH(flags) > 1))
1112                                                 OSAL_SNPRINTF(bit_name, 30,
1113                                                               p_aeu->bit_name,
1114                                                               num);
1115                                         else
1116                                                 OSAL_STRNCPY(bit_name,
1117                                                              p_aeu->bit_name,
1118                                                              30);
1119
1120                                         /* We now need to pass bitmask in its
1121                                          * correct position.
1122                                          */
1123                                         bitmask <<= bit;
1124
1125                                         /* Handle source of the attention */
1126                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1127                                                                       p_aeu,
1128                                                                       aeu_en,
1129                                                                       bit_name,
1130                                                                       bitmask);
1131                                 }
1132
1133                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1134                         }
1135                 }
1136         }
1137
1138         /* Clear IGU indication for the deasserted bits */
1139         /* FIXME - this will change once we'll have GOOD gtt definitions */
1140         DIRECT_REG_WR(p_hwfn,
1141                       (u8 OSAL_IOMEM*)p_hwfn->regview +
1142                                       GTT_BAR0_MAP_REG_IGU_CMD +
1143                                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1144                                         IGU_CMD_INT_ACK_BASE) << 3),
1145                       ~((u32)deasserted_bits));
1146
1147         /* Unmask deasserted attentions in IGU */
1148         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1149                             IGU_REG_ATTENTION_ENABLE);
1150         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1151         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1152
1153         /* Clear deassertion from inner state */
1154         sb_attn_sw->known_attn &= ~deasserted_bits;
1155
1156         return rc;
1157 }
1158
1159 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1160 {
1161         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1162         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1163         u16 index = 0, asserted_bits, deasserted_bits;
1164         u32 attn_bits = 0, attn_acks = 0;
1165         enum _ecore_status_t rc = ECORE_SUCCESS;
1166
1167         /* Read current attention bits/acks - safeguard against attentions
1168          * by guaranting work on a synchronized timeframe
1169          */
1170         do {
1171                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1172                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1173                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1174         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1175         p_sb_attn->sb_index = index;
1176
1177         /* Attention / Deassertion are meaningful (and in correct state)
1178          * only when they differ and consistent with known state - deassertion
1179          * when previous attention & current ack, and assertion when current
1180          * attention with no previous attention
1181          */
1182         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1183                         ~p_sb_attn_sw->known_attn;
1184         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1185                           p_sb_attn_sw->known_attn;
1186
1187         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1188                 DP_INFO(p_hwfn,
1189                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1190                         index, attn_bits, attn_acks, asserted_bits,
1191                         deasserted_bits, p_sb_attn_sw->known_attn);
1192         else if (asserted_bits == 0x100)
1193                 DP_INFO(p_hwfn,
1194                         "MFW indication via attention\n");
1195         else
1196                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1197                            "MFW indication [deassertion]\n");
1198
1199         if (asserted_bits) {
1200                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1201                 if (rc)
1202                         return rc;
1203         }
1204
1205         if (deasserted_bits)
1206                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1207
1208         return rc;
1209 }
1210
1211 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1212                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1213 {
1214         struct igu_prod_cons_update igu_ack = { 0 };
1215
1216         igu_ack.sb_id_and_flags =
1217                 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1218                  (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1219                  (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1220                  (IGU_SEG_ACCESS_ATTN <<
1221                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1222
1223         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1224
1225         /* Both segments (interrupts & acks) are written to same place address;
1226          * Need to guarantee all commands will be received (in-order) by HW.
1227          */
1228         OSAL_MMIOWB(p_hwfn->p_dev);
1229         OSAL_BARRIER(p_hwfn->p_dev);
1230 }
1231
1232 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1233 {
1234         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1235         struct ecore_pi_info *pi_info = OSAL_NULL;
1236         struct ecore_sb_attn_info *sb_attn;
1237         struct ecore_sb_info *sb_info;
1238         int arr_size;
1239         u16 rc = 0;
1240
1241         if (!p_hwfn)
1242                 return;
1243
1244         if (!p_hwfn->p_sp_sb) {
1245                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1246                 return;
1247         }
1248
1249         sb_info = &p_hwfn->p_sp_sb->sb_info;
1250         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1251         if (!sb_info) {
1252                 DP_ERR(p_hwfn->p_dev, "Status block is NULL - cannot ack interrupts\n");
1253                 return;
1254         }
1255
1256         if (!p_hwfn->p_sb_attn) {
1257                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1258                 return;
1259         }
1260         sb_attn =  p_hwfn->p_sb_attn;
1261
1262         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1263                    p_hwfn, p_hwfn->my_id);
1264
1265         /* Disable ack for def status block. Required both for msix +
1266          * inta in non-mask mode, in inta does no harm.
1267          */
1268         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1269
1270         /* Gather Interrupts/Attentions information */
1271         if (!sb_info->sb_virt) {
1272                 DP_ERR(p_hwfn->p_dev, "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1273         } else {
1274                 u32 tmp_index = sb_info->sb_ack;
1275                 rc = ecore_sb_update_sb_idx(sb_info);
1276                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1277                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1278                            tmp_index, sb_info->sb_ack);
1279         }
1280
1281         if (!sb_attn || !sb_attn->sb_attn) {
1282                 DP_ERR(p_hwfn->p_dev, "Attentions Status block is NULL - cannot check for new attentions!\n");
1283         } else {
1284                 u16 tmp_index = sb_attn->index;
1285
1286                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1287                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1288                            "Attention indices: 0x%08x --> 0x%08x\n",
1289                            tmp_index, sb_attn->index);
1290         }
1291
1292         /* Check if we expect interrupts at this time. if not just ack them */
1293         if (!(rc & ECORE_SB_EVENT_MASK)) {
1294                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1295                 return;
1296         }
1297
1298         /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1299         if (!p_hwfn->p_dpc_ptt) {
1300                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1301                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1302                 return;
1303         }
1304
1305         if (rc & ECORE_SB_ATT_IDX)
1306                 ecore_int_attentions(p_hwfn);
1307
1308         if (rc & ECORE_SB_IDX) {
1309                 int pi;
1310
1311                 /* Since we only looked at the SB index, it's possible more
1312                  * than a single protocol-index on the SB incremented.
1313                  * Iterate over all configured protocol indices and check
1314                  * whether something happened for each.
1315                  */
1316                 for (pi = 0; pi < arr_size; pi++) {
1317                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1318                         if (pi_info->comp_cb != OSAL_NULL)
1319                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1320                 }
1321         }
1322
1323         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1324                 /* This should be done before the interrupts are enabled,
1325                  * since otherwise a new attention will be generated.
1326                  */
1327                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1328         }
1329
1330         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1331 }
1332
1333 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1334 {
1335         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1336
1337         if (!p_sb)
1338                 return;
1339
1340         if (p_sb->sb_attn) {
1341                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1342                                        p_sb->sb_phys,
1343                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1344         }
1345
1346         OSAL_FREE(p_hwfn->p_dev, p_sb);
1347         p_hwfn->p_sb_attn = OSAL_NULL;
1348 }
1349
1350 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1351                                     struct ecore_ptt *p_ptt)
1352 {
1353         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1354
1355         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1356
1357         sb_info->index = 0;
1358         sb_info->known_attn = 0;
1359
1360         /* Configure Attention Status Block in IGU */
1361         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1362                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1363         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1364                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1365 }
1366
1367 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1368                                    struct ecore_ptt *p_ptt,
1369                                    void *sb_virt_addr,
1370                                    dma_addr_t sb_phy_addr)
1371 {
1372         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1373         int i, j, k;
1374
1375         sb_info->sb_attn = sb_virt_addr;
1376         sb_info->sb_phys = sb_phy_addr;
1377
1378         /* Set the pointer to the AEU descriptors */
1379         sb_info->p_aeu_desc = aeu_descs;
1380
1381         /* Calculate Parity Masks */
1382         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1383         for (i = 0; i < NUM_ATTN_REGS; i++) {
1384                 /* j is array index, k is bit index */
1385                 for (j = 0, k = 0; k < 32; j++) {
1386                         struct aeu_invert_reg_bit *p_aeu;
1387
1388                         p_aeu = &aeu_descs[i].bits[j];
1389                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1390                                 sb_info->parity_mask[i] |= 1 << k;
1391
1392                         k += ATTENTION_LENGTH(p_aeu->flags);
1393                 }
1394                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1395                            "Attn Mask [Reg %d]: 0x%08x\n",
1396                            i, sb_info->parity_mask[i]);
1397         }
1398
1399         /* Set the address of cleanup for the mcp attention */
1400         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1401                                  MISC_REG_AEU_GENERAL_ATTN_0;
1402
1403         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1404 }
1405
1406 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1407                                                     struct ecore_ptt *p_ptt)
1408 {
1409         struct ecore_dev *p_dev = p_hwfn->p_dev;
1410         struct ecore_sb_attn_info *p_sb;
1411         dma_addr_t p_phys = 0;
1412         void *p_virt;
1413
1414         /* SB struct */
1415         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1416         if (!p_sb) {
1417                 DP_NOTICE(p_dev, false, "Failed to allocate `struct ecore_sb_attn_info'\n");
1418                 return ECORE_NOMEM;
1419         }
1420
1421         /* SB ring  */
1422         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1423                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1424         if (!p_virt) {
1425                 DP_NOTICE(p_dev, false, "Failed to allocate status block (attentions)\n");
1426                 OSAL_FREE(p_dev, p_sb);
1427                 return ECORE_NOMEM;
1428         }
1429
1430         /* Attention setup */
1431         p_hwfn->p_sb_attn = p_sb;
1432         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1433
1434         return ECORE_SUCCESS;
1435 }
1436
1437 /* coalescing timeout = timeset << (timer_res + 1) */
1438 #define ECORE_CAU_DEF_RX_USECS 24
1439 #define ECORE_CAU_DEF_TX_USECS 48
1440
1441 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1442                              struct cau_sb_entry *p_sb_entry,
1443                              u8 pf_id, u16 vf_number, u8 vf_valid)
1444 {
1445         struct ecore_dev *p_dev = p_hwfn->p_dev;
1446         u32 cau_state;
1447         u8 timer_res;
1448
1449         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1450
1451         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1452         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1453         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1454         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1455         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1456
1457         cau_state = CAU_HC_DISABLE_STATE;
1458
1459         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1460                 cau_state = CAU_HC_ENABLE_STATE;
1461                 if (!p_dev->rx_coalesce_usecs)
1462                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1463                 if (!p_dev->tx_coalesce_usecs)
1464                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1465         }
1466
1467         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1468         if (p_dev->rx_coalesce_usecs <= 0x7F)
1469                 timer_res = 0;
1470         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1471                 timer_res = 1;
1472         else
1473                 timer_res = 2;
1474         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1475
1476         if (p_dev->tx_coalesce_usecs <= 0x7F)
1477                 timer_res = 0;
1478         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1479                 timer_res = 1;
1480         else
1481                 timer_res = 2;
1482         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1483
1484         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1485         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1486 }
1487
1488 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1489                                    struct ecore_ptt *p_ptt,
1490                                    u16 igu_sb_id, u32 pi_index,
1491                                    enum ecore_coalescing_fsm coalescing_fsm,
1492                                    u8 timeset)
1493 {
1494         struct cau_pi_entry pi_entry;
1495         u32 sb_offset, pi_offset;
1496
1497         if (IS_VF(p_hwfn->p_dev))
1498                 return;/* @@@TBD MichalK- VF CAU... */
1499
1500         sb_offset = igu_sb_id * PIS_PER_SB_E4;
1501         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1502
1503         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1504         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1505                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1506         else
1507                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1508
1509         pi_offset = sb_offset + pi_index;
1510         if (p_hwfn->hw_init_done) {
1511                 ecore_wr(p_hwfn, p_ptt,
1512                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1513                          *((u32 *)&(pi_entry)));
1514         } else {
1515                 STORE_RT_REG(p_hwfn,
1516                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1517                              *((u32 *)&(pi_entry)));
1518         }
1519 }
1520
1521 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1522                            struct ecore_ptt *p_ptt,
1523                            struct ecore_sb_info *p_sb, u32 pi_index,
1524                            enum ecore_coalescing_fsm coalescing_fsm,
1525                            u8 timeset)
1526 {
1527         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1528                                pi_index, coalescing_fsm, timeset);
1529 }
1530
1531 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1532                            struct ecore_ptt *p_ptt,
1533                            dma_addr_t sb_phys, u16 igu_sb_id,
1534                            u16 vf_number, u8 vf_valid)
1535 {
1536         struct cau_sb_entry sb_entry;
1537
1538         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1539                                 vf_number, vf_valid);
1540
1541         if (p_hwfn->hw_init_done) {
1542                 /* Wide-bus, initialize via DMAE */
1543                 u64 phys_addr = (u64)sb_phys;
1544
1545                 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&phys_addr,
1546                                     CAU_REG_SB_ADDR_MEMORY +
1547                                     igu_sb_id * sizeof(u64), 2,
1548                                     OSAL_NULL /* default parameters */);
1549                 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&sb_entry,
1550                                     CAU_REG_SB_VAR_MEMORY +
1551                                     igu_sb_id * sizeof(u64), 2,
1552                                     OSAL_NULL /* default parameters */);
1553         } else {
1554                 /* Initialize Status Block Address */
1555                 STORE_RT_REG_AGG(p_hwfn,
1556                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET+igu_sb_id*2,
1557                                  sb_phys);
1558
1559                 STORE_RT_REG_AGG(p_hwfn,
1560                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET+igu_sb_id*2,
1561                                  sb_entry);
1562         }
1563
1564         /* Configure pi coalescing if set */
1565         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1566                 /* eth will open queues for all tcs, so configure all of them
1567                  * properly, rather than just the active ones
1568                  */
1569                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1570
1571                 u8 timeset, timer_res;
1572                 u8 i;
1573
1574                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1575                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1576                         timer_res = 0;
1577                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1578                         timer_res = 1;
1579                 else
1580                         timer_res = 2;
1581                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1582                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1583                                        ECORE_COAL_RX_STATE_MACHINE,
1584                                        timeset);
1585
1586                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1587                         timer_res = 0;
1588                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1589                         timer_res = 1;
1590                 else
1591                         timer_res = 2;
1592                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1593                 for (i = 0; i < num_tc; i++) {
1594                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1595                                                igu_sb_id, TX_PI(i),
1596                                                ECORE_COAL_TX_STATE_MACHINE,
1597                                                timeset);
1598                 }
1599         }
1600 }
1601
1602 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1603                                struct ecore_ptt *p_ptt,
1604                                struct ecore_sb_info *sb_info)
1605 {
1606         /* zero status block and ack counter */
1607         sb_info->sb_ack = 0;
1608         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1609
1610         if (IS_PF(p_hwfn->p_dev))
1611                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1612                                       sb_info->igu_sb_id, 0, 0);
1613 }
1614
1615 struct ecore_igu_block *
1616 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1617 {
1618         struct ecore_igu_block *p_block;
1619         u16 igu_id;
1620
1621         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1622              igu_id++) {
1623                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1624
1625                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1626                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1627                         continue;
1628
1629                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1630                     b_is_pf)
1631                         return p_block;
1632         }
1633
1634         return OSAL_NULL;
1635 }
1636
1637 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1638                                   u16 vector_id)
1639 {
1640         struct ecore_igu_block *p_block;
1641         u16 igu_id;
1642
1643         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1644              igu_id++) {
1645                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1646
1647                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1648                     !p_block->is_pf ||
1649                     p_block->vector_number != vector_id)
1650                         continue;
1651
1652                 return igu_id;
1653         }
1654
1655         return ECORE_SB_INVALID_IDX;
1656 }
1657
1658 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1659 {
1660         u16 igu_sb_id;
1661
1662         /* Assuming continuous set of IGU SBs dedicated for given PF */
1663         if (sb_id == ECORE_SP_SB_ID)
1664                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1665         else if (IS_PF(p_hwfn->p_dev))
1666                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1667         else
1668                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1669
1670         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1671                 DP_NOTICE(p_hwfn, true,
1672                           "Slowpath SB vector %04x doesn't exist\n",
1673                           sb_id);
1674         else if (sb_id == ECORE_SP_SB_ID)
1675                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1676                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1677         else
1678                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1679                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1680
1681         return igu_sb_id;
1682 }
1683
1684 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1685                                        struct ecore_ptt *p_ptt,
1686                                        struct ecore_sb_info *sb_info,
1687                                        void *sb_virt_addr,
1688                                        dma_addr_t sb_phy_addr,
1689                                        u16 sb_id)
1690 {
1691         sb_info->sb_virt = sb_virt_addr;
1692         sb_info->sb_phys = sb_phy_addr;
1693
1694         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1695
1696         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1697                 return ECORE_INVAL;
1698
1699         /* Let the igu info reference the client's SB info */
1700         if (sb_id != ECORE_SP_SB_ID) {
1701                 if (IS_PF(p_hwfn->p_dev)) {
1702                         struct ecore_igu_info *p_info;
1703                         struct ecore_igu_block *p_block;
1704
1705                         p_info = p_hwfn->hw_info.p_igu_info;
1706                         p_block = &p_info->entry[sb_info->igu_sb_id];
1707
1708                         p_block->sb_info = sb_info;
1709                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1710                         p_info->usage.free_cnt--;
1711                 } else {
1712                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1713                 }
1714         }
1715
1716 #ifdef ECORE_CONFIG_DIRECT_HWFN
1717         sb_info->p_hwfn = p_hwfn;
1718 #endif
1719         sb_info->p_dev = p_hwfn->p_dev;
1720
1721         /* The igu address will hold the absolute address that needs to be
1722          * written to for a specific status block
1723          */
1724         if (IS_PF(p_hwfn->p_dev)) {
1725                 sb_info->igu_addr = (u8 OSAL_IOMEM*)p_hwfn->regview +
1726                                     GTT_BAR0_MAP_REG_IGU_CMD +
1727                                     (sb_info->igu_sb_id << 3);
1728
1729         } else {
1730                 sb_info->igu_addr =
1731                         (u8 OSAL_IOMEM*)p_hwfn->regview +
1732                         PXP_VF_BAR0_START_IGU +
1733                         ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1734         }
1735
1736         sb_info->flags |= ECORE_SB_INFO_INIT;
1737
1738         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1739
1740         return ECORE_SUCCESS;
1741 }
1742
1743 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1744                                           struct ecore_sb_info *sb_info,
1745                                           u16 sb_id)
1746 {
1747         struct ecore_igu_info *p_info;
1748         struct ecore_igu_block *p_block;
1749
1750         if (sb_info == OSAL_NULL)
1751                 return ECORE_SUCCESS;
1752
1753         /* zero status block and ack counter */
1754         sb_info->sb_ack = 0;
1755         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1756
1757         if (IS_VF(p_hwfn->p_dev)) {
1758                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1759                 return ECORE_SUCCESS;
1760         }
1761
1762         p_info = p_hwfn->hw_info.p_igu_info;
1763         p_block = &p_info->entry[sb_info->igu_sb_id];
1764
1765         /* Vector 0 is reserved to Default SB */
1766         if (p_block->vector_number == 0) {
1767                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1768                 return ECORE_INVAL;
1769         }
1770
1771         /* Lose reference to client's SB info, and fix counters */
1772         p_block->sb_info = OSAL_NULL;
1773         p_block->status |= ECORE_IGU_STATUS_FREE;
1774         p_info->usage.free_cnt++;
1775
1776         return ECORE_SUCCESS;
1777 }
1778
1779 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1780 {
1781         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1782
1783         if (!p_sb)
1784                 return;
1785
1786         if (p_sb->sb_info.sb_virt) {
1787                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1788                                        p_sb->sb_info.sb_virt,
1789                                        p_sb->sb_info.sb_phys,
1790                                        SB_ALIGNED_SIZE(p_hwfn));
1791         }
1792
1793         OSAL_FREE(p_hwfn->p_dev, p_sb);
1794         p_hwfn->p_sp_sb = OSAL_NULL;
1795 }
1796
1797 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1798                                                   struct ecore_ptt *p_ptt)
1799 {
1800         struct ecore_sb_sp_info *p_sb;
1801         dma_addr_t p_phys = 0;
1802         void *p_virt;
1803
1804         /* SB struct */
1805         p_sb = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_sb));
1806         if (!p_sb) {
1807                 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_sb_info'\n");
1808                 return ECORE_NOMEM;
1809         }
1810
1811         /* SB ring  */
1812         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1813                                          &p_phys,
1814                                          SB_ALIGNED_SIZE(p_hwfn));
1815         if (!p_virt) {
1816                 DP_NOTICE(p_hwfn, false, "Failed to allocate status block\n");
1817                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1818                 return ECORE_NOMEM;
1819         }
1820
1821         /* Status Block setup */
1822         p_hwfn->p_sp_sb = p_sb;
1823         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1824                           p_virt, p_phys, ECORE_SP_SB_ID);
1825
1826         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1827
1828         return ECORE_SUCCESS;
1829 }
1830
1831 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1832                                            ecore_int_comp_cb_t comp_cb,
1833                                            void *cookie,
1834                                            u8 *sb_idx,
1835                                            __le16 **p_fw_cons)
1836 {
1837         struct ecore_sb_sp_info *p_sp_sb  = p_hwfn->p_sp_sb;
1838         enum _ecore_status_t rc = ECORE_NOMEM;
1839         u8 pi;
1840
1841         /* Look for a free index */
1842         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1843                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1844                         continue;
1845
1846                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1847                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1848                 *sb_idx = pi;
1849                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1850                 rc = ECORE_SUCCESS;
1851                 break;
1852         }
1853
1854         return rc;
1855 }
1856
1857 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn,
1858                                              u8 pi)
1859 {
1860         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1861
1862         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1863                 return ECORE_NOMEM;
1864
1865         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1866         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1867
1868         return ECORE_SUCCESS;
1869 }
1870
1871 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1872 {
1873         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1874 }
1875
1876 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1877                               struct ecore_ptt  *p_ptt,
1878                               enum ecore_int_mode int_mode)
1879 {
1880         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1881
1882 #ifndef ASIC_ONLY
1883         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1884                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1885                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1886         }
1887 #endif
1888
1889         p_hwfn->p_dev->int_mode = int_mode;
1890         switch (p_hwfn->p_dev->int_mode) {
1891         case ECORE_INT_MODE_INTA:
1892                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1893                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1894                 break;
1895
1896         case ECORE_INT_MODE_MSI:
1897                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1898                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1899                 break;
1900
1901         case ECORE_INT_MODE_MSIX:
1902                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1903                 break;
1904         case ECORE_INT_MODE_POLL:
1905                 break;
1906         }
1907
1908         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1909 }
1910
1911 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1912                                       struct ecore_ptt *p_ptt)
1913 {
1914 #ifndef ASIC_ONLY
1915         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1916                 DP_INFO(p_hwfn, "FPGA - Don't enable Attentions in IGU and MISC\n");
1917                 return;
1918         }
1919 #endif
1920
1921         /* Configure AEU signal change to produce attentions */
1922         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1923         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1924         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1925         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1926
1927         /* Flush the writes to IGU */
1928         OSAL_MMIOWB(p_hwfn->p_dev);
1929
1930         /* Unmask AEU signals toward IGU */
1931         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1932 }
1933
1934 enum _ecore_status_t
1935 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1936                           enum ecore_int_mode int_mode)
1937 {
1938         enum _ecore_status_t rc = ECORE_SUCCESS;
1939
1940         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1941
1942         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1943                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1944                 if (rc != ECORE_SUCCESS) {
1945                         DP_NOTICE(p_hwfn, true, "Slowpath IRQ request failed\n");
1946                         return ECORE_NORESOURCES;
1947                 }
1948                 p_hwfn->b_int_requested = true;
1949         }
1950
1951         /* Enable interrupt Generation */
1952         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1953
1954         p_hwfn->b_int_enabled = 1;
1955
1956         return rc;
1957 }
1958
1959 void ecore_int_igu_disable_int(struct ecore_hwfn        *p_hwfn,
1960                                struct ecore_ptt         *p_ptt)
1961 {
1962         p_hwfn->b_int_enabled = 0;
1963
1964         if (IS_VF(p_hwfn->p_dev))
1965                 return;
1966
1967         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1968 }
1969
1970 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1971 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1972                                      struct ecore_ptt *p_ptt,
1973                                      u16 igu_sb_id,
1974                                      bool cleanup_set,
1975                                      u16 opaque_fid)
1976 {
1977         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1978         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1979         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1980         u8  type = 0; /* FIXME MichalS type??? */
1981
1982         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1983                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1984
1985         /* USE Control Command Register to perform cleanup. There is an
1986          * option to do this using IGU bar, but then it can't be used for VFs.
1987          */
1988
1989         /* Set the data field */
1990         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1991         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1992         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1993
1994         /* Set the control register */
1995         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1996         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1997         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1998
1999         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
2000
2001         OSAL_BARRIER(p_hwfn->p_dev);
2002
2003         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2004
2005         /* Flush the write to IGU */
2006         OSAL_MMIOWB(p_hwfn->p_dev);
2007
2008         /* calculate where to read the status bit from */
2009         sb_bit = 1 << (igu_sb_id % 32);
2010         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2011
2012         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2013
2014         /* Now wait for the command to complete */
2015         while (--sleep_cnt) {
2016                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2017                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2018                         break;
2019                 OSAL_MSLEEP(5);
2020         }
2021
2022         if (!sleep_cnt)
2023                 DP_NOTICE(p_hwfn, true,
2024                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2025                           val, igu_sb_id);
2026 }
2027
2028 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2029                                        struct ecore_ptt *p_ptt,
2030                                        u16 igu_sb_id, u16 opaque, bool b_set)
2031 {
2032         struct ecore_igu_block *p_block;
2033         int pi, i;
2034
2035         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2036         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2037                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2038                    igu_sb_id, p_block->function_id, p_block->is_pf,
2039                    p_block->vector_number);
2040
2041         /* Set */
2042         if (b_set)
2043                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2044
2045         /* Clear */
2046         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2047
2048         /* Wait for the IGU SB to cleanup */
2049         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2050                 u32 val;
2051
2052                 val = ecore_rd(p_hwfn, p_ptt,
2053                                IGU_REG_WRITE_DONE_PENDING +
2054                                ((igu_sb_id / 32) * 4));
2055                 if (val & (1 << (igu_sb_id % 32)))
2056                         OSAL_UDELAY(10);
2057                 else
2058                         break;
2059         }
2060         if (i == IGU_CLEANUP_SLEEP_LENGTH)
2061                 DP_NOTICE(p_hwfn, true,
2062                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2063                           igu_sb_id);
2064
2065         /* Clear the CAU for the SB */
2066         for (pi = 0; pi < 12; pi++)
2067                 ecore_wr(p_hwfn, p_ptt,
2068                          CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
2069 }
2070
2071 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2072                                  struct ecore_ptt *p_ptt,
2073                                  bool b_set,
2074                                  bool b_slowpath)
2075 {
2076         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2077         struct ecore_igu_block *p_block;
2078         u16 igu_sb_id = 0;
2079         u32 val = 0;
2080
2081         /* @@@TBD MichalK temporary... should be moved to init-tool... */
2082         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2083         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2084         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2085         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2086         /* end temporary */
2087
2088         for (igu_sb_id = 0;
2089              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2090              igu_sb_id++) {
2091                 p_block = &p_info->entry[igu_sb_id];
2092
2093                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2094                     !p_block->is_pf ||
2095                     (p_block->status & ECORE_IGU_STATUS_DSB))
2096                         continue;
2097
2098                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2099                                                   p_hwfn->hw_info.opaque_fid,
2100                                                   b_set);
2101         }
2102
2103         if (b_slowpath)
2104                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2105                                                   p_info->igu_dsb_id,
2106                                                   p_hwfn->hw_info.opaque_fid,
2107                                                   b_set);
2108 }
2109
2110 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2111                             struct ecore_ptt *p_ptt)
2112 {
2113         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2114         struct ecore_igu_block *p_block;
2115         int pf_sbs, vf_sbs;
2116         u16 igu_sb_id;
2117         u32 val, rval;
2118
2119         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2120                 /* We're using an old MFW - have to prevent any switching
2121                  * of SBs between PF and VFs as later driver wouldn't be
2122                  * able to tell which belongs to which.
2123                  */
2124                 p_info->b_allow_pf_vf_change = false;
2125         } else {
2126                 /* Use the numbers the MFW have provided -
2127                  * don't forget MFW accounts for the default SB as well.
2128                  */
2129                 p_info->b_allow_pf_vf_change = true;
2130
2131                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2132                         DP_INFO(p_hwfn,
2133                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2134                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2135                                 p_info->usage.cnt);
2136                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2137                 }
2138
2139                 /* TODO - how do we learn about VF SBs from MFW? */
2140                 if (IS_PF_SRIOV(p_hwfn)) {
2141                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2142
2143                         if (vfs != p_info->usage.iov_cnt)
2144                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2145                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2146                                            p_info->usage.iov_cnt, vfs);
2147
2148                         /* At this point we know how many SBs we have totally
2149                          * in IGU + number of PF SBs. So we can validate that
2150                          * we'd have sufficient for VF.
2151                          */
2152                         if (vfs > p_info->usage.free_cnt +
2153                                   p_info->usage.free_cnt_iov -
2154                                   p_info->usage.cnt) {
2155                                 DP_NOTICE(p_hwfn, true,
2156                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2157                                           p_info->usage.free_cnt +
2158                                           p_info->usage.free_cnt_iov,
2159                                           p_info->usage.cnt, vfs);
2160                                 return ECORE_INVAL;
2161                         }
2162                 }
2163         }
2164
2165         /* Cap the number of VFs SBs by the number of VFs */
2166         if (IS_PF_SRIOV(p_hwfn))
2167                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2168
2169         /* Mark all SBs as free, now in the right PF/VFs division */
2170         p_info->usage.free_cnt = p_info->usage.cnt;
2171         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2172         p_info->usage.orig = p_info->usage.cnt;
2173         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2174
2175         /* We now proceed to re-configure the IGU cam to reflect the initial
2176          * configuration. We can start with the Default SB.
2177          */
2178         pf_sbs = p_info->usage.cnt;
2179         vf_sbs = p_info->usage.iov_cnt;
2180
2181         for (igu_sb_id = p_info->igu_dsb_id;
2182              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2183              igu_sb_id++) {
2184                 p_block = &p_info->entry[igu_sb_id];
2185                 val = 0;
2186
2187                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2188                         continue;
2189
2190                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2191                         p_block->function_id = p_hwfn->rel_pf_id;
2192                         p_block->is_pf = 1;
2193                         p_block->vector_number = 0;
2194                         p_block->status = ECORE_IGU_STATUS_VALID |
2195                                           ECORE_IGU_STATUS_PF |
2196                                           ECORE_IGU_STATUS_DSB;
2197                 } else if (pf_sbs) {
2198                         pf_sbs--;
2199                         p_block->function_id = p_hwfn->rel_pf_id;
2200                         p_block->is_pf = 1;
2201                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2202                         p_block->status = ECORE_IGU_STATUS_VALID |
2203                                           ECORE_IGU_STATUS_PF |
2204                                           ECORE_IGU_STATUS_FREE;
2205                 } else if (vf_sbs) {
2206                         p_block->function_id =
2207                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2208                                 p_info->usage.iov_cnt - vf_sbs;
2209                         p_block->is_pf = 0;
2210                         p_block->vector_number = 0;
2211                         p_block->status = ECORE_IGU_STATUS_VALID |
2212                                           ECORE_IGU_STATUS_FREE;
2213                         vf_sbs--;
2214                 } else {
2215                         p_block->function_id = 0;
2216                         p_block->is_pf = 0;
2217                         p_block->vector_number = 0;
2218                 }
2219
2220                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2221                           p_block->function_id);
2222                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2223                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2224                           p_block->vector_number);
2225
2226                 /* VF entries would be enabled when VF is initializaed */
2227                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2228
2229                 rval = ecore_rd(p_hwfn, p_ptt,
2230                                 IGU_REG_MAPPING_MEMORY +
2231                                 sizeof(u32) * igu_sb_id);
2232
2233                 if (rval != val) {
2234                         ecore_wr(p_hwfn, p_ptt,
2235                                  IGU_REG_MAPPING_MEMORY +
2236                                  sizeof(u32) * igu_sb_id,
2237                                  val);
2238
2239                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2240                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2241                                    igu_sb_id, p_block->function_id,
2242                                    p_block->is_pf, p_block->vector_number,
2243                                    rval, val);
2244                 }
2245         }
2246
2247         return 0;
2248 }
2249
2250 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2251                                     struct ecore_ptt *p_ptt)
2252 {
2253         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2254
2255         /* Return all the usage indications to default prior to the reset;
2256          * The reset expects the !orig to reflect the initial status of the
2257          * SBs, and would re-calculate the originals based on those.
2258          */
2259         p_cnt->cnt = p_cnt->orig;
2260         p_cnt->free_cnt = p_cnt->orig;
2261         p_cnt->iov_cnt = p_cnt->iov_orig;
2262         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2263         p_cnt->orig = 0;
2264         p_cnt->iov_orig = 0;
2265
2266         /* TODO - we probably need to re-configure the CAU as well... */
2267         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2268 }
2269
2270 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2271                                          struct ecore_ptt *p_ptt,
2272                                          u16 igu_sb_id)
2273 {
2274         u32 val = ecore_rd(p_hwfn, p_ptt,
2275                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2276         struct ecore_igu_block *p_block;
2277
2278         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2279
2280         /* Fill the block information */
2281         p_block->function_id = GET_FIELD(val,
2282                                          IGU_MAPPING_LINE_FUNCTION_NUMBER);
2283         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2284         p_block->vector_number = GET_FIELD(val,
2285                                            IGU_MAPPING_LINE_VECTOR_NUMBER);
2286         p_block->igu_sb_id = igu_sb_id;
2287 }
2288
2289 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2290                                             struct ecore_ptt *p_ptt)
2291 {
2292         struct ecore_igu_info *p_igu_info;
2293         struct ecore_igu_block *p_block;
2294         u32 min_vf = 0, max_vf = 0;
2295         u16 igu_sb_id;
2296
2297         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2298                                                  GFP_KERNEL,
2299                                                  sizeof(*p_igu_info));
2300         if (!p_hwfn->hw_info.p_igu_info)
2301                 return ECORE_NOMEM;
2302         p_igu_info = p_hwfn->hw_info.p_igu_info;
2303
2304         /* Distinguish between existent and onn-existent default SB */
2305         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2306
2307         /* Find the range of VF ids whose SB belong to this PF */
2308         if (p_hwfn->p_dev->p_iov_info) {
2309                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2310
2311                 min_vf = p_iov->first_vf_in_pf;
2312                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2313         }
2314
2315         for (igu_sb_id = 0;
2316              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2317              igu_sb_id++) {
2318                 /* Read current entry; Notice it might not belong to this PF */
2319                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2320                 p_block = &p_igu_info->entry[igu_sb_id];
2321
2322                 if ((p_block->is_pf) &&
2323                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2324                         p_block->status = ECORE_IGU_STATUS_PF |
2325                                           ECORE_IGU_STATUS_VALID |
2326                                           ECORE_IGU_STATUS_FREE;
2327
2328                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2329                                 p_igu_info->usage.cnt++;
2330                 } else if (!(p_block->is_pf) &&
2331                            (p_block->function_id >= min_vf) &&
2332                            (p_block->function_id < max_vf)) {
2333                         /* Available for VFs of this PF */
2334                         p_block->status = ECORE_IGU_STATUS_VALID |
2335                                           ECORE_IGU_STATUS_FREE;
2336
2337                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2338                                 p_igu_info->usage.iov_cnt++;
2339                 }
2340
2341                 /* Mark the First entry belonging to the PF or its VFs
2342                  * as the default SB [we'll reset IGU prior to first usage].
2343                  */
2344                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2345                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2346                         p_igu_info->igu_dsb_id = igu_sb_id;
2347                         p_block->status |= ECORE_IGU_STATUS_DSB;
2348                 }
2349
2350                 /* While this isn't suitable for all clients, limit number
2351                  * of prints by having each PF print only its entries with the
2352                  * exception of PF0 which would print everything.
2353                  */
2354                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2355                     (p_hwfn->abs_pf_id == 0))
2356                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2357                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2358                                    igu_sb_id, p_block->function_id,
2359                                    p_block->is_pf, p_block->vector_number);
2360         }
2361
2362         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2363                 DP_NOTICE(p_hwfn, true,
2364                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2365                           p_igu_info->igu_dsb_id);
2366                 return ECORE_INVAL;
2367         }
2368
2369         /* All non default SB are considered free at this point */
2370         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2371         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2372
2373         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2374                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2375                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2376                    p_igu_info->usage.iov_cnt);
2377
2378         return ECORE_SUCCESS;
2379 }
2380
2381 enum _ecore_status_t
2382 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2383                           u16 sb_id, bool b_to_vf)
2384 {
2385         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2386         struct ecore_igu_block *p_block = OSAL_NULL;
2387         u16 igu_sb_id = 0, vf_num = 0;
2388         u32 val = 0;
2389
2390         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2391                 return ECORE_INVAL;
2392
2393         if (sb_id == ECORE_SP_SB_ID)
2394                 return ECORE_INVAL;
2395
2396         if (!p_info->b_allow_pf_vf_change) {
2397                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2398                 return ECORE_INVAL;
2399         }
2400
2401         /* If we're moving a SB from PF to VF, the client had to specify
2402          * which vector it wants to move.
2403          */
2404         if (b_to_vf) {
2405                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2406                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2407                         return ECORE_INVAL;
2408         }
2409
2410         /* If we're moving a SB from VF to PF, need to validate there isn't
2411          * already a line configured for that vector.
2412          */
2413         if (!b_to_vf) {
2414                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2415                     ECORE_SB_INVALID_IDX)
2416                         return ECORE_INVAL;
2417         }
2418
2419         /* We need to validate that the SB can actually be relocated.
2420          * This would also handle the previous case where we've explicitly
2421          * stated which IGU SB needs to move.
2422          */
2423         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2424              igu_sb_id++) {
2425                 p_block = &p_info->entry[igu_sb_id];
2426
2427                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2428                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2429                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2430                         if (b_to_vf)
2431                                 return ECORE_INVAL;
2432                         else
2433                                 continue;
2434                 }
2435
2436                 break;
2437         }
2438
2439         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2440                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2441                            "Failed to find a free SB to move\n");
2442                 return ECORE_INVAL;
2443         }
2444
2445         if (p_block == OSAL_NULL) {
2446                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2447                            "SB address (p_block) is NULL\n");
2448                 return ECORE_INVAL;
2449         }
2450
2451         /* At this point, p_block points to the SB we want to relocate */
2452         if (b_to_vf) {
2453                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2454
2455                 /* It doesn't matter which VF number we choose, since we're
2456                  * going to disable the line; But let's keep it in range.
2457                  */
2458                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2459
2460                 p_block->function_id = (u8)vf_num;
2461                 p_block->is_pf = 0;
2462                 p_block->vector_number = 0;
2463
2464                 p_info->usage.cnt--;
2465                 p_info->usage.free_cnt--;
2466                 p_info->usage.iov_cnt++;
2467                 p_info->usage.free_cnt_iov++;
2468
2469                 /* TODO - if SBs aren't really the limiting factor,
2470                  * then it might not be accurate [in the since that
2471                  * we might not need decrement the feature].
2472                  */
2473                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2474                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2475         } else {
2476                 p_block->status |= ECORE_IGU_STATUS_PF;
2477                 p_block->function_id = p_hwfn->rel_pf_id;
2478                 p_block->is_pf = 1;
2479                 p_block->vector_number = sb_id + 1;
2480
2481                 p_info->usage.cnt++;
2482                 p_info->usage.free_cnt++;
2483                 p_info->usage.iov_cnt--;
2484                 p_info->usage.free_cnt_iov--;
2485
2486                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2487                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2488         }
2489
2490         /* Update the IGU and CAU with the new configuration */
2491         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2492                   p_block->function_id);
2493         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2494         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2495         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2496                   p_block->vector_number);
2497
2498         ecore_wr(p_hwfn, p_ptt,
2499                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2500                  val);
2501
2502         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2503                               igu_sb_id, vf_num,
2504                               p_block->is_pf ? 0 : 1);
2505
2506         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2507                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2508                    igu_sb_id, p_block->function_id,
2509                    p_block->is_pf, p_block->vector_number);
2510
2511         return ECORE_SUCCESS;
2512 }
2513
2514 /**
2515  * @brief Initialize igu runtime registers
2516  *
2517  * @param p_hwfn
2518  */
2519 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2520 {
2521         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2522
2523         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2524 }
2525
2526 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2527                           IGU_CMD_INT_ACK_BASE)
2528 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2529                           IGU_CMD_INT_ACK_BASE)
2530 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2531 {
2532         u32 intr_status_hi = 0, intr_status_lo = 0;
2533         u64 intr_status = 0;
2534
2535         intr_status_lo = REG_RD(p_hwfn,
2536                                 GTT_BAR0_MAP_REG_IGU_CMD +
2537                                 LSB_IGU_CMD_ADDR * 8);
2538         intr_status_hi = REG_RD(p_hwfn,
2539                                 GTT_BAR0_MAP_REG_IGU_CMD +
2540                                 MSB_IGU_CMD_ADDR * 8);
2541         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2542
2543         return intr_status;
2544 }
2545
2546 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2547 {
2548         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2549         p_hwfn->b_sp_dpc_enabled = true;
2550 }
2551
2552 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2553 {
2554         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2555         if (!p_hwfn->sp_dpc)
2556                 return ECORE_NOMEM;
2557
2558         return ECORE_SUCCESS;
2559 }
2560
2561 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2562 {
2563         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2564         p_hwfn->sp_dpc = OSAL_NULL;
2565 }
2566
2567 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2568                                      struct ecore_ptt *p_ptt)
2569 {
2570         enum _ecore_status_t rc = ECORE_SUCCESS;
2571
2572         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2573         if (rc != ECORE_SUCCESS) {
2574                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2575                 return rc;
2576         }
2577
2578         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2579         if (rc != ECORE_SUCCESS) {
2580                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2581                 return rc;
2582         }
2583
2584         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2585         if (rc != ECORE_SUCCESS)
2586                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2587
2588         return rc;
2589 }
2590
2591 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2592 {
2593         ecore_int_sp_sb_free(p_hwfn);
2594         ecore_int_sb_attn_free(p_hwfn);
2595         ecore_int_sp_dpc_free(p_hwfn);
2596 }
2597
2598 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2599 {
2600         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2601                 return;
2602
2603         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2604         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2605         ecore_int_sp_dpc_setup(p_hwfn);
2606 }
2607
2608 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2609                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2610 {
2611         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2612
2613         if (!p_igu_info || !p_sb_cnt_info)
2614                 return;
2615
2616         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2617                     sizeof(*p_sb_cnt_info));
2618 }
2619
2620 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2621 {
2622         int i;
2623
2624         for_each_hwfn(p_dev, i)
2625                 p_dev->hwfns[i].b_int_requested = false;
2626 }
2627
2628 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2629 {
2630         p_dev->attn_clr_en = clr_enable;
2631 }
2632
2633 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2634                                              struct ecore_ptt *p_ptt,
2635                                              u8 timer_res, u16 sb_id, bool tx)
2636 {
2637         struct cau_sb_entry sb_entry;
2638         enum _ecore_status_t rc;
2639
2640         if (!p_hwfn->hw_init_done) {
2641                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2642                 return ECORE_INVAL;
2643         }
2644
2645         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2646                                  sb_id * sizeof(u64),
2647                                  (u64)(osal_uintptr_t)&sb_entry, 2,
2648                                  OSAL_NULL /* default parameters */);
2649         if (rc != ECORE_SUCCESS) {
2650                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2651                 return rc;
2652         }
2653
2654         if (tx)
2655                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2656         else
2657                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2658
2659         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2660                                  (u64)(osal_uintptr_t)&sb_entry,
2661                                  CAU_REG_SB_VAR_MEMORY + sb_id * sizeof(u64), 2,
2662                                  OSAL_NULL /* default parameters */);
2663         if (rc != ECORE_SUCCESS) {
2664                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2665                 return rc;
2666         }
2667
2668         return rc;
2669 }
2670
2671 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2672                                           struct ecore_ptt *p_ptt,
2673                                           struct ecore_sb_info *p_sb,
2674                                           struct ecore_sb_info_dbg *p_info)
2675 {
2676         u16 sbid = p_sb->igu_sb_id;
2677         int i;
2678
2679         if (IS_VF(p_hwfn->p_dev))
2680                 return ECORE_INVAL;
2681
2682         if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2683                 return ECORE_INVAL;
2684
2685         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2686                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2687         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2688                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2689
2690         for (i = 0; i < PIS_PER_SB_E4; i++)
2691                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2692                                               CAU_REG_PI_MEMORY +
2693                                               sbid * 4 * PIS_PER_SB_E4 + i * 4);
2694
2695         return ECORE_SUCCESS;
2696 }