sys/dev/qlnx/qlnxe/ecore_int_api.h

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  *
  29  */
  30
  31 #ifndef __ECORE_INT_API_H__
  32 #define __ECORE_INT_API_H__
  33
  34 #include "common_hsi.h"
  35
  36 #ifndef __EXTRACT__LINUX__
  37 #define ECORE_SB_IDX            0x0002
  38
  39 #define RX_PI           0
  40 #define TX_PI(tc)       (RX_PI + 1 + tc)
  41
  42 #ifndef ECORE_INT_MODE
  43 #define ECORE_INT_MODE
  44 enum ecore_int_mode {
  45         ECORE_INT_MODE_INTA,
  46         ECORE_INT_MODE_MSIX,
  47         ECORE_INT_MODE_MSI,
  48         ECORE_INT_MODE_POLL,
  49 };
  50 #endif
  51
  52 struct ecore_sb_info {
  53         struct status_block_e4 *sb_virt;
  54         dma_addr_t sb_phys;
  55         u32 sb_ack; /* Last given ack */
  56         u16 igu_sb_id;
  57         void OSAL_IOMEM *igu_addr;
  58         u8 flags;
  59 #define ECORE_SB_INFO_INIT      0x1
  60 #define ECORE_SB_INFO_SETUP     0x2
  61
  62 #ifdef ECORE_CONFIG_DIRECT_HWFN
  63         struct ecore_hwfn *p_hwfn;
  64 #endif
  65         struct ecore_dev *p_dev;
  66 };
  67
  68 struct ecore_sb_info_dbg {
  69         u32 igu_prod;
  70         u32 igu_cons;
  71         u16 pi[PIS_PER_SB_E4];
  72 };
  73
  74 struct ecore_sb_cnt_info {
  75         /* Original, current, and free SBs for PF */
  76         int orig;
  77         int cnt;
  78         int free_cnt;
  79
  80         /* Original, current and free SBS for child VFs */
  81         int iov_orig;
  82         int iov_cnt;
  83         int free_cnt_iov;
  84 };
  85
  86 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
  87 {
  88         u32 prod = 0;
  89         u16 rc   = 0;
  90
  91         // barrier(); /* status block is written to by the chip */
  92         // FIXME: need some sort of barrier.
  93         prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
  94                STATUS_BLOCK_E4_PROD_INDEX_MASK;
  95         if (sb_info->sb_ack != prod) {
  96                 sb_info->sb_ack = prod;
  97                 rc |= ECORE_SB_IDX;
  98         }
  99
 100         OSAL_MMIOWB(sb_info->p_dev);
 101         return rc;
 102 }
 103
 104 /**
 105  * @brief This function creates an update command for interrupts that is
 106  *        written to the IGU.
 107  *
 108  * @param sb_info       - This is the structure allocated and
 109  *                 initialized per status block. Assumption is
 110  *                 that it was initialized using ecore_sb_init
 111  * @param int_cmd       - Enable/Disable/Nop
 112  * @param upd_flg       - whether igu consumer should be
 113  *                 updated.
 114  *
 115  * @return OSAL_INLINE void
 116  */
 117 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
 118                                      enum igu_int_cmd int_cmd, u8 upd_flg)
 119 {
 120         struct igu_prod_cons_update igu_ack = { 0 };
 121
 122 #ifndef ECORE_CONFIG_DIRECT_HWFN
 123         u32 val;
 124 #endif
 125
 126 #ifndef LINUX_REMOVE
 127         if (sb_info->p_dev->int_mode == ECORE_INT_MODE_POLL)
 128                 return;
 129 #endif
 130         igu_ack.sb_id_and_flags =
 131                  OSAL_CPU_TO_LE32((sb_info->sb_ack <<
 132                  IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 133                  (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 134                  (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 135                  (IGU_SEG_ACCESS_REG <<
 136                  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 137
 138 #ifdef ECORE_CONFIG_DIRECT_HWFN
 139         DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
 140                       igu_ack.sb_id_and_flags);
 141 #else
 142         val = OSAL_LE32_TO_CPU(igu_ack.sb_id_and_flags);
 143         DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, val);
 144 #endif
 145         /* Both segments (interrupts & acks) are written to same place address;
 146          * Need to guarantee all commands will be received (in-order) by HW.
 147          */
 148         OSAL_MMIOWB(sb_info->p_dev);
 149         OSAL_BARRIER(sb_info->p_dev);
 150 }
 151
 152 #ifdef ECORE_CONFIG_DIRECT_HWFN
 153 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
 154                                           void OSAL_IOMEM *addr,
 155                                           int size, u32 *data)
 156 #else
 157 static OSAL_INLINE void __internal_ram_wr(void *p_hwfn,
 158                                           void OSAL_IOMEM *addr,
 159                                           int size, u32 *data)
 160
 161 #endif
 162 {
 163         unsigned int i;
 164
 165         for (i = 0; i < size / sizeof(*data); i++)
 166                 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
 167 }
 168
 169 #ifdef ECORE_CONFIG_DIRECT_HWFN
 170 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
 171                                         void OSAL_IOMEM *addr,
 172                                         int size, u32 *data)
 173 {
 174         __internal_ram_wr(p_hwfn, addr, size, data);
 175 }
 176 #else
 177 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
 178                                         int size, u32 *data)
 179 {
 180         __internal_ram_wr(OSAL_NULL, addr, size, data);
 181 }
 182 #endif
 183 #endif
 184
 185 struct ecore_hwfn;
 186 struct ecore_ptt;
 187
 188 enum ecore_coalescing_fsm {
 189         ECORE_COAL_RX_STATE_MACHINE,
 190         ECORE_COAL_TX_STATE_MACHINE
 191 };
 192
 193 /**
 194  * @brief ecore_int_cau_conf_pi - configure cau for a given
 195  *        status block
 196  *
 197  * @param p_hwfn
 198  * @param p_ptt
 199  * @param p_sb
 200  * @param pi_index
 201  * @param state
 202  * @param timeset
 203  */
 204 void ecore_int_cau_conf_pi(struct ecore_hwfn            *p_hwfn,
 205                            struct ecore_ptt             *p_ptt,
 206                            struct ecore_sb_info         *p_sb,
 207                            u32                          pi_index,
 208                            enum ecore_coalescing_fsm    coalescing_fsm,
 209                            u8                           timeset);
 210
 211 /**
 212  * @brief ecore_int_igu_enable_int - enable device interrupts
 213  *
 214  * @param p_hwfn
 215  * @param p_ptt
 216  * @param int_mode - interrupt mode to use
 217  */
 218 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
 219                               struct ecore_ptt *p_ptt,
 220                               enum ecore_int_mode int_mode);
 221
 222 /**
 223  * @brief ecore_int_igu_disable_int - disable device interrupts
 224  *
 225  * @param p_hwfn
 226  * @param p_ptt
 227  */
 228 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
 229                                struct ecore_ptt *p_ptt);
 230
 231 /**
 232  * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
 233  *        register from igu.
 234  *
 235  * @param p_hwfn
 236  *
 237  * @return u64
 238  */
 239 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
 240
 241 #define ECORE_SP_SB_ID 0xffff
 242
 243 /**
 244  * @brief ecore_int_sb_init - Initializes the sb_info structure.
 245  *
 246  * once the structure is initialized it can be passed to sb related functions.
 247  *
 248  * @param p_hwfn
 249  * @param p_ptt
 250  * @param sb_info       points to an uninitialized (but
 251  *                      allocated) sb_info structure
 252  * @param sb_virt_addr
 253  * @param sb_phy_addr
 254  * @param sb_id         the sb_id to be used (zero based in driver)
 255  *                      should use ECORE_SP_SB_ID for SP Status block
 256  *
 257  * @return enum _ecore_status_t
 258  */
 259 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn        *p_hwfn,
 260                                        struct ecore_ptt         *p_ptt,
 261                                        struct ecore_sb_info     *sb_info,
 262                                        void                     *sb_virt_addr,
 263                                        dma_addr_t               sb_phy_addr,
 264                                        u16                      sb_id);
 265 /**
 266  * @brief ecore_int_sb_setup - Setup the sb.
 267  *
 268  * @param p_hwfn
 269  * @param p_ptt
 270  * @param sb_info       initialized sb_info structure
 271  */
 272 void ecore_int_sb_setup(
 273                 struct ecore_hwfn       *p_hwfn,
 274                 struct ecore_ptt                *p_ptt,
 275                 struct ecore_sb_info    *sb_info);
 276
 277 /**
 278  * @brief ecore_int_sb_release - releases the sb_info structure.
 279  *
 280  * once the structure is released, it's memory can be freed
 281  *
 282  * @param p_hwfn
 283  * @param sb_info       points to an allocated sb_info structure
 284  * @param sb_id         the sb_id to be used (zero based in driver)
 285  *                      should never be equal to ECORE_SP_SB_ID
 286  *                      (SP Status block)
 287  *
 288  * @return enum _ecore_status_t
 289  */
 290 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn     *p_hwfn,
 291                                           struct ecore_sb_info  *sb_info,
 292                                           u16                   sb_id);
 293
 294 /**
 295  * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
 296  *        default status block.
 297  *
 298  * @param p_hwfn - pointer to hwfn
 299  *
 300  */
 301 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
 302
 303 /**
 304  * @brief ecore_int_get_num_sbs - get the number of status
 305  *        blocks configured for this funciton in the igu.
 306  *
 307  * @param p_hwfn
 308  * @param p_sb_cnt_info
 309  *
 310  * @return
 311  */
 312 void ecore_int_get_num_sbs(struct ecore_hwfn        *p_hwfn,
 313                            struct ecore_sb_cnt_info *p_sb_cnt_info);
 314
 315 /**
 316  * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
 317  *        release. The API need to be called after releasing all slowpath IRQs
 318  *        of the device.
 319  *
 320  * @param p_dev
 321  *
 322  */
 323 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
 324
 325 /**
 326  * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
 327  *        preventing attentions from being reasserted, or following the
 328  *        attributes of the specific attention.
 329  *
 330  * @param p_dev
 331  * @param clr_enable
 332  *
 333  */
 334 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
 335
 336 /**
 337  * @brief Read debug information regarding a given SB.
 338  *
 339  * @param p_hwfn
 340  * @param p_ptt
 341  * @param p_sb - point to Status block for which we want to get info.
 342  * @param p_info - pointer to struct to fill with information regarding SB.
 343  *
 344  * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
 345  */
 346 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
 347                                           struct ecore_ptt *p_ptt,
 348                                           struct ecore_sb_info *p_sb,
 349                                           struct ecore_sb_info_dbg *p_info);
 350
 351 /**
 352  * @brief - Move a free Status block between PF and child VF
 353  *
 354  * @param p_hwfn
 355  * @param p_ptt
 356  * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
 357  *                from VF, given-up if moving to VF]
 358  * @param b_to_vf - PF->VF == true, VF->PF == false
 359  *
 360  * @return ECORE_SUCCESS if SB successfully moved.
 361  */
 362 enum _ecore_status_t
 363 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 364                           u16 sb_id, bool b_to_vf);
 365 #endif