2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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10 * notice, this list of conditions and the following disclaimer.
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13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 #ifndef __ECORE_INT_API_H__
32 #define __ECORE_INT_API_H__
34 #include "common_hsi.h"
36 #ifndef __EXTRACT__LINUX__
37 #define ECORE_SB_IDX 0x0002
40 #define TX_PI(tc) (RX_PI + 1 + tc)
42 #ifndef ECORE_INT_MODE
43 #define ECORE_INT_MODE
52 struct ecore_sb_info {
53 struct status_block_e4 *sb_virt;
55 u32 sb_ack; /* Last given ack */
57 void OSAL_IOMEM *igu_addr;
59 #define ECORE_SB_INFO_INIT 0x1
60 #define ECORE_SB_INFO_SETUP 0x2
62 #ifdef ECORE_CONFIG_DIRECT_HWFN
63 struct ecore_hwfn *p_hwfn;
65 struct ecore_dev *p_dev;
68 struct ecore_sb_info_dbg {
71 u16 pi[PIS_PER_SB_E4];
74 struct ecore_sb_cnt_info {
75 /* Original, current, and free SBs for PF */
80 /* Original, current and free SBS for child VFs */
86 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
91 // barrier(); /* status block is written to by the chip */
92 // FIXME: need some sort of barrier.
93 prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
94 STATUS_BLOCK_E4_PROD_INDEX_MASK;
95 if (sb_info->sb_ack != prod) {
96 sb_info->sb_ack = prod;
100 OSAL_MMIOWB(sb_info->p_dev);
105 * @brief This function creates an update command for interrupts that is
106 * written to the IGU.
108 * @param sb_info - This is the structure allocated and
109 * initialized per status block. Assumption is
110 * that it was initialized using ecore_sb_init
111 * @param int_cmd - Enable/Disable/Nop
112 * @param upd_flg - whether igu consumer should be
115 * @return OSAL_INLINE void
117 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
118 enum igu_int_cmd int_cmd, u8 upd_flg)
120 struct igu_prod_cons_update igu_ack = { 0 };
122 #ifndef ECORE_CONFIG_DIRECT_HWFN
127 if (sb_info->p_dev->int_mode == ECORE_INT_MODE_POLL)
130 igu_ack.sb_id_and_flags =
131 OSAL_CPU_TO_LE32((sb_info->sb_ack <<
132 IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
133 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
134 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
135 (IGU_SEG_ACCESS_REG <<
136 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
138 #ifdef ECORE_CONFIG_DIRECT_HWFN
139 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
140 igu_ack.sb_id_and_flags);
142 val = OSAL_LE32_TO_CPU(igu_ack.sb_id_and_flags);
143 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, val);
145 /* Both segments (interrupts & acks) are written to same place address;
146 * Need to guarantee all commands will be received (in-order) by HW.
148 OSAL_MMIOWB(sb_info->p_dev);
149 OSAL_BARRIER(sb_info->p_dev);
152 #ifdef ECORE_CONFIG_DIRECT_HWFN
153 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
154 void OSAL_IOMEM *addr,
157 static OSAL_INLINE void __internal_ram_wr(void *p_hwfn,
158 void OSAL_IOMEM *addr,
165 for (i = 0; i < size / sizeof(*data); i++)
166 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
169 #ifdef ECORE_CONFIG_DIRECT_HWFN
170 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
171 void OSAL_IOMEM *addr,
174 __internal_ram_wr(p_hwfn, addr, size, data);
177 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
180 __internal_ram_wr(OSAL_NULL, addr, size, data);
188 enum ecore_coalescing_fsm {
189 ECORE_COAL_RX_STATE_MACHINE,
190 ECORE_COAL_TX_STATE_MACHINE
194 * @brief ecore_int_cau_conf_pi - configure cau for a given
204 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
205 struct ecore_ptt *p_ptt,
206 struct ecore_sb_info *p_sb,
208 enum ecore_coalescing_fsm coalescing_fsm,
212 * @brief ecore_int_igu_enable_int - enable device interrupts
216 * @param int_mode - interrupt mode to use
218 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
219 struct ecore_ptt *p_ptt,
220 enum ecore_int_mode int_mode);
223 * @brief ecore_int_igu_disable_int - disable device interrupts
228 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
229 struct ecore_ptt *p_ptt);
232 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
239 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
241 #define ECORE_SP_SB_ID 0xffff
244 * @brief ecore_int_sb_init - Initializes the sb_info structure.
246 * once the structure is initialized it can be passed to sb related functions.
250 * @param sb_info points to an uninitialized (but
251 * allocated) sb_info structure
252 * @param sb_virt_addr
254 * @param sb_id the sb_id to be used (zero based in driver)
255 * should use ECORE_SP_SB_ID for SP Status block
257 * @return enum _ecore_status_t
259 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
260 struct ecore_ptt *p_ptt,
261 struct ecore_sb_info *sb_info,
263 dma_addr_t sb_phy_addr,
266 * @brief ecore_int_sb_setup - Setup the sb.
270 * @param sb_info initialized sb_info structure
272 void ecore_int_sb_setup(
273 struct ecore_hwfn *p_hwfn,
274 struct ecore_ptt *p_ptt,
275 struct ecore_sb_info *sb_info);
278 * @brief ecore_int_sb_release - releases the sb_info structure.
280 * once the structure is released, it's memory can be freed
283 * @param sb_info points to an allocated sb_info structure
284 * @param sb_id the sb_id to be used (zero based in driver)
285 * should never be equal to ECORE_SP_SB_ID
288 * @return enum _ecore_status_t
290 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
291 struct ecore_sb_info *sb_info,
295 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
296 * default status block.
298 * @param p_hwfn - pointer to hwfn
301 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
304 * @brief ecore_int_get_num_sbs - get the number of status
305 * blocks configured for this funciton in the igu.
308 * @param p_sb_cnt_info
312 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
313 struct ecore_sb_cnt_info *p_sb_cnt_info);
316 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
317 * release. The API need to be called after releasing all slowpath IRQs
323 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
326 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
327 * preventing attentions from being reasserted, or following the
328 * attributes of the specific attention.
334 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
337 * @brief Read debug information regarding a given SB.
341 * @param p_sb - point to Status block for which we want to get info.
342 * @param p_info - pointer to struct to fill with information regarding SB.
344 * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
346 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
347 struct ecore_ptt *p_ptt,
348 struct ecore_sb_info *p_sb,
349 struct ecore_sb_info_dbg *p_info);
352 * @brief - Move a free Status block between PF and child VF
356 * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
357 * from VF, given-up if moving to VF]
358 * @param b_to_vf - PF->VF == true, VF->PF == false
360 * @return ECORE_SUCCESS if SB successfully moved.
363 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
364 u16 sb_id, bool b_to_vf);