2 * Copyright (c) 2018-2019 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 #ifndef __ECORE_RDMA_API_H__
31 #define __ECORE_RDMA_API_H__
39 #ifndef __EXTRACT__LINUX__
41 enum ecore_roce_ll2_tx_dest
43 ECORE_ROCE_LL2_TX_DEST_NW /* Light L2 TX Destination to the Network */,
44 ECORE_ROCE_LL2_TX_DEST_LB /* Light L2 TX Destination to the Loopback */,
45 ECORE_ROCE_LL2_TX_DEST_MAX
48 /* HW/FW RoCE Limitations (external. For internal see ecore_roce.h) */
49 /* CNQ size Limitation
50 * The CNQ size should be set as twice the amount of CQs, since for each CQ one
51 * element may be inserted into the CNQ and another element is used per CQ to
52 * accommodate for a possible race in the arm mechanism.
53 * The FW supports a CNQ of 64k-1 and this apparently causes an issue - notice
54 * that the number of QPs can reach 32k giving 64k CQs and 128k CNQ elements.
55 * Luckily the FW can buffer CNQ elements avoiding an overflow, on the expense
58 #define ECORE_RDMA_MAX_CNQ_SIZE (0xFFFF) /* 2^16 - 1 */
62 enum ecore_roce_qp_state {
63 ECORE_ROCE_QP_STATE_RESET, /* Reset */
64 ECORE_ROCE_QP_STATE_INIT, /* Initialized */
65 ECORE_ROCE_QP_STATE_RTR, /* Ready to Receive */
66 ECORE_ROCE_QP_STATE_RTS, /* Ready to Send */
67 ECORE_ROCE_QP_STATE_SQD, /* Send Queue Draining */
68 ECORE_ROCE_QP_STATE_ERR, /* Error */
69 ECORE_ROCE_QP_STATE_SQE /* Send Queue Error */
72 enum ecore_rdma_qp_type {
73 ECORE_RDMA_QP_TYPE_RC,
74 ECORE_RDMA_QP_TYPE_XRC_INI,
75 ECORE_RDMA_QP_TYPE_XRC_TGT,
76 ECORE_RDMA_QP_TYPE_INVAL = 0xffff,
79 enum ecore_rdma_tid_type
81 ECORE_RDMA_TID_REGISTERED_MR,
83 ECORE_RDMA_TID_MW_TYPE1,
84 ECORE_RDMA_TID_MW_TYPE2A
88 void (*affiliated_event_t)(void *context,
93 void (*unaffiliated_event_t)(void *context,
96 struct ecore_rdma_events {
98 affiliated_event_t affiliated_event;
99 unaffiliated_event_t unaffiliated_event;
102 struct ecore_rdma_device {
103 /* Vendor specific information */
109 u64 node_guid; /* node GUID */
110 u64 sys_image_guid; /* System image GUID */
113 u8 max_sge; /* The maximum number of scatter/gather entries
114 * per Work Request supported
116 u8 max_srq_sge; /* The maximum number of scatter/gather entries
117 * per Work Request supported for SRQ
120 u32 max_wqe; /* The maximum number of outstanding work
121 * requests on any Work Queue supported
123 u32 max_srq_wqe; /* The maximum number of outstanding work
124 * requests on any Work Queue supported for SRQ
126 u8 max_qp_resp_rd_atomic_resc; /* The maximum number of RDMA Reads
127 * & atomic operation that can be
131 u8 max_qp_req_rd_atomic_resc; /* The maximum depth per QP for
132 * initiation of RDMA Read
133 * & atomic operations
135 u64 max_dev_resp_rd_atomic_resc;
138 u32 max_srq; /* Maximum number of SRQs */
139 u32 max_mr; /* Maximum number of MRs supported by this device */
140 u64 max_mr_size; /* Size (in bytes) of the largest contiguous memory
141 * block that can be registered by this device
144 u32 max_mw; /* The maximum number of memory windows supported */
146 u32 max_mr_mw_fmr_pbl;
147 u64 max_mr_mw_fmr_size;
148 u32 max_pd; /* The maximum number of protection domains supported */
151 u16 max_srq_wr; /* Maximum number of WRs per SRQ */
152 u8 max_stats_queues; /* Maximum number of statistics queues */
155 /* Abilty to support RNR-NAK generation */
157 #define ECORE_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
158 #define ECORE_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
159 /* Abilty to support shutdown port */
160 #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
161 #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
162 /* Abilty to support port active event */
163 #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
164 #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
165 /* Abilty to support port change event */
166 #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
167 #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
168 /* Abilty to support system image GUID */
169 #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
170 #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
171 /* Abilty to support bad P_Key counter support */
172 #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
173 #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
174 /* Abilty to support atomic operations */
175 #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
176 #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
177 #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
178 #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
179 /* Abilty to support modifying the maximum number of
180 * outstanding work requests per QP
182 #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
183 #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
184 /* Abilty to support automatic path migration */
185 #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
186 #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
187 /* Abilty to support the base memory management extensions */
188 #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
189 #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
190 #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
191 #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
192 /* Abilty to support multipile page sizes per memory region */
193 #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
194 #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
195 /* Abilty to support block list physical buffer list */
196 #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
197 #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
198 /* Abilty to support zero based virtual addresses */
199 #define ECORE_RDMA_DEV_CAP_ZBVA_MASK 0x1
200 #define ECORE_RDMA_DEV_CAP_ZBVA_SHIFT 14
201 /* Abilty to support local invalidate fencing */
202 #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
203 #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
204 /* Abilty to support Loopback on QP */
205 #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
206 #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
209 u32 reserved_lkey; /* Value of reserved L_key */
210 u32 bad_pkey_counter; /* Bad P_key counter support indicator */
211 struct ecore_rdma_events events;
214 enum ecore_port_state {
216 ECORE_RDMA_PORT_DOWN,
219 enum ecore_roce_capability {
220 ECORE_ROCE_V1 = 1 << 0,
221 ECORE_ROCE_V2 = 1 << 1,
224 struct ecore_rdma_port {
225 enum ecore_port_state port_state;
228 u8 source_gid_table_len;
229 void *source_gid_table_ptr;
231 void *pkey_table_ptr;
232 u32 pkey_bad_counter;
233 enum ecore_roce_capability capability;
236 struct ecore_rdma_cnq_params
238 u8 num_pbl_pages; /* Number of pages in the PBL allocated
241 u64 pbl_ptr; /* Address to the first entry of the queue PBL */
244 /* The CQ Mode affects the CQ doorbell transaction size.
245 * 64/32 bit machines should configure to 32/16 bits respectively.
247 enum ecore_rdma_cq_mode {
248 ECORE_RDMA_CQ_MODE_16_BITS,
249 ECORE_RDMA_CQ_MODE_32_BITS,
252 struct ecore_roce_dcqcn_params {
253 u8 notification_point;
256 /* fields for notification point */
257 u32 cnp_send_timeout;
259 u8 cnp_vlan_priority;
261 /* fields for reaction point */
262 u32 rl_bc_rate; /* Byte Counter Limit. */
263 u32 rl_max_rate; /* Maximum rate in Mbps resolution */
264 u32 rl_r_ai; /* Active increase rate */
265 u32 rl_r_hai; /* Hyper active increase rate */
266 u32 dcqcn_gd; /* Alpha denominator */
267 u32 dcqcn_k_us; /* Alpha update interval */
268 u32 dcqcn_timeout_us;
271 struct ecore_rdma_glob_cfg {
272 /* global tunables affecting all QPs created after they are
284 #define ECORE_RDMA_DCSP_BIT_MASK 0x01
285 #define ECORE_RDMA_DCSP_EN_BIT_MASK 0x02
286 #define ECORE_RDMA_ECN_BIT_MASK 0x04
287 #define ECORE_RDMA_ECN_EN_BIT_MASK 0x08
288 #define ECORE_RDMA_VLAN_PRIO_BIT_MASK 0x10
289 #define ECORE_RDMA_VLAN_PRIO_EN_BIT_MASK 0x20
292 ecore_rdma_set_glob_cfg(struct ecore_hwfn *p_hwfn,
293 struct ecore_rdma_glob_cfg *in_params,
297 ecore_rdma_get_glob_cfg(struct ecore_hwfn *p_hwfn,
298 struct ecore_rdma_glob_cfg *out_params);
299 #endif /* LINUX_REMOVE */
301 #ifdef CONFIG_ECORE_IWARP
303 #define ECORE_IWARP_MAX_LIS_BACKLOG (256)
305 #define ECORE_MPA_RTR_TYPE_NONE 0 /* No RTR type */
306 #define ECORE_MPA_RTR_TYPE_ZERO_SEND (1 << 0)
307 #define ECORE_MPA_RTR_TYPE_ZERO_WRITE (1 << 1)
308 #define ECORE_MPA_RTR_TYPE_ZERO_READ (1 << 2)
315 struct ecore_iwarp_params {
318 #define ECORE_IWARP_TS_EN (1 << 0)
319 #define ECORE_IWARP_DA_EN (1 << 1)
322 enum ecore_mpa_rev mpa_rev;
329 struct ecore_roce_params {
330 enum ecore_rdma_cq_mode cq_mode;
331 struct ecore_roce_dcqcn_params dcqcn_params;
332 u8 ll2_handle; /* required for UD QPs */
335 struct ecore_rdma_start_in_params {
336 struct ecore_rdma_events *events;
337 struct ecore_rdma_cnq_params cnq_pbl_list[128];
340 u8 mac_addr[ETH_ALEN];
341 #ifdef CONFIG_ECORE_IWARP
342 struct ecore_iwarp_params iwarp;
344 struct ecore_roce_params roce;
347 struct ecore_rdma_add_user_out_params {
348 /* output variables (given to miniport) */
364 /* ECORE GID can be used as IPv4/6 address in RoCE v2 */
373 struct ecore_rdma_register_tid_in_params {
374 /* input variables (given by miniport) */
375 u32 itid; /* index only, 18 bit long, lkey = itid << 8 | key */
376 enum ecore_rdma_tid_type tid_type;
387 u8 pbl_page_size_log; /* for the pages that contain the pointers
390 u8 page_size_log; /* for the MR pages */
392 u64 length; /* only lower 40 bits are valid */
398 /* DIF related fields */
404 /*Returns the CQ CID or zero in case of failure */
405 struct ecore_rdma_create_cq_in_params {
406 /* input variables (given by miniport) */
407 u32 cq_handle_lo; /* CQ handle to be written in CNQ */
414 u8 pbl_page_size_log; /* for the pages that contain the
415 * pointers to the CQ pages
421 struct ecore_rdma_create_srq_in_params {
428 /* XRC related only */
432 bool reserved_key_en;
435 struct ecore_rdma_destroy_cq_in_params {
436 /* input variables (given by miniport) */
440 struct ecore_rdma_destroy_cq_out_params {
441 /* output variables, provided to the upper layer */
443 /* Sequence number of completion notification sent for the CQ on
450 struct ecore_rdma_resize_cq_in_params {
451 /* input variables (given by miniport) */
458 u8 pbl_page_size_log; /* for the pages that contain the
459 * pointers to the CQ pages
463 #ifndef __EXTRACT__LINUX__
465 struct ecore_rdma_create_qp_in_params {
466 /* input variables (given by miniport) */
467 u32 qp_handle_lo; /* QP handle to be written in CQE */
469 u32 qp_handle_async_lo; /* QP handle to be written in async event */
470 u32 qp_handle_async_hi;
473 bool fmr_and_reserved_lkey;
478 u64 sq_pbl_ptr; /* Not relevant for iWARP */
482 u64 rq_pbl_ptr; /* Not relevant for iWARP */
485 enum ecore_rdma_qp_type qp_type;
489 struct ecore_rdma_create_qp_out_params {
490 /* output variables (given to miniport) */
494 dma_addr_t rq_pbl_phys;
496 dma_addr_t sq_pbl_phys;
499 struct ecore_rdma_modify_qp_in_params {
500 /* input variables (given by miniport) */
502 #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
503 #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
504 #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
505 #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
506 #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
507 #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
508 #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
509 #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
510 #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
511 #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
512 #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
513 #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
514 #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
515 #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
516 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
517 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
518 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
519 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
520 #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
521 #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
522 #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
523 #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
524 #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
525 #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
526 #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
527 #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
528 #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
529 #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
530 #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
531 #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
533 enum ecore_roce_qp_state new_state;
535 bool incoming_rdma_read_en;
536 bool incoming_rdma_write_en;
537 bool incoming_atomic_en;
538 bool e2e_flow_control_en;
541 u8 traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
542 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
543 u32 flow_label; /* ignored in IPv4 */
544 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
545 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
546 u16 udp_src_port; /* RoCEv2 only */
552 u8 max_rd_atomic_resp;
553 u8 max_rd_atomic_req;
557 u8 min_rnr_nak_timer;
559 u8 remote_mac_addr[6];
560 u8 local_mac_addr[6];
562 enum roce_mode roce_mode;
565 struct ecore_rdma_query_qp_out_params {
566 /* output variables (given to miniport) */
567 enum ecore_roce_qp_state state;
568 u32 rq_psn; /* responder */
569 u32 sq_psn; /* requester */
570 bool draining; /* send queue is draining */
573 bool incoming_rdma_read_en;
574 bool incoming_rdma_write_en;
575 bool incoming_atomic_en;
576 bool e2e_flow_control_en;
577 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
578 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
579 u32 flow_label; /* ignored in IPv4 */
580 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
581 u8 traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
585 u8 min_rnr_nak_timer;
588 u8 max_dest_rd_atomic;
592 struct ecore_rdma_destroy_qp_out_params {
597 struct ecore_rdma_create_srq_out_params {
601 struct ecore_rdma_destroy_srq_in_params {
606 struct ecore_rdma_modify_srq_in_params {
613 struct ecore_rdma_resize_cq_out_params {
614 /* output variables, provided to the upper layer */
615 u32 prod; /* CQ producer value on old PBL */
616 u32 cons; /* CQ consumer value on old PBL */
619 struct ecore_rdma_resize_cnq_in_params {
620 /* input variables (given by miniport) */
622 u32 pbl_page_size_log; /* for the pages that contain the
623 * pointers to the cnq pages
628 #ifndef __EXTRACT__LINUX__
629 struct ecore_rdma_stats_out_params {
636 u64 icrc_errors; /* wraps at 32 bits */
637 u64 retransmit_events; /* wraps at 32 bits */
638 u64 silent_drops; /* wraps at 16 bits */
639 u64 rnr_nacks_sent; /* wraps at 16 bits */
647 u64 iwarp_tx_fast_rxmit_cnt;
648 u64 iwarp_tx_slow_start_cnt;
652 struct ecore_rdma_counters_out_params {
673 ecore_rdma_add_user(void *rdma_cxt,
674 struct ecore_rdma_add_user_out_params *out_params);
677 ecore_rdma_alloc_pd(void *rdma_cxt,
681 ecore_rdma_alloc_tid(void *rdma_cxt,
685 ecore_rdma_create_cq(void *rdma_cxt,
686 struct ecore_rdma_create_cq_in_params *params,
689 /* Returns a pointer to the responders' CID, which is also a pointer to the
690 * ecore_qp_params struct. Returns NULL in case of failure.
692 struct ecore_rdma_qp*
693 ecore_rdma_create_qp(void *rdma_cxt,
694 struct ecore_rdma_create_qp_in_params *in_params,
695 struct ecore_rdma_create_qp_out_params *out_params);
698 ecore_roce_create_ud_qp(void *rdma_cxt,
699 struct ecore_rdma_create_qp_out_params *out_params);
702 ecore_rdma_deregister_tid(void *rdma_cxt,
706 ecore_rdma_destroy_cq(void *rdma_cxt,
707 struct ecore_rdma_destroy_cq_in_params *in_params,
708 struct ecore_rdma_destroy_cq_out_params *out_params);
711 ecore_rdma_destroy_qp(void *rdma_cxt,
712 struct ecore_rdma_qp *qp,
713 struct ecore_rdma_destroy_qp_out_params *out_params);
716 ecore_roce_destroy_ud_qp(void *rdma_cxt, u16 cid);
719 ecore_rdma_free_pd(void *rdma_cxt,
723 ecore_rdma_alloc_xrcd(void *rdma_cxt, u16 *xrcd_id);
726 ecore_rdma_free_xrcd(void *rdma_cxt, u16 xrcd_id);
729 ecore_rdma_free_tid(void *rdma_cxt,
733 ecore_rdma_modify_qp(void *rdma_cxt,
734 struct ecore_rdma_qp *qp,
735 struct ecore_rdma_modify_qp_in_params *params);
737 struct ecore_rdma_device*
738 ecore_rdma_query_device(void *rdma_cxt);
740 struct ecore_rdma_port*
741 ecore_rdma_query_port(void *rdma_cxt);
744 ecore_rdma_query_qp(void *rdma_cxt,
745 struct ecore_rdma_qp *qp,
746 struct ecore_rdma_query_qp_out_params *out_params);
749 ecore_rdma_register_tid(void *rdma_cxt,
750 struct ecore_rdma_register_tid_in_params *params);
752 void ecore_rdma_remove_user(void *rdma_cxt,
756 ecore_rdma_resize_cnq(void *rdma_cxt,
757 struct ecore_rdma_resize_cnq_in_params *in_params);
759 /*Returns the CQ CID or zero in case of failure */
761 ecore_rdma_resize_cq(void *rdma_cxt,
762 struct ecore_rdma_resize_cq_in_params *in_params,
763 struct ecore_rdma_resize_cq_out_params *out_params);
765 /* Before calling rdma_start upper layer (VBD/qed) should fill the
766 * page-size and mtu in hwfn context
769 ecore_rdma_start(void *p_hwfn,
770 struct ecore_rdma_start_in_params *params);
773 ecore_rdma_stop(void *rdma_cxt);
776 ecore_rdma_query_stats(void *rdma_cxt, u8 stats_queue,
777 struct ecore_rdma_stats_out_params *out_parms);
780 ecore_rdma_query_counters(void *rdma_cxt,
781 struct ecore_rdma_counters_out_params *out_parms);
783 u32 ecore_rdma_get_sb_id(struct ecore_hwfn *p_hwfn, u32 rel_sb_id);
786 u32 ecore_rdma_query_cau_timer_res(void);
789 void ecore_rdma_cnq_prod_update(void *rdma_cxt, u8 cnq_index, u16 prod);
791 void ecore_rdma_resc_free(struct ecore_hwfn *p_hwfn);
794 ecore_rdma_create_srq(void *rdma_cxt,
795 struct ecore_rdma_create_srq_in_params *in_params,
796 struct ecore_rdma_create_srq_out_params *out_params);
799 ecore_rdma_destroy_srq(void *rdma_cxt,
800 struct ecore_rdma_destroy_srq_in_params *in_params);
803 ecore_rdma_modify_srq(void *rdma_cxt,
804 struct ecore_rdma_modify_srq_in_params *in_params);
806 #ifdef CONFIG_ECORE_IWARP
810 #ifndef __EXTRACT__LINUX__
812 enum ecore_iwarp_event_type {
813 ECORE_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */
814 ECORE_IWARP_EVENT_PASSIVE_COMPLETE, /* Passive side established
815 * ( ack on mpa response )
817 ECORE_IWARP_EVENT_LISTEN_PAUSE_COMP, /* Passive side will drop
820 ECORE_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */
821 ECORE_IWARP_EVENT_DISCONNECT,
822 ECORE_IWARP_EVENT_CLOSE,
823 /* Slow/Error path events start from here */
824 ECORE_IWARP_EVENT_IRQ_FULL,
825 ECORE_IWARP_ERROR_EVENTS_START = ECORE_IWARP_EVENT_IRQ_FULL,
826 ECORE_IWARP_EVENT_RQ_EMPTY,
827 ECORE_IWARP_EVENT_LLP_TIMEOUT,
828 ECORE_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
829 ECORE_IWARP_EVENT_CQ_OVERFLOW,
830 ECORE_IWARP_EVENT_QP_CATASTROPHIC,
831 ECORE_IWARP_EVENT_ACTIVE_MPA_REPLY,
832 ECORE_IWARP_EVENT_LOCAL_ACCESS_ERROR,
833 ECORE_IWARP_EVENT_REMOTE_OPERATION_ERROR,
834 ECORE_IWARP_EVENT_TERMINATE_RECEIVED
837 enum ecore_tcp_ip_version
843 struct ecore_iwarp_cm_info {
844 enum ecore_tcp_ip_version ip_version;
850 const void *private_data;
851 u16 private_data_len;
856 struct ecore_iwarp_cm_event_params {
857 enum ecore_iwarp_event_type event;
858 const struct ecore_iwarp_cm_info *cm_info;
859 void *ep_context; /* To be passed to accept call */
863 typedef int (*iwarp_event_handler)(void *context,
864 struct ecore_iwarp_cm_event_params *event);
866 /* Active Side Connect Flow:
867 * upper layer driver calls ecore_iwarp_connect
868 * Function is blocking: i.e. returns after tcp connection is established
869 * After MPA connection is established ECORE_IWARP_EVENT_ACTIVE_COMPLETE event
870 * will be passed to upperlayer driver using the event_cb passed in
871 * ecore_iwarp_connect_in. Information of the established connection will be
872 * initialized in event data.
874 struct ecore_iwarp_connect_in {
875 iwarp_event_handler event_cb;
877 struct ecore_rdma_qp *qp;
878 struct ecore_iwarp_cm_info cm_info;
880 u8 remote_mac_addr[6];
881 u8 local_mac_addr[6];
884 struct ecore_iwarp_connect_out {
888 /* Passive side connect flow:
889 * upper layer driver calls ecore_iwarp_create_listen
890 * once Syn packet that matches a ip/port that is listened on arrives, ecore
891 * will offload the tcp connection. After MPA Request is received on the
892 * offload connection, the event ECORE_IWARP_EVENT_MPA_REQUEST will be sent
893 * to upper layer driver using the event_cb passed below. The event data
894 * will be placed in event parameter. After upper layer driver processes the
895 * event, ecore_iwarp_accept or ecore_iwarp_reject should be called to continue
896 * MPA negotiation. Once negotiation is complete the event
897 * ECORE_IWARP_EVENT_PASSIVE_COMPLETE will be passed to the event_cb passed
898 * originally in ecore_iwarp_listen_in structure.
900 struct ecore_iwarp_listen_in {
901 iwarp_event_handler event_cb; /* Callback func for delivering events */
902 void *cb_context; /* passed to event_cb */
903 u32 max_backlog; /* Max num of pending incoming connection requests */
904 enum ecore_tcp_ip_version ip_version;
910 struct ecore_iwarp_listen_out {
911 void *handle; /* to be sent to destroy */
914 struct ecore_iwarp_accept_in {
915 void *ep_context; /* From event data of ECORE_IWARP_EVENT_MPA_REQUEST */
916 void *cb_context; /* context to be passed to event_cb */
917 struct ecore_rdma_qp *qp;
918 const void *private_data;
919 u16 private_data_len;
924 struct ecore_iwarp_reject_in {
925 void *ep_context; /* From event data of ECORE_IWARP_EVENT_MPA_REQUEST */
926 void *cb_context; /* context to be passed to event_cb */
927 const void *private_data;
928 u16 private_data_len;
931 struct ecore_iwarp_send_rtr_in {
935 struct ecore_iwarp_tcp_abort_in {
942 ecore_iwarp_connect(void *rdma_cxt,
943 struct ecore_iwarp_connect_in *iparams,
944 struct ecore_iwarp_connect_out *oparams);
947 ecore_iwarp_create_listen(void *rdma_cxt,
948 struct ecore_iwarp_listen_in *iparams,
949 struct ecore_iwarp_listen_out *oparams);
952 ecore_iwarp_accept(void *rdma_cxt,
953 struct ecore_iwarp_accept_in *iparams);
956 ecore_iwarp_reject(void *rdma_cxt,
957 struct ecore_iwarp_reject_in *iparams);
960 ecore_iwarp_destroy_listen(void *rdma_cxt, void *handle);
963 ecore_iwarp_send_rtr(void *rdma_cxt, struct ecore_iwarp_send_rtr_in *iparams);
966 ecore_iwarp_pause_listen(void *rdma_cxt, void *handle, bool pause, bool comp);
968 #endif /* CONFIG_ECORE_IWARP */