2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __ECORE_RDMA_H__
32 #define __ECORE_RDMA_H__
34 #include "ecore_status.h"
36 #include "ecore_hsi_common.h"
37 #include "ecore_proto_if.h"
38 #include "ecore_roce_api.h"
39 #include "ecore_dev_api.h"
43 /* HW/FW RoCE Limitations (internal. For external see ecore_rdma_api.h) */
44 #define ECORE_RDMA_MAX_FMR (RDMA_MAX_TIDS) /* 2^17 - 1 */
45 #define ECORE_RDMA_MAX_P_KEY (1)
46 #define ECORE_RDMA_MAX_WQE (0x7FFF) /* 2^15 -1 */
47 #define ECORE_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF) /* 2^15 -1 */
48 #define ECORE_RDMA_PAGE_SIZE_CAPS (0xFFFFF000) /* TODO: > 4k?! */
49 #define ECORE_RDMA_ACK_DELAY (15) /* 131 milliseconds */
50 #define ECORE_RDMA_MAX_MR_SIZE (0x10000000000ULL) /* 2^40 */
51 #define ECORE_RDMA_MAX_CQS (RDMA_MAX_CQS) /* 64k */
52 #define ECORE_RDMA_MAX_MRS (RDMA_MAX_TIDS) /* 2^17 - 1 */
53 /* Add 1 for header element */
54 #define ECORE_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
55 #define ECORE_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
56 #define ECORE_RDMA_SRQ_WQE_ELEM_SIZE (16)
57 #define ECORE_RDMA_MAX_SRQS (32 * 1024) /* 32k */
60 /* Max CQE is derived from u16/32 size, halved and decremented by 1 to handle
61 * wrap properly and then decremented by 1 again. The latter decrement comes
62 * from a requirement to create a chain that is bigger than what the user
64 * The CQE size is 32 bytes but the FW writes in chunks of 64
65 * bytes, for performance purposes. Allocating an extra entry and telling the
66 * FW we have less prevents overwriting the first entry in case of a wrap i.e.
67 * when the FW writes the last entry and the application hasn't read the first
70 #define ECORE_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
71 #define ECORE_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
73 enum ecore_rdma_toggle_bit {
74 ECORE_RDMA_TOGGLE_BIT_CLEAR = 0,
75 ECORE_RDMA_TOGGLE_BIT_SET = 1
78 /* @@@TBD Currently we support only affilited events
79 * enum ecore_rdma_unaffiliated_event_code {
80 * ECORE_RDMA_PORT_ACTIVE, // Link Up
81 * ECORE_RDMA_PORT_CHANGED, // SGID table has changed
82 * ECORE_RDMA_LOCAL_CATASTROPHIC_ERR, // Fatal device error
83 * ECORE_RDMA_PORT_ERR, // Link down
87 #define QEDR_MAX_BMAP_NAME (10)
90 unsigned long *bitmap;
91 char name[QEDR_MAX_BMAP_NAME];
94 /* functions for enabling/disabling edpm in rdma PFs according to existence of
95 * qps during DCBx update or bar size
97 void ecore_roce_dpm_dcbx(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
98 void ecore_rdma_dpm_bar(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
100 #ifdef CONFIG_ECORE_IWARP
102 #define ECORE_IWARP_PREALLOC_CNT (256)
104 #define ECORE_IWARP_LL2_SYN_TX_SIZE (128)
105 #define ECORE_IWARP_LL2_SYN_RX_SIZE (256)
107 #define ECORE_IWARP_LL2_OOO_DEF_TX_SIZE (256)
108 #define ECORE_IWARP_LL2_OOO_DEF_RX_SIZE (4096)
109 #define ECORE_IWARP_LL2_OOO_MAX_RX_SIZE (16384)
111 #define ECORE_IWARP_MAX_SYN_PKT_SIZE (128)
112 #define ECORE_IWARP_HANDLE_INVAL (0xff)
114 struct ecore_iwarp_ll2_buff {
115 struct ecore_iwarp_ll2_buff *piggy_buf;
117 dma_addr_t data_phys_addr;
121 struct ecore_iwarp_ll2_mpa_buf {
122 osal_list_entry_t list_entry;
123 struct ecore_iwarp_ll2_buff *ll2_buf;
124 struct unaligned_opaque_data data;
129 /* In some cases a fpdu will arrive with only one byte of the header, in this
130 * case the fpdu_length will be partial ( contain only higher byte and
131 * incomplete bytes will contain the invalid value */
132 #define ECORE_IWARP_INVALID_INCOMPLETE_BYTES 0xffff
134 struct ecore_iwarp_fpdu {
135 struct ecore_iwarp_ll2_buff *mpa_buf;
142 u16 incomplete_bytes;
145 struct ecore_iwarp_info {
146 osal_list_t listen_list; /* ecore_iwarp_listener */
147 osal_list_t ep_list; /* ecore_iwarp_ep */
148 osal_list_t ep_free_list;/* pre-allocated ep's */
149 osal_list_t mpa_buf_list;/* list of mpa_bufs */
150 osal_list_t mpa_buf_pending_list;
151 osal_spinlock_t iw_lock;
152 osal_spinlock_t qp_lock; /* for teardown races */
153 struct iwarp_rxmit_stats_drv stats;
157 u8 mac_addr[ETH_ALEN];
165 enum mpa_negotiation_mode mpa_rev;
166 enum mpa_rtr_type rtr_type;
167 struct ecore_iwarp_fpdu *partial_fpdus;
168 struct ecore_iwarp_ll2_mpa_buf *mpa_bufs;
169 u8 *mpa_intermediate_buf;
170 u16 max_num_partial_fpdus;
177 #define IS_ECORE_DCQCN(p_hwfn) \
178 (!!(p_hwfn->pf_params.rdma_pf_params.enable_dcqcn))
180 struct ecore_roce_info {
181 struct roce_events_stats event_stats;
184 u8 dcqcn_reaction_point;
187 struct ecore_rdma_info {
188 osal_spinlock_t lock;
190 struct ecore_bmap cq_map;
191 struct ecore_bmap pd_map;
192 struct ecore_bmap tid_map;
193 struct ecore_bmap srq_map;
194 struct ecore_bmap cid_map;
195 struct ecore_bmap tcp_cid_map;
196 struct ecore_bmap real_cid_map;
197 struct ecore_bmap dpi_map;
198 struct ecore_bmap toggle_bits;
199 struct ecore_rdma_events events;
200 struct ecore_rdma_device *dev;
201 struct ecore_rdma_port *port;
204 struct rdma_sent_stats rdma_sent_pstats;
205 struct rdma_rcv_stats rdma_rcv_tstats;
211 enum protocol_type proto;
212 struct ecore_roce_info roce;
213 #ifdef CONFIG_ECORE_IWARP
214 struct ecore_iwarp_info iwarp;
218 #ifdef CONFIG_ECORE_IWARP
219 enum ecore_iwarp_qp_state {
220 ECORE_IWARP_QP_STATE_IDLE,
221 ECORE_IWARP_QP_STATE_RTS,
222 ECORE_IWARP_QP_STATE_TERMINATE,
223 ECORE_IWARP_QP_STATE_CLOSING,
224 ECORE_IWARP_QP_STATE_ERROR,
228 struct ecore_rdma_qp {
229 struct regpair qp_handle;
230 struct regpair qp_handle_async;
231 u32 qpid; /* iwarp: may differ from icid */
233 enum ecore_roce_qp_state cur_state;
234 #ifdef CONFIG_ECORE_IWARP
235 enum ecore_iwarp_qp_state iwarp_state;
239 bool fmr_and_reserved_lkey;
241 bool incoming_rdma_read_en;
242 bool incoming_rdma_write_en;
243 bool incoming_atomic_en;
244 bool e2e_flow_control_en;
246 u16 pd; /* Protection domain */
247 u16 pkey; /* Primary P_key index */
251 u8 traffic_class_tos; /* IPv6/GRH traffic class; IPv4 TOS */
252 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
254 u32 flow_label; /* ignored in IPv4 */
259 u8 min_rnr_nak_timer;
261 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
262 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
263 enum roce_mode roce_mode;
264 u16 udp_src_port; /* RoCEv2 only */
268 u8 max_rd_atomic_req;
270 u16 sq_cq_id; /* The cq to be associated with the send queue*/
272 dma_addr_t sq_pbl_ptr;
274 dma_addr_t orq_phys_addr;
279 u8 max_rd_atomic_resp;
281 u16 rq_cq_id; /* The cq to be associated with the receive queue */
283 dma_addr_t rq_pbl_ptr;
285 dma_addr_t irq_phys_addr;
290 u8 remote_mac_addr[6];
291 u8 local_mac_addr[6];
294 dma_addr_t shared_queue_phys_addr;
295 #ifdef CONFIG_ECORE_IWARP
296 struct ecore_iwarp_ep *ep;
300 #ifdef CONFIG_ECORE_IWARP
302 enum ecore_iwarp_ep_state {
304 ECORE_IWARP_EP_MPA_REQ_RCVD,
305 ECORE_IWARP_EP_ESTABLISHED,
306 ECORE_IWARP_EP_CLOSED
310 struct iwarp_eqe_data_mpa_async_completion mpa_response;
311 struct iwarp_eqe_data_tcp_async_completion mpa_request;
314 #define ECORE_MAX_PRIV_DATA_LEN (512)
315 struct ecore_iwarp_ep_memory {
316 u8 in_pdata[ECORE_MAX_PRIV_DATA_LEN];
317 u8 out_pdata[ECORE_MAX_PRIV_DATA_LEN];
318 union async_output async_output;
321 /* Endpoint structure represents a TCP connection. This connection can be
322 * associated with a QP or not (in which case QP==NULL)
324 struct ecore_iwarp_ep {
325 osal_list_entry_t list_entry;
327 struct ecore_rdma_qp *qp;
328 enum ecore_iwarp_ep_state state;
330 /* This contains entire buffer required for ep memories. This is the
331 * only one actually allocated and freed. The rest are pointers into
334 struct ecore_iwarp_ep_memory *ep_buffer_virt;
335 dma_addr_t ep_buffer_phys;
337 struct ecore_iwarp_cm_info cm_info;
338 enum tcp_connect_mode connect_mode;
339 enum mpa_rtr_type rtr_type;
340 enum mpa_negotiation_mode mpa_rev;
343 u8 remote_mac_addr[6];
344 u8 local_mac_addr[6];
346 bool mpa_reply_processed;
348 /* The event_cb function is called for asynchrounous events associated
349 * with the ep. It is initialized at different entry points depending
350 * on whether the ep is the tcp connection active side or passive side
351 * The cb_context is passed to the event_cb function.
353 iwarp_event_handler event_cb;
356 /* For Passive side - syn packet related data */
357 struct ecore_iwarp_ll2_buff *syn;
358 u16 syn_ip_payload_length;
359 dma_addr_t syn_phy_addr;
362 struct ecore_iwarp_listener {
363 osal_list_entry_t list_entry;
365 /* The event_cb function is called for connection requests.
366 * The cb_context is passed to the event_cb function.
368 iwarp_event_handler event_cb;
378 void ecore_iwarp_async_event(struct ecore_hwfn *p_hwfn,
380 struct regpair *fw_handle,
383 #endif /* CONFIG_ECORE_IWARP */
385 void ecore_roce_async_event(struct ecore_hwfn *p_hwfn,
387 union rdma_eqe_data *rdma_data);
389 #endif /*__ECORE_RDMA_H__*/