2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
29 * File : ecore_sp_commands.c
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #include "ecore_status.h"
39 #include "ecore_chain.h"
40 #include "ecore_spq.h"
41 #include "ecore_init_fw_funcs.h"
42 #include "ecore_cxt.h"
43 #include "ecore_sp_commands.h"
44 #include "ecore_gtt_reg_addr.h"
45 #include "ecore_iro.h"
47 #include "ecore_int.h"
49 #include "ecore_dcbx.h"
50 #include "ecore_sriov.h"
53 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
54 struct ecore_spq_entry **pp_ent,
57 struct ecore_sp_init_data *p_data)
59 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
60 struct ecore_spq_entry *p_ent = OSAL_NULL;
61 enum _ecore_status_t rc;
66 /* Get an SPQ entry */
67 rc = ecore_spq_get_entry(p_hwfn, pp_ent);
68 if (rc != ECORE_SUCCESS)
71 /* Fill the SPQ entry */
73 p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
74 p_ent->elem.hdr.cmd_id = cmd;
75 p_ent->elem.hdr.protocol_id = protocol;
76 p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
77 p_ent->comp_mode = p_data->comp_mode;
78 p_ent->comp_done.done = 0;
80 switch (p_ent->comp_mode) {
81 case ECORE_SPQ_MODE_EBLOCK:
82 p_ent->comp_cb.cookie = &p_ent->comp_done;
85 case ECORE_SPQ_MODE_BLOCK:
86 if (!p_data->p_comp_data)
89 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
92 case ECORE_SPQ_MODE_CB:
93 if (!p_data->p_comp_data)
94 p_ent->comp_cb.function = OSAL_NULL;
96 p_ent->comp_cb = *p_data->p_comp_data;
100 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
105 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
106 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
107 opaque_cid, cmd, protocol,
108 (unsigned long)&p_ent->ramrod,
109 D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
110 ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
113 OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
115 return ECORE_SUCCESS;
118 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
121 case ECORE_TUNN_CLSS_MAC_VLAN:
122 return TUNNEL_CLSS_MAC_VLAN;
123 case ECORE_TUNN_CLSS_MAC_VNI:
124 return TUNNEL_CLSS_MAC_VNI;
125 case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
126 return TUNNEL_CLSS_INNER_MAC_VLAN;
127 case ECORE_TUNN_CLSS_INNER_MAC_VNI:
128 return TUNNEL_CLSS_INNER_MAC_VNI;
129 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
130 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
132 return TUNNEL_CLSS_MAC_VLAN;
137 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
138 struct ecore_tunnel_info *p_src,
141 if (p_src->vxlan.b_update_mode || b_pf_start)
142 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
144 if (p_src->l2_gre.b_update_mode || b_pf_start)
145 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
147 if (p_src->ip_gre.b_update_mode || b_pf_start)
148 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
150 if (p_src->l2_geneve.b_update_mode || b_pf_start)
151 p_tun->l2_geneve.b_mode_enabled =
152 p_src->l2_geneve.b_mode_enabled;
154 if (p_src->ip_geneve.b_update_mode || b_pf_start)
155 p_tun->ip_geneve.b_mode_enabled =
156 p_src->ip_geneve.b_mode_enabled;
159 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
160 struct ecore_tunnel_info *p_src)
162 enum tunnel_clss type;
164 p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
165 p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
167 type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
168 p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
169 type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
170 p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
171 type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
172 p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
173 type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
174 p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
175 type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
176 p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
179 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
180 struct ecore_tunnel_info *p_src)
182 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
183 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
185 if (p_src->geneve_port.b_update_port)
186 p_tun->geneve_port.port = p_src->geneve_port.port;
188 if (p_src->vxlan_port.b_update_port)
189 p_tun->vxlan_port.port = p_src->vxlan_port.port;
193 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
194 struct ecore_tunn_update_type *tun_type)
196 *p_tunn_cls = tun_type->tun_cls;
200 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
201 struct ecore_tunn_update_type *tun_type,
202 u8 *p_update_port, __le16 *p_port,
203 struct ecore_tunn_update_udp_port *p_udp_port)
205 __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
206 if (p_udp_port->b_update_port) {
208 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
213 ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,
214 struct ecore_tunnel_info *p_src,
215 struct pf_update_tunnel_config *p_tunn_cfg)
217 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
219 ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
220 ecore_set_tunn_cls_info(p_tun, p_src);
221 ecore_set_tunn_ports(p_tun, p_src);
223 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
225 &p_tunn_cfg->set_vxlan_udp_port_flg,
226 &p_tunn_cfg->vxlan_udp_port,
229 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
231 &p_tunn_cfg->set_geneve_udp_port_flg,
232 &p_tunn_cfg->geneve_udp_port,
233 &p_tun->geneve_port);
235 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
238 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
241 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
244 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
247 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
248 struct ecore_ptt *p_ptt,
249 struct ecore_tunnel_info *p_tun)
251 ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
252 p_tun->ip_gre.b_mode_enabled);
253 ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
255 ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
256 p_tun->ip_geneve.b_mode_enabled);
259 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
260 struct ecore_tunnel_info *p_tunn)
262 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
263 DP_NOTICE(p_hwfn, true,
264 "A0 chip: tunnel hw config is not supported\n");
268 if (p_tunn->vxlan_port.b_update_port)
269 ecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
270 p_tunn->vxlan_port.port);
272 if (p_tunn->geneve_port.b_update_port)
273 ecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
274 p_tunn->geneve_port.port);
276 ecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn);
280 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
281 struct ecore_tunnel_info *p_src,
282 struct pf_start_tunnel_config *p_tunn_cfg)
284 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
286 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
287 DP_NOTICE(p_hwfn, true,
288 "A0 chip: tunnel pf start config is not supported\n");
295 ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
296 ecore_set_tunn_cls_info(p_tun, p_src);
297 ecore_set_tunn_ports(p_tun, p_src);
299 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
301 &p_tunn_cfg->set_vxlan_udp_port_flg,
302 &p_tunn_cfg->vxlan_udp_port,
305 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
307 &p_tunn_cfg->set_geneve_udp_port_flg,
308 &p_tunn_cfg->geneve_udp_port,
309 &p_tun->geneve_port);
311 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
314 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
317 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
321 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
322 struct ecore_tunnel_info *p_tunn,
323 enum ecore_mf_mode mode,
324 bool allow_npar_tx_switch)
326 struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
327 u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
328 u8 sb_index = p_hwfn->p_eq->eq_sb_index;
329 struct ecore_spq_entry *p_ent = OSAL_NULL;
330 struct ecore_sp_init_data init_data;
331 enum _ecore_status_t rc = ECORE_NOTIMPL;
334 /* update initial eq producer */
335 ecore_eq_prod_update(p_hwfn,
336 ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
338 /* Initialize the SPQ entry for the ramrod */
339 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
340 init_data.cid = ecore_spq_get_cid(p_hwfn);
341 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
342 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
344 rc = ecore_sp_init_request(p_hwfn, &p_ent,
345 COMMON_RAMROD_PF_START,
348 if (rc != ECORE_SUCCESS)
351 /* Fill the ramrod data */
352 p_ramrod = &p_ent->ramrod.pf_start;
353 p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
354 p_ramrod->event_ring_sb_index = sb_index;
355 p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
357 /* For easier debugging */
358 p_ramrod->dont_log_ramrods = 0;
359 p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
362 case ECORE_MF_DEFAULT:
364 p_ramrod->mf_mode = MF_NPAR;
367 p_ramrod->mf_mode = MF_OVLAN;
370 DP_NOTICE(p_hwfn, true, "Unsupported MF mode, init as DEFAULT\n");
371 p_ramrod->mf_mode = MF_NPAR;
373 p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
375 /* Place EQ address in RAMROD */
376 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
377 p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
378 page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
379 p_ramrod->event_ring_num_pages = page_cnt;
380 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
381 p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
383 ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
384 &p_ramrod->tunnel_config);
386 if (IS_MF_SI(p_hwfn))
387 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
389 switch (p_hwfn->hw_info.personality) {
391 p_ramrod->personality = PERSONALITY_ETH;
394 p_ramrod->personality = PERSONALITY_FCOE;
396 case ECORE_PCI_ISCSI:
397 p_ramrod->personality = PERSONALITY_ISCSI;
399 case ECORE_PCI_ETH_IWARP:
400 case ECORE_PCI_ETH_ROCE:
401 case ECORE_PCI_ETH_RDMA:
402 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
405 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
406 p_hwfn->hw_info.personality);
407 p_ramrod->personality = PERSONALITY_ETH;
410 if (p_hwfn->p_dev->p_iov_info) {
411 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
413 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
414 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
416 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
417 * version is available.
419 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
420 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
422 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
423 "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
424 sb, sb_index, p_ramrod->outer_tag);
426 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
429 ecore_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->p_dev->tunnel);
434 enum _ecore_status_t ecore_sp_pf_update(struct ecore_hwfn *p_hwfn)
436 struct ecore_spq_entry *p_ent = OSAL_NULL;
437 struct ecore_sp_init_data init_data;
438 enum _ecore_status_t rc = ECORE_NOTIMPL;
441 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
442 init_data.cid = ecore_spq_get_cid(p_hwfn);
443 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
444 init_data.comp_mode = ECORE_SPQ_MODE_CB;
446 rc = ecore_sp_init_request(p_hwfn, &p_ent,
447 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
449 if (rc != ECORE_SUCCESS)
452 ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
453 &p_ent->ramrod.pf_update);
455 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
458 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
459 struct ecore_rl_update_params *params)
461 struct ecore_spq_entry *p_ent = OSAL_NULL;
462 enum _ecore_status_t rc = ECORE_NOTIMPL;
463 struct rl_update_ramrod_data *rl_update;
464 struct ecore_sp_init_data init_data;
467 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
468 init_data.cid = ecore_spq_get_cid(p_hwfn);
469 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
470 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
472 rc = ecore_sp_init_request(p_hwfn, &p_ent,
473 COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
475 if (rc != ECORE_SUCCESS)
478 rl_update = &p_ent->ramrod.rl_update;
480 rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
481 rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
482 rl_update->rl_init_flg = params->rl_init_flg;
483 rl_update->rl_start_flg = params->rl_start_flg;
484 rl_update->rl_stop_flg = params->rl_stop_flg;
485 rl_update->rl_id_first = params->rl_id_first;
486 rl_update->rl_id_last = params->rl_id_last;
487 rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
488 rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
489 rl_update->rl_max_rate = OSAL_CPU_TO_LE16(params->rl_max_rate);
490 rl_update->rl_r_ai = OSAL_CPU_TO_LE16(params->rl_r_ai);
491 rl_update->rl_r_hai = OSAL_CPU_TO_LE16(params->rl_r_hai);
492 rl_update->dcqcn_g = OSAL_CPU_TO_LE16(params->dcqcn_g);
493 rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
494 rl_update->dcqcn_timeuot_us = OSAL_CPU_TO_LE32(
495 params->dcqcn_timeuot_us);
496 rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
498 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
501 /* Set pf update ramrod command params */
503 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
504 struct ecore_tunnel_info *p_tunn,
505 enum spq_mode comp_mode,
506 struct ecore_spq_comp_cb *p_comp_data)
508 struct ecore_spq_entry *p_ent = OSAL_NULL;
509 struct ecore_sp_init_data init_data;
510 enum _ecore_status_t rc = ECORE_NOTIMPL;
512 if (IS_VF(p_hwfn->p_dev))
513 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
515 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
516 DP_NOTICE(p_hwfn, true,
517 "A0 chip: tunnel pf update config is not supported\n");
525 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
526 init_data.cid = ecore_spq_get_cid(p_hwfn);
527 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
528 init_data.comp_mode = comp_mode;
529 init_data.p_comp_data = p_comp_data;
531 rc = ecore_sp_init_request(p_hwfn, &p_ent,
532 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
534 if (rc != ECORE_SUCCESS)
537 ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
538 &p_ent->ramrod.pf_update.tunnel_config);
540 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
541 if (rc != ECORE_SUCCESS)
544 ecore_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->p_dev->tunnel);
549 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
551 struct ecore_spq_entry *p_ent = OSAL_NULL;
552 struct ecore_sp_init_data init_data;
553 enum _ecore_status_t rc = ECORE_NOTIMPL;
556 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
557 init_data.cid = ecore_spq_get_cid(p_hwfn);
558 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
559 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
561 rc = ecore_sp_init_request(p_hwfn, &p_ent,
562 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
564 if (rc != ECORE_SUCCESS)
567 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
570 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
572 struct ecore_spq_entry *p_ent = OSAL_NULL;
573 struct ecore_sp_init_data init_data;
574 enum _ecore_status_t rc;
577 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
578 init_data.cid = ecore_spq_get_cid(p_hwfn);
579 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
580 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
582 rc = ecore_sp_init_request(p_hwfn, &p_ent,
583 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
585 if (rc != ECORE_SUCCESS)
588 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);