sys/dev/qlnx/qlnxe/mcp_public.h

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  *
  29  */
  30
  31 /****************************************************************************
  32  *
  33  * Name:        mcp_public.h
  34  *
  35  * Description: MCP public data
  36  *
  37  * Created:     13/01/2013 yanivr
  38  *
  39  ****************************************************************************/
  40
  41 #ifndef MCP_PUBLIC_H
  42 #define MCP_PUBLIC_H
  43
  44 #define VF_MAX_STATIC 192       /* In case of AH */
  45
  46 #define MCP_GLOB_PATH_MAX       2
  47 #define MCP_PORT_MAX            2       /* Global */
  48 #define MCP_GLOB_PORT_MAX       4       /* Global */
  49 #define MCP_GLOB_FUNC_MAX       16      /* Global */
  50
  51 typedef u32 offsize_t;      /* In DWORDS !!! */
  52 /* Offset from the beginning of the MCP scratchpad */
  53 #define OFFSIZE_OFFSET_OFFSET   0
  54 #define OFFSIZE_OFFSET_MASK     0x0000ffff
  55 /* Size of specific element (not the whole array if any) */
  56 #define OFFSIZE_SIZE_OFFSET     16
  57 #define OFFSIZE_SIZE_MASK       0xffff0000
  58
  59 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
  60 #define SECTION_OFFSET(_offsize)        ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2))
  61
  62 /* SECTION_SIZE is calculating the size in bytes out of offsize */
  63 #define SECTION_SIZE(_offsize)          (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2)
  64
  65 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */
  66 #define SECTION_ADDR(_offsize, idx)     (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
  67
  68 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */
  69 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
  70 /* PHY configuration */
  71 struct eth_phy_cfg {
  72         u32 speed;      /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
  73 #define ETH_SPEED_AUTONEG   0
  74 #define ETH_SPEED_SMARTLINQ  0x8 /* deprecated - use link_modes field instead */
  75
  76         u32 pause;      /* bitmask */
  77 #define ETH_PAUSE_NONE          0x0
  78 #define ETH_PAUSE_AUTONEG       0x1
  79 #define ETH_PAUSE_RX            0x2
  80 #define ETH_PAUSE_TX            0x4
  81
  82         u32 adv_speed;      /* Default should be the speed_cap_mask */
  83         u32 loopback_mode;
  84 #define ETH_LOOPBACK_NONE                (0)
  85 #define ETH_LOOPBACK_INT_PHY             (1) /* Serdes loopback. In AH, it refers to Near End */
  86 #define ETH_LOOPBACK_EXT_PHY             (2) /* External PHY Loopback */
  87 #define ETH_LOOPBACK_EXT                 (3) /* External Loopback (Require loopback plug) */
  88 #define ETH_LOOPBACK_MAC                 (4) /* MAC Loopback - not supported */
  89 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123   (5) /* Port to itself */
  90 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301   (6) /* Port to Port */
  91 #define ETH_LOOPBACK_PCS_AH_ONLY         (7) /* PCS loopback (TX to RX) */
  92 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */
  93 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */
  94
  95         u32 eee_cfg;
  96 #define EEE_CFG_EEE_ENABLED     (1<<0)  /* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */
  97 #define EEE_CFG_TX_LPI          (1<<1)
  98 #define EEE_CFG_ADV_SPEED_1G    (1<<2)
  99 #define EEE_CFG_ADV_SPEED_10G   (1<<3)
 100 #define EEE_TX_TIMER_USEC_MASK  (0xfffffff0)
 101 #define EEE_TX_TIMER_USEC_OFFSET        4
 102 #define EEE_TX_TIMER_USEC_BALANCED_TIME         (0xa00)
 103 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME       (0x100)
 104 #define EEE_TX_TIMER_USEC_LATENCY_TIME          (0x6000)
 105
 106         u32 link_modes; /* Additional link modes */
 107 #define LINK_MODE_SMARTLINQ_ENABLE              0x1  /* XXX Deprecate */
 108 };
 109
 110 struct port_mf_cfg {
 111
 112         u32 dynamic_cfg;    /* device control channel */
 113 #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff
 114 #define PORT_MF_CFG_OV_TAG_OFFSET             0
 115 #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK
 116
 117         u32 reserved[1];
 118 };
 119
 120 /* DO NOT add new fields in the middle
 121  * MUST be synced with struct pmm_stats_map
 122  */
 123 struct eth_stats {
 124         u64 r64;        /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
 125         u64 r127;       /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
 126         u64 r255;       /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
 127         u64 r511;       /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
 128         u64 r1023;      /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
 129         u64 r1518;      /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
 130         union {
 131                 struct { /* bb */
 132                         u64 r1522;      /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
 133                         u64 r2047;      /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
 134                         u64 r4095;      /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
 135                         u64 r9216;      /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
 136                         u64 r16383;     /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
 137
 138                 } bb0;
 139                 struct { /* ah */
 140                         u64 unused1;
 141                         u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/
 142                         u64 unused2;
 143                         u64 unused3;
 144                         u64 unused4;
 145                 } ah0;
 146         } u0;
 147         u64 rfcs;       /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
 148         u64 rxcf;       /* 0x10 (Offset 0x60 ) RX control frame counter*/
 149         u64 rxpf;       /* 0x11 (Offset 0x68 ) RX pause frame counter*/
 150         u64 rxpp;       /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
 151         u64 raln;       /* 0x16 (Offset 0x78 ) RX alignment error counter*/
 152         u64 rfcr;       /* 0x19 (Offset 0x80 ) RX false carrier counter */
 153         u64 rovr;       /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
 154         u64 rjbr;       /* 0x1B (Offset 0x90 ) RX jabber frame counter */
 155         u64 rund;       /* 0x34 (Offset 0x98 ) RX undersized frame counter */
 156         u64 rfrg;       /* 0x35 (Offset 0xa0 ) RX fragment counter */
 157         u64 t64;        /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
 158         u64 t127;       /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
 159         u64 t255;       /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
 160         u64 t511;       /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
 161         u64 t1023;      /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
 162         u64 t1518;      /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
 163         union {
 164                 struct { /* bb */
 165                         u64 t2047;      /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
 166                         u64 t4095;      /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
 167                         u64 t9216;      /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
 168                         u64 t16383;     /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
 169                 } bb1;
 170                 struct { /* ah */
 171                         u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */
 172                         u64 unused6;
 173                         u64 unused7;
 174                         u64 unused8;
 175                 } ah1;
 176         } u1;
 177         u64 txpf;       /* 0x50 (Offset 0xf8 ) TX pause frame counter */
 178         u64 txpp;       /* 0x51 (Offset 0x100) TX PFC frame counter */
 179         union {
 180                 struct { /* bb */
 181                         u64 tlpiec;     /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
 182                         u64 tncl;       /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
 183                 } bb2;
 184                 struct { /* ah */
 185                         u64 unused9;
 186                         u64 unused10;
 187                 } ah2;
 188         } u2;
 189         u64 rbyte;      /* 0x3d (Offset 0x118) RX byte counter */
 190         u64 rxuca;      /* 0x0c (Offset 0x120) RX UC frame counter */
 191         u64 rxmca;      /* 0x0d (Offset 0x128) RX MC frame counter */
 192         u64 rxbca;      /* 0x0e (Offset 0x130) RX BC frame counter */
 193         u64 rxpok;      /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
 194         u64 tbyte;      /* 0x6f (Offset 0x140) TX byte counter */
 195         u64 txuca;      /* 0x4d (Offset 0x148) TX UC frame counter */
 196         u64 txmca;      /* 0x4e (Offset 0x150) TX MC frame counter */
 197         u64 txbca;      /* 0x4f (Offset 0x158) TX BC frame counter */
 198         u64 txcf;       /* 0x54 (Offset 0x160) TX control frame counter */
 199         /* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */
 200 };
 201
 202 struct brb_stats {
 203         u64 brb_truncate[8];
 204         u64 brb_discard[8];
 205 };
 206
 207 struct port_stats {
 208         struct brb_stats brb;
 209         struct eth_stats eth;
 210 };
 211
 212 /*-----+-----------------------------------------------------------------------------
 213  * Chip | Number and       | Ports in| Ports in|2 PHY-s |# of ports|# of engines
 214  *      | rate of physical | team #1 | team #2 |are used|per path  | (paths) enabled
 215  *      | ports            |         |         |        |          |
 216  *======+==================+=========+=========+========+==========+=================
 217  * BB   | 1x100G           | This is special mode, where there are actually 2 HW func
 218  * BB   | 2x10/20Gbps      | 0,1     | NA      |  No    | 1        | 1
 219  * BB   | 2x40 Gbps        | 0,1     | NA      |  Yes   | 1        | 1
 220  * BB   | 2x50Gbps         | 0,1     | NA      |  No    | 1        | 1
 221  * BB   | 4x10Gbps         | 0,2     | 1,3     |  No    | 1/2      | 1,2 (2 is optional)
 222  * BB   | 4x10Gbps         | 0,1     | 2,3     |  No    | 1/2      | 1,2 (2 is optional)
 223  * BB   | 4x10Gbps         | 0,3     | 1,2     |  No    | 1/2      | 1,2 (2 is optional)
 224  * BB   | 4x10Gbps         | 0,1,2,3 | NA      |  No    | 1        | 1
 225  * AH   | 2x10/20Gbps      | 0,1     | NA      |  NA    | 1        | NA
 226  * AH   | 4x10Gbps         | 0,1     | 2,3     |  NA    | 2        | NA
 227  * AH   | 4x10Gbps         | 0,2     | 1,3     |  NA    | 2        | NA
 228  * AH   | 4x10Gbps         | 0,3     | 1,2     |  NA    | 2        | NA
 229  * AH   | 4x10Gbps         | 0,1,2,3 | NA      |  NA    | 1        | NA
 230  *======+==================+=========+=========+========+==========+===================
 231  */
 232
 233 #define CMT_TEAM0 0
 234 #define CMT_TEAM1 1
 235 #define CMT_TEAM_MAX 2
 236
 237 struct couple_mode_teaming {
 238         u8 port_cmt[MCP_GLOB_PORT_MAX];
 239 #define PORT_CMT_IN_TEAM            (1<<0)
 240
 241 #define PORT_CMT_PORT_ROLE          (1<<1)
 242 #define PORT_CMT_PORT_INACTIVE      (0<<1)
 243 #define PORT_CMT_PORT_ACTIVE        (1<<1)
 244
 245 #define PORT_CMT_TEAM_MASK          (1<<2)
 246 #define PORT_CMT_TEAM0              (0<<2)
 247 #define PORT_CMT_TEAM1              (1<<2)
 248 };
 249
 250 /**************************************
 251  *     LLDP and DCBX HSI structures
 252  **************************************/
 253 #define LLDP_CHASSIS_ID_STAT_LEN 4
 254 #define LLDP_PORT_ID_STAT_LEN 4
 255 #define DCBX_MAX_APP_PROTOCOL           32
 256 #define MAX_SYSTEM_LLDP_TLV_DATA    32
 257
 258 typedef enum _lldp_agent_e {
 259         LLDP_NEAREST_BRIDGE = 0,
 260         LLDP_NEAREST_NON_TPMR_BRIDGE,
 261         LLDP_NEAREST_CUSTOMER_BRIDGE,
 262         LLDP_MAX_LLDP_AGENTS
 263 } lldp_agent_e;
 264
 265 struct lldp_config_params_s {
 266         u32 config;
 267 #define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff
 268 #define LLDP_CONFIG_TX_INTERVAL_OFFSET       0
 269 #define LLDP_CONFIG_HOLD_MASK               0x00000f00
 270 #define LLDP_CONFIG_HOLD_OFFSET              8
 271 #define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000
 272 #define LLDP_CONFIG_MAX_CREDIT_OFFSET        12
 273 #define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000
 274 #define LLDP_CONFIG_ENABLE_RX_OFFSET         30
 275 #define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000
 276 #define LLDP_CONFIG_ENABLE_TX_OFFSET         31
 277         /* Holds local Chassis ID TLV header, subtype and 9B of payload.
 278            If firtst byte is 0, then we will use default chassis ID */
 279         u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
 280         /* Holds local Port ID TLV header, subtype and 9B of payload.
 281            If firtst byte is 0, then we will use default port ID */
 282         u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
 283 };
 284
 285 struct lldp_status_params_s {
 286         u32 prefix_seq_num;
 287         u32 status; /* TBD */
 288         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
 289         u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
 290         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
 291         u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
 292         u32 suffix_seq_num;
 293 };
 294
 295 struct dcbx_ets_feature {
 296         u32 flags;
 297 #define DCBX_ETS_ENABLED_MASK                   0x00000001
 298 #define DCBX_ETS_ENABLED_OFFSET                  0
 299 #define DCBX_ETS_WILLING_MASK                   0x00000002
 300 #define DCBX_ETS_WILLING_OFFSET                  1
 301 #define DCBX_ETS_ERROR_MASK                     0x00000004
 302 #define DCBX_ETS_ERROR_OFFSET                    2
 303 #define DCBX_ETS_CBS_MASK                       0x00000008
 304 #define DCBX_ETS_CBS_OFFSET                      3
 305 #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0
 306 #define DCBX_ETS_MAX_TCS_OFFSET                  4
 307 #define DCBX_OOO_TC_MASK                        0x00000f00
 308 #define DCBX_OOO_TC_OFFSET                      8
 309         /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
 310         u32  pri_tc_tbl[1];
 311 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */
 312 #define DCBX_TCP_OOO_TC                         (4)
 313 #define DCBX_TCP_OOO_K2_4PORT_TC                (3)
 314
 315 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET         (DCBX_TCP_OOO_TC + 1)
 316 #define DCBX_CEE_STRICT_PRIORITY                0xf
 317         /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
 318         u32  tc_bw_tbl[2];
 319         /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
 320         u32  tc_tsa_tbl[2];
 321 #define DCBX_ETS_TSA_STRICT                     0
 322 #define DCBX_ETS_TSA_CBS                        1
 323 #define DCBX_ETS_TSA_ETS                        2
 324 };
 325
 326 struct dcbx_app_priority_entry {
 327         u32 entry;
 328 #define DCBX_APP_PRI_MAP_MASK       0x000000ff
 329 #define DCBX_APP_PRI_MAP_OFFSET      0
 330 #define DCBX_APP_PRI_0              0x01
 331 #define DCBX_APP_PRI_1              0x02
 332 #define DCBX_APP_PRI_2              0x04
 333 #define DCBX_APP_PRI_3              0x08
 334 #define DCBX_APP_PRI_4              0x10
 335 #define DCBX_APP_PRI_5              0x20
 336 #define DCBX_APP_PRI_6              0x40
 337 #define DCBX_APP_PRI_7              0x80
 338 #define DCBX_APP_SF_MASK            0x00000300
 339 #define DCBX_APP_SF_OFFSET           8
 340 #define DCBX_APP_SF_ETHTYPE         0
 341 #define DCBX_APP_SF_PORT            1
 342 #define DCBX_APP_SF_IEEE_MASK       0x0000f000
 343 #define DCBX_APP_SF_IEEE_OFFSET      12
 344 #define DCBX_APP_SF_IEEE_RESERVED   0
 345 #define DCBX_APP_SF_IEEE_ETHTYPE    1
 346 #define DCBX_APP_SF_IEEE_TCP_PORT   2
 347 #define DCBX_APP_SF_IEEE_UDP_PORT   3
 348 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
 349
 350 #define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000
 351 #define DCBX_APP_PROTOCOL_ID_OFFSET  16
 352 };
 353
 354
 355 /* FW structure in BE */
 356 struct dcbx_app_priority_feature {
 357         u32 flags;
 358 #define DCBX_APP_ENABLED_MASK           0x00000001
 359 #define DCBX_APP_ENABLED_OFFSET          0
 360 #define DCBX_APP_WILLING_MASK           0x00000002
 361 #define DCBX_APP_WILLING_OFFSET          1
 362 #define DCBX_APP_ERROR_MASK             0x00000004
 363 #define DCBX_APP_ERROR_OFFSET            2
 364         /* Not in use
 365         #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
 366         #define DCBX_APP_DEFAULT_PRI_OFFSET      8
 367         */
 368 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
 369 #define DCBX_APP_MAX_TCS_OFFSET          12
 370 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
 371 #define DCBX_APP_NUM_ENTRIES_OFFSET      16
 372         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
 373 };
 374
 375 /* FW structure in BE */
 376 struct dcbx_features {
 377         /* PG feature */
 378         struct dcbx_ets_feature ets;
 379         /* PFC feature */
 380         u32 pfc;
 381 #define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff
 382 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET            0
 383 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01
 384 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02
 385 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04
 386 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08
 387 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10
 388 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20
 389 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40
 390 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80
 391
 392 #define DCBX_PFC_FLAGS_MASK                     0x0000ff00
 393 #define DCBX_PFC_FLAGS_OFFSET                    8
 394 #define DCBX_PFC_CAPS_MASK                      0x00000f00
 395 #define DCBX_PFC_CAPS_OFFSET                     8
 396 #define DCBX_PFC_MBC_MASK                       0x00004000
 397 #define DCBX_PFC_MBC_OFFSET                      14
 398 #define DCBX_PFC_WILLING_MASK                   0x00008000
 399 #define DCBX_PFC_WILLING_OFFSET                  15
 400 #define DCBX_PFC_ENABLED_MASK                   0x00010000
 401 #define DCBX_PFC_ENABLED_OFFSET                  16
 402 #define DCBX_PFC_ERROR_MASK                     0x00020000
 403 #define DCBX_PFC_ERROR_OFFSET                    17
 404
 405         /* APP feature */
 406         struct dcbx_app_priority_feature app;
 407 };
 408
 409 struct dcbx_local_params {
 410         u32 config;
 411 #define DCBX_CONFIG_VERSION_MASK            0x00000007
 412 #define DCBX_CONFIG_VERSION_OFFSET           0
 413 #define DCBX_CONFIG_VERSION_DISABLED        0
 414 #define DCBX_CONFIG_VERSION_IEEE            1
 415 #define DCBX_CONFIG_VERSION_CEE             2
 416 #define DCBX_CONFIG_VERSION_STATIC          4
 417
 418         u32 flags;
 419         struct dcbx_features features;
 420 };
 421
 422 struct dcbx_mib {
 423         u32 prefix_seq_num;
 424         u32 flags;
 425         /*
 426         #define DCBX_CONFIG_VERSION_MASK            0x00000007
 427         #define DCBX_CONFIG_VERSION_OFFSET           0
 428         #define DCBX_CONFIG_VERSION_DISABLED        0
 429         #define DCBX_CONFIG_VERSION_IEEE            1
 430         #define DCBX_CONFIG_VERSION_CEE             2
 431         #define DCBX_CONFIG_VERSION_STATIC          4
 432         */
 433         struct dcbx_features features;
 434         u32 suffix_seq_num;
 435 };
 436
 437 struct lldp_system_tlvs_buffer_s {
 438         u16 valid;
 439         u16 length;
 440         u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
 441 };
 442
 443 struct dcb_dscp_map {
 444         u32 flags;
 445 #define DCB_DSCP_ENABLE_MASK                    0x1
 446 #define DCB_DSCP_ENABLE_OFFSET                  0
 447 #define DCB_DSCP_ENABLE                         1
 448         u32 dscp_pri_map[8];
 449         /* the map structure is the following:
 450            each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp
 451            Lowest dscp is at lsb
 452                             31          28          24          20          16          12          8           4           0
 453            dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri |
 454            dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri |
 455            etc.*/
 456 };
 457
 458 /**************************************/
 459 /*                                    */
 460 /*     P U B L I C      G L O B A L   */
 461 /*                                    */
 462 /**************************************/
 463 struct public_global {
 464         u32 max_path;       /* 32bit is wasty, but this will be used often */
 465         u32 max_ports;      /* (Global) 32bit is wasty, but this will be used often */
 466 #define MODE_1P 1               /* TBD - NEED TO THINK OF A BETTER NAME */
 467 #define MODE_2P 2
 468 #define MODE_3P 3
 469 #define MODE_4P 4
 470         u32 debug_mb_offset;
 471         u32 phymod_dbg_mb_offset;
 472         struct couple_mode_teaming cmt;
 473         s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */
 474         u32 mfw_ver;
 475         u32 running_bundle_id;
 476         s32 external_temperature;
 477         u32 mdump_reason;
 478 #define MDUMP_REASON_INTERNAL_ERROR     (1 << 0)
 479 #define MDUMP_REASON_EXTERNAL_TRIGGER   (1 << 1)
 480 #define MDUMP_REASON_DUMP_AGED          (1 << 2)
 481         u32 ext_phy_upgrade_fw;
 482 #define EXT_PHY_FW_UPGRADE_STATUS_MASK          (0x0000ffff)
 483 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET                (0)
 484 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS   (1)
 485 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED        (2)
 486 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS       (3)
 487 #define EXT_PHY_FW_UPGRADE_TYPE_MASK            (0xffff0000)
 488 #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET          (16)
 489
 490         u8 runtime_port_swap_map[MODE_4P];
 491         u32 data_ptr;
 492         u32 data_size;
 493 };
 494
 495 /**************************************/
 496 /*                                    */
 497 /*     P U B L I C      P A T H       */
 498 /*                                    */
 499 /**************************************/
 500
 501 /****************************************************************************
 502  * Shared Memory 2 Region                                                   *
 503  ****************************************************************************/
 504 /* The fw_flr_ack is actually built in the following way:                   */
 505 /* 8 bit:  PF ack                                                           */
 506 /* 128 bit: VF ack                                                           */
 507 /* 8 bit:  ios_dis_ack                                                      */
 508 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
 509 /* u32. The fw must have the VF right after the PF since this is how it     */
 510 /* access arrays(it expects always the VF to reside after the PF, and that  */
 511 /* makes the calculation much easier for it. )                              */
 512 /* In order to answer both limitations, and keep the struct small, the code */
 513 /* will abuse the structure defined here to achieve the actual partition    */
 514 /* above                                                                    */
 515 /****************************************************************************/
 516 struct fw_flr_mb {
 517         u32 aggint;
 518         u32 opgen_addr;
 519         u32 accum_ack;      /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
 520 #define ACCUM_ACK_PF_BASE       0
 521 #define ACCUM_ACK_PF_SHIFT      0
 522
 523 #define ACCUM_ACK_VF_BASE       8
 524 #define ACCUM_ACK_VF_SHIFT      3
 525
 526 #define ACCUM_ACK_IOV_DIS_BASE  256
 527 #define ACCUM_ACK_IOV_DIS_SHIFT 8
 528
 529 };
 530
 531 struct public_path {
 532         struct fw_flr_mb flr_mb;
 533         /*
 534          * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
 535          * which were disabled/flred
 536          */
 537         u32 mcp_vf_disabled[VF_MAX_STATIC / 32];    /* 0x003c */
 538
 539         u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */
 540 #define PROCESS_KILL_COUNTER_MASK               0x0000ffff
 541 #define PROCESS_KILL_COUNTER_OFFSET             0
 542 #define PROCESS_KILL_GLOB_AEU_BIT_MASK          0xffff0000
 543 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET                16
 544 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit)
 545 };
 546
 547 /**************************************/
 548 /*                                    */
 549 /*     P U B L I C      P O R T       */
 550 /*                                    */
 551 /**************************************/
 552 #define FC_NPIV_WWPN_SIZE 8
 553 #define FC_NPIV_WWNN_SIZE 8
 554 struct dci_npiv_settings {
 555         u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
 556         u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
 557 };
 558
 559 struct dci_fc_npiv_cfg {
 560         /* hdr used internally by the MFW */
 561         u32 hdr;
 562         u32 num_of_npiv;
 563 };
 564
 565 #define MAX_NUMBER_NPIV 64
 566 struct dci_fc_npiv_tbl {
 567         struct dci_fc_npiv_cfg fc_npiv_cfg;
 568         struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
 569 };
 570
 571 /****************************************************************************
 572  * Driver <-> FW Mailbox                                                    *
 573  ****************************************************************************/
 574
 575 struct public_port {
 576         u32 validity_map;   /* 0x0 (4*2 = 0x8) */
 577
 578         /* validity bits */
 579 #define MCP_VALIDITY_PCI_CFG                    0x00100000
 580 #define MCP_VALIDITY_MB                         0x00200000
 581 #define MCP_VALIDITY_DEV_INFO                   0x00400000
 582 #define MCP_VALIDITY_RESERVED                   0x00000007
 583
 584         /* One licensing bit should be set */
 585 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038      /* yaniv - tbd ? license */
 586 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
 587 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
 588 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
 589
 590         /* Active MFW */
 591 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
 592 #define MCP_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
 593 #define MCP_VALIDITY_ACTIVE_MFW_NCSI            0x00000040
 594 #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
 595
 596         u32 link_status;
 597 #define LINK_STATUS_LINK_UP                             0x00000001
 598 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001e
 599 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (1<<1)
 600 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (2<<1)
 601 #define LINK_STATUS_SPEED_AND_DUPLEX_10G                (3<<1)
 602 #define LINK_STATUS_SPEED_AND_DUPLEX_20G                (4<<1)
 603 #define LINK_STATUS_SPEED_AND_DUPLEX_40G                (5<<1)
 604 #define LINK_STATUS_SPEED_AND_DUPLEX_50G                (6<<1)
 605 #define LINK_STATUS_SPEED_AND_DUPLEX_100G               (7<<1)
 606 #define LINK_STATUS_SPEED_AND_DUPLEX_25G                (8<<1)
 607 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
 608 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
 609 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
 610 #define LINK_STATUS_PFC_ENABLED                         0x00000100
 611 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
 612 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
 613 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
 614 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
 615 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
 616 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
 617 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
 618 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
 619 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
 620 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
 621 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
 622 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
 623 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
 624 #define LINK_STATUS_SFP_TX_FAULT                        0x00100000
 625 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00200000
 626 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00400000
 627 #define LINK_STATUS_RX_SIGNAL_PRESENT                   0x00800000
 628 #define LINK_STATUS_MAC_LOCAL_FAULT                     0x01000000
 629 #define LINK_STATUS_MAC_REMOTE_FAULT                    0x02000000
 630 #define LINK_STATUS_UNSUPPORTED_SPD_REQ                 0x04000000
 631 #define LINK_STATUS_FEC_MODE_MASK                       0x38000000
 632 #define LINK_STATUS_FEC_MODE_NONE                       (0<<27)
 633 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74              (1<<27)
 634 #define LINK_STATUS_FEC_MODE_RS_CL91                    (2<<27)
 635 #define LINK_STATUS_EXT_PHY_LINK_UP                     0x40000000
 636
 637         u32 link_status1;
 638         u32 ext_phy_fw_version;
 639         u32 drv_phy_cfg_addr;   /* Points to struct eth_phy_cfg (For READ-ONLY) */
 640
 641         u32 port_stx;
 642
 643         u32 stat_nig_timer;
 644
 645         struct port_mf_cfg port_mf_config;
 646         struct port_stats stats;
 647
 648         u32 media_type;
 649 #define MEDIA_UNSPECIFIED               0x0
 650 #define MEDIA_SFPP_10G_FIBER    0x1     /* Use MEDIA_MODULE_FIBER instead */
 651 #define MEDIA_XFP_FIBER                 0x2     /* Use MEDIA_MODULE_FIBER instead */
 652 #define MEDIA_DA_TWINAX                 0x3
 653 #define MEDIA_BASE_T                    0x4
 654 #define MEDIA_SFP_1G_FIBER              0x5     /* Use MEDIA_MODULE_FIBER instead */
 655 #define MEDIA_MODULE_FIBER              0x6
 656 #define MEDIA_KR                                0xf0
 657 #define MEDIA_NOT_PRESENT               0xff
 658
 659         u32 lfa_status;
 660 #define LFA_LINK_FLAP_REASON_OFFSET             0
 661 #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
 662 #define LFA_NO_REASON                                   (0<<0)
 663 #define LFA_LINK_DOWN                                   (1<<0)
 664 #define LFA_FORCE_INIT                                  (1<<1)
 665 #define LFA_LOOPBACK_MISMATCH                           (1<<2)
 666 #define LFA_SPEED_MISMATCH                              (1<<3)
 667 #define LFA_FLOW_CTRL_MISMATCH                          (1<<4)
 668 #define LFA_ADV_SPEED_MISMATCH                          (1<<5)
 669 #define LFA_EEE_MISMATCH                                (1<<6)
 670 #define LFA_LINK_MODES_MISMATCH                 (1<<7)
 671 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
 672 #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
 673 #define LINK_FLAP_COUNT_OFFSET                  16
 674 #define LINK_FLAP_COUNT_MASK                    0x00ff0000
 675
 676         u32 link_change_count;
 677
 678         /* LLDP params */
 679         struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];  // offset: 536 bytes?
 680         struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
 681         struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
 682
 683         /* DCBX related MIB */
 684         struct dcbx_local_params local_admin_dcbx_mib;
 685         struct dcbx_mib remote_dcbx_mib;
 686         struct dcbx_mib operational_dcbx_mib;
 687
 688         /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
 689         u32 fc_npiv_nvram_tbl_addr;
 690 #define NPIV_TBL_INVALID_ADDR                   0xFFFFFFFF
 691
 692         u32 fc_npiv_nvram_tbl_size;
 693         u32 transceiver_data;
 694 #define ETH_TRANSCEIVER_STATE_MASK              0x000000FF
 695 #define ETH_TRANSCEIVER_STATE_OFFSET            0x0
 696 #define ETH_TRANSCEIVER_STATE_UNPLUGGED                 0x00
 697 #define ETH_TRANSCEIVER_STATE_PRESENT                   0x01
 698 #define ETH_TRANSCEIVER_STATE_VALID                     0x03
 699 #define ETH_TRANSCEIVER_STATE_UPDATING                  0x08
 700 #define ETH_TRANSCEIVER_TYPE_MASK               0x0000FF00
 701 #define ETH_TRANSCEIVER_TYPE_OFFSET             0x8
 702 #define ETH_TRANSCEIVER_TYPE_NONE                       0x00
 703 #define ETH_TRANSCEIVER_TYPE_UNKNOWN                    0xFF
 704 #define ETH_TRANSCEIVER_TYPE_1G_PCC                     0x01 /* 1G Passive copper cable */
 705 #define ETH_TRANSCEIVER_TYPE_1G_ACC                     0x02 /* 1G Active copper cable  */
 706 #define ETH_TRANSCEIVER_TYPE_1G_LX                      0x03
 707 #define ETH_TRANSCEIVER_TYPE_1G_SX                      0x04
 708 #define ETH_TRANSCEIVER_TYPE_10G_SR                     0x05
 709 #define ETH_TRANSCEIVER_TYPE_10G_LR                     0x06
 710 #define ETH_TRANSCEIVER_TYPE_10G_LRM                    0x07
 711 #define ETH_TRANSCEIVER_TYPE_10G_ER                     0x08
 712 #define ETH_TRANSCEIVER_TYPE_10G_PCC                    0x09 /* 10G Passive copper cable */
 713 #define ETH_TRANSCEIVER_TYPE_10G_ACC                    0x0a /* 10G Active copper cable  */
 714 #define ETH_TRANSCEIVER_TYPE_XLPPI                      0x0b
 715 #define ETH_TRANSCEIVER_TYPE_40G_LR4                    0x0c
 716 #define ETH_TRANSCEIVER_TYPE_40G_SR4                    0x0d
 717 #define ETH_TRANSCEIVER_TYPE_40G_CR4                    0x0e
 718 #define ETH_TRANSCEIVER_TYPE_100G_AOC                   0x0f /* Active optical cable */
 719 #define ETH_TRANSCEIVER_TYPE_100G_SR4                   0x10
 720 #define ETH_TRANSCEIVER_TYPE_100G_LR4                   0x11
 721 #define ETH_TRANSCEIVER_TYPE_100G_ER4                   0x12
 722 #define ETH_TRANSCEIVER_TYPE_100G_ACC                   0x13 /* Active copper cable */
 723 #define ETH_TRANSCEIVER_TYPE_100G_CR4                   0x14
 724 #define ETH_TRANSCEIVER_TYPE_4x10G_SR                   0x15
 725 #define ETH_TRANSCEIVER_TYPE_25G_CA_N                   0x16 /* 25G Passive copper cable - short */
 726 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S                  0x17 /* 25G Active copper cable  - short */
 727 #define ETH_TRANSCEIVER_TYPE_25G_CA_S                   0x18 /* 25G Passive copper cable - medium */
 728 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M                  0x19 /* 25G Active copper cable  - medium */
 729 #define ETH_TRANSCEIVER_TYPE_25G_CA_L                   0x1a /* 25G Passive copper cable - long */
 730 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L                  0x1b /* 25G Active copper cable  - long */
 731 #define ETH_TRANSCEIVER_TYPE_25G_SR                     0x1c
 732 #define ETH_TRANSCEIVER_TYPE_25G_LR                     0x1d
 733 #define ETH_TRANSCEIVER_TYPE_25G_AOC                    0x1e
 734 #define ETH_TRANSCEIVER_TYPE_4x10G                      0x1f
 735 #define ETH_TRANSCEIVER_TYPE_4x25G_CR                   0x20
 736 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR      0x30
 737 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR      0x31
 738 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR      0x32
 739 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR     0x33
 740 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR     0x34
 741 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR     0x35
 742 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC    0x36
 743         u32 wol_info;
 744         u32 wol_pkt_len;
 745         u32 wol_pkt_details;
 746         struct dcb_dscp_map dcb_dscp_map;
 747
 748         u32 eee_status;
 749 #define EEE_ACTIVE_BIT          (1<<0)          /* Set when EEE negotiation is complete. */
 750
 751 #define EEE_LD_ADV_STATUS_MASK  0x000000f0      /* Shows the Local Device EEE capabilities */
 752 #define EEE_LD_ADV_STATUS_OFFSET        4
 753         #define EEE_1G_ADV      (1<<1)
 754         #define EEE_10G_ADV     (1<<2)
 755 #define EEE_LP_ADV_STATUS_MASK  0x00000f00      /* Same values as in EEE_LD_ADV, but for Link Parter */
 756 #define EEE_LP_ADV_STATUS_OFFSET        8
 757
 758         u32 eee_remote; /* Used for EEE in LLDP */
 759 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
 760 #define EEE_REMOTE_TW_TX_OFFSET 0
 761 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
 762 #define EEE_REMOTE_TW_RX_OFFSET 16
 763
 764         u32 module_info;
 765 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK            0x000000FF
 766 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET          0
 767 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED              (1 << 2)
 768 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE            (1 << 3)
 769 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED           (1 << 4)
 770 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED           (1 << 5)
 771 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC                  (1 << 6)
 772 #define ETH_TRANSCEIVER_IDENT_MASK                      0x0000ff00
 773 #define ETH_TRANSCEIVER_IDENT_OFFSET                    8
 774 };
 775
 776 /**************************************/
 777 /*                                    */
 778 /*     P U B L I C      F U N C       */
 779 /*                                    */
 780 /**************************************/
 781
 782 struct public_func {
 783
 784         u32 iscsi_boot_signature;
 785         u32 iscsi_boot_block_offset;
 786
 787         /* MTU size per funciton is needed for the OV feature */
 788         u32 mtu_size;
 789         /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
 790         /* For PCP values 0-3 use the map lower */
 791         /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
 792          * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
 793          */
 794         u32 c2s_pcp_map_lower;
 795         /* For PCP values 4-7 use the map upper */
 796         /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
 797          * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
 798         */
 799         u32 c2s_pcp_map_upper;
 800
 801         /* For PCP default value get the MSB byte of the map default */
 802         u32 c2s_pcp_map_default;
 803
 804         u32 reserved[4];
 805
 806         // replace old mf_cfg
 807         u32 config;
 808         /* E/R/I/D */
 809         /* function 0 of each port cannot be hidden */
 810 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
 811 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
 812 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET    0x00000001
 813
 814
 815 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
 816 #define FUNC_MF_CFG_PROTOCOL_OFFSET              4
 817 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
 818 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
 819 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
 820 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
 821 #define FUNC_MF_CFG_PROTOCOL_MAX                0x00000030
 822
 823         /* MINBW, MAXBW */
 824         /* value range - 0..100, increments in 1 %  */
 825 #define FUNC_MF_CFG_MIN_BW_MASK                 0x0000ff00
 826 #define FUNC_MF_CFG_MIN_BW_OFFSET                8
 827 #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
 828 #define FUNC_MF_CFG_MAX_BW_MASK                 0x00ff0000
 829 #define FUNC_MF_CFG_MAX_BW_OFFSET                16
 830 #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x00640000
 831
 832         /*RDMA PROTOCL*/
 833 #define FUNC_MF_CFG_RDMA_PROTOCOL_MASK          0x03000000
 834 #define FUNC_MF_CFG_RDMA_PROTOCOL_OFFSET         24
 835 #define FUNC_MF_CFG_RDMA_PROTOCOL_NONE          0x00000000
 836 #define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE          0x01000000
 837 #define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP         0x02000000
 838         /*for future support*/
 839 #define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH          0x03000000
 840
 841 #define FUNC_MF_CFG_BOOT_MODE_MASK              0x0C000000
 842 #define FUNC_MF_CFG_BOOT_MODE_OFFSET            26
 843 #define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL         0x00000000
 844 #define FUNC_MF_CFG_BOOT_MODE_DISABLED          0x04000000
 845 #define FUNC_MF_CFG_BOOT_MODE_ENABLED           0x08000000
 846
 847         u32 status;
 848 #define FUNC_STATUS_VLINK_DOWN                  0x00000001
 849
 850         u32 mac_upper;      /* MAC */
 851 #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
 852 #define FUNC_MF_CFG_UPPERMAC_OFFSET              0
 853 #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK
 854         u32 mac_lower;
 855 #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
 856
 857         u32 fcoe_wwn_port_name_upper;
 858         u32 fcoe_wwn_port_name_lower;
 859
 860         u32 fcoe_wwn_node_name_upper;
 861         u32 fcoe_wwn_node_name_lower;
 862
 863         u32 ovlan_stag;     /* tags */
 864 #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff
 865 #define FUNC_MF_CFG_OV_STAG_OFFSET             0
 866 #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK
 867
 868         u32 pf_allocation; /* vf per pf */
 869
 870         u32 preserve_data; /* Will be used bt CCM */
 871
 872         u32 driver_last_activity_ts;
 873
 874         /*
 875          * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
 876          * VFs
 877          */
 878         u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];    /* 0x0044 */
 879
 880         u32 drv_id;
 881 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
 882 #define DRV_ID_PDA_COMP_VER_OFFSET      0
 883
 884 #define LOAD_REQ_HSI_VERSION            2
 885 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
 886 #define DRV_ID_MCP_HSI_VER_OFFSET       16
 887 #define DRV_ID_MCP_HSI_VER_CURRENT      (LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_OFFSET)
 888
 889 #define DRV_ID_DRV_TYPE_MASK            0x7f000000
 890 #define DRV_ID_DRV_TYPE_OFFSET          24
 891 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_OFFSET)
 892 #define DRV_ID_DRV_TYPE_LINUX           (1 << DRV_ID_DRV_TYPE_OFFSET)
 893 #define DRV_ID_DRV_TYPE_WINDOWS         (2 << DRV_ID_DRV_TYPE_OFFSET)
 894 #define DRV_ID_DRV_TYPE_DIAG            (3 << DRV_ID_DRV_TYPE_OFFSET)
 895 #define DRV_ID_DRV_TYPE_PREBOOT         (4 << DRV_ID_DRV_TYPE_OFFSET)
 896 #define DRV_ID_DRV_TYPE_SOLARIS         (5 << DRV_ID_DRV_TYPE_OFFSET)
 897 #define DRV_ID_DRV_TYPE_VMWARE          (6 << DRV_ID_DRV_TYPE_OFFSET)
 898 #define DRV_ID_DRV_TYPE_FREEBSD         (7 << DRV_ID_DRV_TYPE_OFFSET)
 899 #define DRV_ID_DRV_TYPE_AIX             (8 << DRV_ID_DRV_TYPE_OFFSET)
 900
 901 #define DRV_ID_DRV_TYPE_OS                      (DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \
 902                                                                          DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \
 903                                                                          DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX)
 904
 905 #define DRV_ID_DRV_INIT_HW_MASK         0x80000000
 906 #define DRV_ID_DRV_INIT_HW_OFFSET       31
 907 #define DRV_ID_DRV_INIT_HW_FLAG         (1 << DRV_ID_DRV_INIT_HW_OFFSET)
 908 };
 909
 910 /**************************************/
 911 /*                                    */
 912 /*     P U B L I C       M B          */
 913 /*                                    */
 914 /**************************************/
 915 /* This is the only section that the driver can write to, and each */
 916 /* Basically each driver request to set feature parameters,
 917  * will be done using a different command, which will be linked
 918  * to a specific data structure from the union below.
 919  * For huge strucuture, the common blank structure should be used.
 920  */
 921
 922 struct mcp_mac {
 923         u32 mac_upper;      /* Upper 16 bits are always zeroes */
 924         u32 mac_lower;
 925 };
 926
 927 struct mcp_val64 {
 928         u32 lo;
 929         u32 hi;
 930 };
 931
 932 struct mcp_file_att {
 933         u32 nvm_start_addr;
 934         u32 len;
 935 };
 936
 937 struct bist_nvm_image_att {
 938         u32 return_code;
 939         u32 image_type;         /* Image type */
 940         u32 nvm_start_addr;     /* NVM address of the image */
 941         u32 len;                /* Include CRC */
 942 };
 943
 944 #define MCP_DRV_VER_STR_SIZE 16
 945 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
 946 #define MCP_DRV_NVM_BUF_LEN 32
 947 struct drv_version_stc {
 948         u32 version;
 949         u8 name[MCP_DRV_VER_STR_SIZE - 4];
 950 };
 951
 952 /* statistics for ncsi */
 953 struct lan_stats_stc {
 954         u64 ucast_rx_pkts;
 955         u64 ucast_tx_pkts;
 956         u32 fcs_err;
 957         u32 rserved;
 958 };
 959
 960 struct fcoe_stats_stc {
 961         u64 rx_pkts;
 962         u64 tx_pkts;
 963         u32 fcs_err;
 964         u32 login_failure;
 965 };
 966
 967 struct iscsi_stats_stc {
 968         u64 rx_pdus;
 969         u64 tx_pdus;
 970         u64 rx_bytes;
 971         u64 tx_bytes;
 972 };
 973
 974 struct rdma_stats_stc {
 975         u64 rx_pkts;
 976         u64 tx_pkts;
 977         u64 rx_bytes;
 978         u64 tx_bytes;
 979 };
 980
 981 struct ocbb_data_stc {
 982         u32 ocbb_host_addr;
 983         u32 ocsd_host_addr;
 984         u32 ocsd_req_update_interval;
 985 };
 986
 987 #define MAX_NUM_OF_SENSORS                      7
 988 #define MFW_SENSOR_LOCATION_INTERNAL            1
 989 #define MFW_SENSOR_LOCATION_EXTERNAL            2
 990 #define MFW_SENSOR_LOCATION_SFP                 3
 991
 992 #define SENSOR_LOCATION_OFFSET                  0
 993 #define SENSOR_LOCATION_MASK                    0x000000ff
 994 #define THRESHOLD_HIGH_OFFSET                   8
 995 #define THRESHOLD_HIGH_MASK                     0x0000ff00
 996 #define CRITICAL_TEMPERATURE_OFFSET             16
 997 #define CRITICAL_TEMPERATURE_MASK               0x00ff0000
 998 #define CURRENT_TEMP_OFFSET                     24
 999 #define CURRENT_TEMP_MASK                       0xff000000
1000 struct temperature_status_stc {
1001         u32 num_of_sensors;
1002         u32 sensor[MAX_NUM_OF_SENSORS];
1003 };
1004
1005 /* crash dump configuration header */
1006 struct mdump_config_stc {
1007         u32 version;
1008         u32 config;
1009         u32 epoc;
1010         u32 num_of_logs;
1011         u32 valid_logs;
1012 };
1013
1014 enum resource_id_enum {
1015         RESOURCE_NUM_SB_E               =       0,
1016         RESOURCE_NUM_L2_QUEUE_E         =       1,
1017         RESOURCE_NUM_VPORT_E            =       2,
1018         RESOURCE_NUM_VMQ_E              =       3,
1019         RESOURCE_FACTOR_NUM_RSS_PF_E    =       4,  /* Not a real resource!! it's a factor used to calculate others */
1020         RESOURCE_FACTOR_RSS_PER_VF_E    =       5,  /* Not a real resource!! it's a factor used to calculate others */
1021         RESOURCE_NUM_RL_E               =       6,
1022         RESOURCE_NUM_PQ_E               =       7,
1023         RESOURCE_NUM_VF_E               =       8,
1024         RESOURCE_VFC_FILTER_E           =       9,
1025         RESOURCE_ILT_E                  =       10,
1026         RESOURCE_CQS_E                  =       11,
1027         RESOURCE_GFT_PROFILES_E         =       12,
1028         RESOURCE_NUM_TC_E               =       13,
1029         RESOURCE_NUM_RSS_ENGINES_E      =       14,
1030         RESOURCE_LL2_QUEUE_E            =       15,
1031         RESOURCE_RDMA_STATS_QUEUE_E     =       16,
1032         RESOURCE_BDQ_E                  =       17,
1033         RESOURCE_MAX_NUM,
1034         RESOURCE_NUM_INVALID            =       0xFFFFFFFF
1035 };
1036
1037 /* Resource ID is to be filled by the driver in the MB request
1038  * Size, offset & flags to be filled by the MFW in the MB response
1039  */
1040 struct resource_info {
1041         enum resource_id_enum res_id;
1042         u32 size; /* number of allocated resources */
1043         u32 offset; /* Offset of the 1st resource */
1044         u32 vf_size;
1045         u32 vf_offset;
1046         u32 flags;
1047 #define RESOURCE_ELEMENT_STRICT (1 << 0)
1048 };
1049
1050 struct mcp_wwn {
1051         u32 wwn_upper;
1052         u32 wwn_lower;
1053 };
1054
1055 #define DRV_ROLE_NONE           0
1056 #define DRV_ROLE_PREBOOT        1
1057 #define DRV_ROLE_OS             2
1058 #define DRV_ROLE_KDUMP          3
1059
1060 struct load_req_stc {
1061         u32 drv_ver_0;
1062         u32 drv_ver_1;
1063         u32 fw_ver;
1064         u32 misc0;
1065 #define LOAD_REQ_ROLE_MASK              0x000000FF
1066 #define LOAD_REQ_ROLE_OFFSET            0
1067 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
1068 #define LOAD_REQ_LOCK_TO_OFFSET         8
1069 #define LOAD_REQ_LOCK_TO_DEFAULT        0
1070 #define LOAD_REQ_LOCK_TO_NONE           255
1071 #define LOAD_REQ_FORCE_MASK             0x000F0000
1072 #define LOAD_REQ_FORCE_OFFSET           16
1073 #define LOAD_REQ_FORCE_NONE             0
1074 #define LOAD_REQ_FORCE_PF               1
1075 #define LOAD_REQ_FORCE_ALL              2
1076 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
1077 #define LOAD_REQ_FLAGS0_OFFSET          20
1078 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
1079 };
1080
1081 struct load_rsp_stc {
1082         u32 drv_ver_0;
1083         u32 drv_ver_1;
1084         u32 fw_ver;
1085         u32 misc0;
1086 #define LOAD_RSP_ROLE_MASK              0x000000FF
1087 #define LOAD_RSP_ROLE_OFFSET            0
1088 #define LOAD_RSP_HSI_MASK               0x0000FF00
1089 #define LOAD_RSP_HSI_OFFSET             8
1090 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
1091 #define LOAD_RSP_FLAGS0_OFFSET          16
1092 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
1093 };
1094
1095 struct mdump_retain_data_stc {
1096         u32 valid;
1097         u32 epoch;
1098         u32 pf;
1099         u32 status;
1100 };
1101
1102 union drv_union_data {
1103         struct mcp_mac wol_mac; /* UNLOAD_DONE */
1104
1105         /* This configuration should be set by the driver for the LINK_SET command. */
1106         struct eth_phy_cfg drv_phy_cfg;
1107
1108         struct mcp_val64 val64; /* For PHY / AVS commands */
1109
1110         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
1111
1112         struct mcp_file_att file_att;
1113
1114         u32 ack_vf_disabled[VF_MAX_STATIC / 32];
1115
1116         struct drv_version_stc drv_version;
1117
1118         struct lan_stats_stc lan_stats;
1119         struct fcoe_stats_stc fcoe_stats;
1120         struct iscsi_stats_stc iscsi_stats;
1121         struct rdma_stats_stc rdma_stats;
1122         struct ocbb_data_stc ocbb_info;
1123         struct temperature_status_stc temp_info;
1124         struct resource_info resource;
1125         struct bist_nvm_image_att nvm_image_att;
1126         struct mdump_config_stc mdump_config;
1127         struct mcp_mac lldp_mac;
1128         struct mcp_wwn fcoe_fabric_name;
1129         u32 dword;
1130
1131         struct load_req_stc load_req;
1132         struct load_rsp_stc load_rsp;
1133         struct mdump_retain_data_stc mdump_retain;
1134         /* ... */
1135 };
1136
1137 struct public_drv_mb {
1138
1139         u32 drv_mb_header;
1140 #define DRV_MSG_CODE_MASK                       0xffff0000
1141 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1142 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1143 #define DRV_MSG_CODE_INIT_HW                    0x12000000
1144 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
1145 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
1146 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1147 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
1148         /* Params - FORCE - Reinitialize the link regardless of LFA */
1149         /*        - DONT_CARE - Don't flap the link if up */
1150 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
1151
1152         // Vitaly: LLDP commands
1153 #define DRV_MSG_CODE_SET_LLDP                   0x24000000
1154 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
1155         /* OneView feature driver HSI*/
1156 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
1157 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
1158 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
1159 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
1160 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
1161 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
1162 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
1163 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
1164 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG          0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */
1165 #define DRV_MSG_SET_RESOURCE_VALUE_MSG          0x35000000
1166 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
1167 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
1168 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK           0x3b000000
1169 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID       0x3c000000
1170 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME        0x3d000000
1171 #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG        0x3e000000
1172 #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT       0x3f000000
1173 #define DRV_MSG_CODE_OV_GET_CURR_CFG            0x40000000
1174
1175 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED    0x02000000 /*deprecated don't use*/
1176 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
1177 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1178 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
1179 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX            0xc0020000
1180 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN         0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */
1181 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA          0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */
1182 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000 /* MFW will place the file offset and len in file_att struct */
1183 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/
1184 #define DRV_MSG_CODE_NVM_WRITE_NVRAM            0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */
1185 #define DRV_MSG_CODE_NVM_DEL_FILE               0x00080000 /* Delete a file from nvram. Param is image_type. */
1186 #define DRV_MSG_CODE_MCP_RESET                  0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */
1187 #define DRV_MSG_CODE_SET_SECURE_MODE            0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */
1188 #define DRV_MSG_CODE_PHY_RAW_READ               0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/
1189 #define DRV_MSG_CODE_PHY_RAW_WRITE              0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */
1190 #define DRV_MSG_CODE_PHY_CORE_READ              0x000d0000 /* Param: [0:15] - Address, [30:31] - port */
1191 #define DRV_MSG_CODE_PHY_CORE_WRITE             0x000e0000 /* Param: [0:15] - Address, [30:31] - port */
1192 #define DRV_MSG_CODE_SET_VERSION                0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */
1193 #define DRV_MSG_CODE_MCP_HALT                   0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */
1194 #define DRV_MSG_CODE_SET_VMAC                   0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1195 #define DRV_MSG_CODE_GET_VMAC                   0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1196 #define DRV_MSG_CODE_VMAC_TYPE_OFFSET           4
1197 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
1198 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
1199 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
1200 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
1201
1202 #define DRV_MSG_CODE_GET_STATS                  0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */
1203 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
1204 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
1205 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
1206 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
1207 #define DRV_MSG_CODE_PMD_DIAG_DUMP              0x00140000 /* Host shall provide buffer and size for MFW  */
1208 #define DRV_MSG_CODE_PMD_DIAG_EYE               0x00150000 /* Host shall provide buffer and size for MFW  */
1209 #define DRV_MSG_CODE_TRANSCEIVER_READ           0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */
1210 #define DRV_MSG_CODE_TRANSCEIVER_WRITE          0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */
1211 #define DRV_MSG_CODE_OCBB_DATA                  0x00180000 /* indicate OCBB related information */
1212 #define DRV_MSG_CODE_SET_BW                     0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */
1213 #define BW_MAX_MASK                             0x000000ff
1214 #define BW_MAX_OFFSET                           0
1215 #define BW_MIN_MASK                             0x0000ff00
1216 #define BW_MIN_OFFSET                           8
1217
1218 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */
1219 #define DRV_MSG_CODE_INDUCE_FAILURE             0x001b0000 /* param[0] - Simulate fan failure,  param[1] - simulate over temp. */
1220 #define DRV_MSG_FAN_FAILURE_TYPE                (1 << 0)
1221 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE        (1 << 1)
1222 #define DRV_MSG_CODE_GPIO_READ                  0x001c0000 /* Param: [0:15] - gpio number */
1223 #define DRV_MSG_CODE_GPIO_WRITE                 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */
1224 #define DRV_MSG_CODE_BIST_TEST                  0x001e0000      /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
1225 #define DRV_MSG_CODE_GET_TEMPERATURE            0x001f0000
1226 #define DRV_MSG_CODE_SET_LED_MODE               0x00200000 /* Set LED mode  params :0 operational, 1 LED turn ON, 2 LED turn OFF */
1227 #define DRV_MSG_CODE_TIMESTAMP                  0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */
1228 #define DRV_MSG_CODE_EMPTY_MB                   0x00220000 /* This is an empty mailbox just return OK*/
1229
1230 #define DRV_MSG_CODE_RESOURCE_CMD               0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */
1231
1232 #define RESOURCE_CMD_REQ_RESC_MASK              0x0000001F
1233 #define RESOURCE_CMD_REQ_RESC_OFFSET            0
1234 #define RESOURCE_CMD_REQ_OPCODE_MASK            0x000000E0
1235 #define RESOURCE_CMD_REQ_OPCODE_OFFSET          5
1236 #define RESOURCE_OPCODE_REQ                     1 /* request resource ownership with default aging */
1237 #define RESOURCE_OPCODE_REQ_WO_AGING            2 /* request resource ownership without aging */
1238 #define RESOURCE_OPCODE_REQ_W_AGING             3 /* request resource ownership with specific aging timer (in seconds) */
1239 #define RESOURCE_OPCODE_RELEASE                 4 /* release resource */
1240 #define RESOURCE_OPCODE_FORCE_RELEASE           5 /* force resource release */
1241 #define RESOURCE_CMD_REQ_AGE_MASK               0x0000FF00
1242 #define RESOURCE_CMD_REQ_AGE_OFFSET             8
1243
1244 #define RESOURCE_CMD_RSP_OWNER_MASK             0x000000FF
1245 #define RESOURCE_CMD_RSP_OWNER_OFFSET           0
1246 #define RESOURCE_CMD_RSP_OPCODE_MASK            0x00000700
1247 #define RESOURCE_CMD_RSP_OPCODE_OFFSET          8
1248 #define RESOURCE_OPCODE_GNT                     1 /* resource is free and granted to requester */
1249 #define RESOURCE_OPCODE_BUSY                    2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */
1250 #define RESOURCE_OPCODE_RELEASED                3 /* indicate release request was acknowledged */
1251 #define RESOURCE_OPCODE_RELEASED_PREVIOUS       4 /* indicate release request was previously received by other owner */
1252 #define RESOURCE_OPCODE_WRONG_OWNER             5 /* indicate wrong owner during release */
1253 #define RESOURCE_OPCODE_UNKNOWN_CMD             255
1254
1255 #define RESOURCE_DUMP                           0 /* dedicate resource 0 for dump */
1256
1257 #define DRV_MSG_CODE_GET_MBA_VERSION            0x00240000 /* Get MBA version */
1258 #define DRV_MSG_CODE_MDUMP_CMD                  0x00250000 /* Send crash dump commands with param[3:0] - opcode */
1259 #define MDUMP_DRV_PARAM_OPCODE_MASK             0x0000000f
1260 #define DRV_MSG_CODE_MDUMP_ACK                  0x01 /* acknowledge reception of error indication */
1261 #define DRV_MSG_CODE_MDUMP_SET_VALUES           0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */
1262 #define DRV_MSG_CODE_MDUMP_TRIGGER              0x03 /* trigger crash dump procedure */
1263 #define DRV_MSG_CODE_MDUMP_GET_CONFIG           0x04 /* Request valid logs and config words */
1264 #define DRV_MSG_CODE_MDUMP_SET_ENABLE           0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */
1265 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS           0x06 /* Clear all logs */
1266 #define DRV_MSG_CODE_MDUMP_GET_RETAIN           0x07 /* Get retained data */
1267 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN           0x08 /* Clear retain data */
1268 #define DRV_MSG_CODE_MEM_ECC_EVENTS             0x00260000 /* Param: None */
1269 #define DRV_MSG_CODE_GPIO_INFO                  0x00270000 /* Param: [0:15] - gpio number */
1270 #define DRV_MSG_CODE_EXT_PHY_READ               0x00280000 /* Value will be placed in union */
1271 #define DRV_MSG_CODE_EXT_PHY_WRITE              0x00290000 /* Value shoud be placed in union */
1272 #define DRV_MB_PARAM_ADDR_OFFSET                        0
1273 #define DRV_MB_PARAM_ADDR_MASK                  0x0000FFFF
1274 #define DRV_MB_PARAM_DEVAD_OFFSET               16
1275 #define DRV_MB_PARAM_DEVAD_MASK                 0x001F0000
1276 #define DRV_MB_PARAM_PORT_OFFSET                        21
1277 #define DRV_MB_PARAM_PORT_MASK                  0x00600000
1278 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE         0x002a0000
1279 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL       0x002b0000
1280 #define DRV_MSG_CODE_SET_LLDP_MAC                       0x002c0000
1281 #define DRV_MSG_CODE_GET_LLDP_MAC                       0x002d0000
1282 #define DRV_MSG_CODE_OS_WOL                                     0x002e0000
1283
1284 #define DRV_MSG_CODE_GET_TLV_DONE               0x002f0000 /* Param: None */
1285 #define DRV_MSG_CODE_FEATURE_SUPPORT            0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
1286 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT    0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_*  */
1287
1288 #define DRV_MSG_CODE_READ_WOL_REG                       0X00320000
1289 #define DRV_MSG_CODE_WRITE_WOL_REG                      0X00330000
1290 #define DRV_MSG_CODE_GET_WOL_BUFFER                     0X00340000
1291
1292 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
1293
1294         u32 drv_mb_param;
1295         /* UNLOAD_REQ params */
1296 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
1297 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
1298 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
1299 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
1300
1301         /* UNLOAD_DONE_params */
1302 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER        0x00000001
1303
1304         /* INIT_PHY params */
1305 #define DRV_MB_PARAM_INIT_PHY_FORCE             0x00000001
1306 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE         0x00000002
1307
1308         /* LLDP / DCBX params*/
1309 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
1310 #define DRV_MB_PARAM_LLDP_SEND_OFFSET           0
1311 #define DRV_MB_PARAM_LLDP_AGENT_MASK            0x00000006
1312 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET          1
1313 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x00000008
1314 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET         3
1315
1316 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK   0x000000FF
1317 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0
1318
1319 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW     0x1
1320 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE   0x2
1321
1322 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET          0
1323 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
1324 #define DRV_MB_PARAM_NVM_LEN_OFFSET             24
1325 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
1326
1327 #define DRV_MB_PARAM_PHY_ADDR_OFFSET            0
1328 #define DRV_MB_PARAM_PHY_ADDR_MASK              0x1FF0FFFF
1329 #define DRV_MB_PARAM_PHY_LANE_OFFSET            16
1330 #define DRV_MB_PARAM_PHY_LANE_MASK              0x000F0000
1331 #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET     29
1332 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK       0x20000000
1333 #define DRV_MB_PARAM_PHY_PORT_OFFSET            30
1334 #define DRV_MB_PARAM_PHY_PORT_MASK              0xc0000000
1335
1336 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET         0
1337 #define DRV_MB_PARAM_PHYMOD_LANE_MASK           0x000000FF
1338 #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET         8
1339 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK           0x000FFF00
1340         /* configure vf MSIX params BB */
1341 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET   0
1342 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK             0x000000FF
1343 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET  8
1344 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
1345         /* configure vf MSIX for PF params AH*/
1346 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET      0
1347 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK        0x000000FF
1348
1349         /* OneView configuration parametres */
1350 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET         0
1351 #define DRV_MB_PARAM_OV_CURR_CFG_MASK           0x0000000F
1352 #define DRV_MB_PARAM_OV_CURR_CFG_NONE           0
1353 #define DRV_MB_PARAM_OV_CURR_CFG_OS                     1
1354 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC    2
1355 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER          3
1356 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP         4
1357 #define DRV_MB_PARAM_OV_CURR_CFG_CNU            5
1358 #define DRV_MB_PARAM_OV_CURR_CFG_DCI            6
1359 #define DRV_MB_PARAM_OV_CURR_CFG_HII            7
1360
1361 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET                                 0
1362 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK                                   0x000000FF
1363 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE                                   (1 << 0)
1364 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED              (1 << 1)
1365 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS      (1 << 1)
1366 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND                  (1 << 2)
1367 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS             (1 << 3)
1368 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND                 (1 << 3)
1369 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT                (1 << 4)
1370 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED                 (1 << 5)
1371 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF                             (1 << 6)
1372 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED                                   0
1373
1374 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET      0
1375 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK                0x000000FF
1376
1377 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET             0
1378 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK                       0xFFFFFFFF
1379 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK         0xFF000000
1380 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK         0x00FF0000
1381 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK         0x0000FF00
1382 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK          0x000000FF
1383
1384 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET              0
1385 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK                0xF
1386 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN             0x1
1387 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED  0x2 /* Not Installed*/
1388 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING             0x3
1389 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED    0x4 /* installed but disabled by user/admin/OS */
1390 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE              0x5 /* installed and active */
1391
1392 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET         0
1393 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK           0xFFFFFFFF
1394
1395 #define DRV_MB_PARAM_WOL_MASK           (DRV_MB_PARAM_WOL_DEFAULT |     \
1396                                          DRV_MB_PARAM_WOL_DISABLED |    \
1397                                          DRV_MB_PARAM_WOL_ENABLED)
1398 #define DRV_MB_PARAM_WOL_DEFAULT        DRV_MB_PARAM_UNLOAD_WOL_MCP
1399 #define DRV_MB_PARAM_WOL_DISABLED       DRV_MB_PARAM_UNLOAD_WOL_DISABLED
1400 #define DRV_MB_PARAM_WOL_ENABLED        DRV_MB_PARAM_UNLOAD_WOL_ENABLED
1401
1402 #define DRV_MB_PARAM_ESWITCH_MODE_MASK  (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
1403                                          DRV_MB_PARAM_ESWITCH_MODE_VEB |   \
1404                                          DRV_MB_PARAM_ESWITCH_MODE_VEPA)
1405 #define DRV_MB_PARAM_ESWITCH_MODE_NONE  0x0
1406 #define DRV_MB_PARAM_ESWITCH_MODE_VEB   0x1
1407 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA  0x2
1408
1409 #define DRV_MB_PARAM_FCOE_CVID_MASK     0xFFF
1410 #define DRV_MB_PARAM_FCOE_CVID_OFFSET   0
1411
1412 #define DRV_MB_PARAM_SET_LED_MODE_OPER          0x0
1413 #define DRV_MB_PARAM_SET_LED_MODE_ON            0x1
1414 #define DRV_MB_PARAM_SET_LED_MODE_OFF           0x2
1415
1416 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET            0
1417 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK              0x00000003
1418 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET            2
1419 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK              0x000000FC
1420 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET     8
1421 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK       0x0000FF00
1422 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET          16
1423 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK            0xFFFF0000
1424
1425 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET         0
1426 #define DRV_MB_PARAM_GPIO_NUMBER_MASK           0x0000FFFF
1427 #define DRV_MB_PARAM_GPIO_VALUE_OFFSET          16
1428 #define DRV_MB_PARAM_GPIO_VALUE_MASK            0xFFFF0000
1429 #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET      16
1430 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK        0x00FF0000
1431 #define DRV_MB_PARAM_GPIO_CTRL_OFFSET           24
1432 #define DRV_MB_PARAM_GPIO_CTRL_MASK             0xFF000000
1433
1434         /* Resource Allocation params - Driver version support*/
1435 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK  0xFFFF0000
1436 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET                16
1437 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK  0x0000FFFF
1438 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET                0
1439
1440 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST          0
1441 #define DRV_MB_PARAM_BIST_REGISTER_TEST         1
1442 #define DRV_MB_PARAM_BIST_CLOCK_TEST            2
1443 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES           3
1444 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX       4
1445
1446 #define DRV_MB_PARAM_BIST_RC_UNKNOWN            0
1447 #define DRV_MB_PARAM_BIST_RC_PASSED             1
1448 #define DRV_MB_PARAM_BIST_RC_FAILED             2
1449 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER          3
1450
1451 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET      0
1452 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
1453 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET      8
1454 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK       0x0000FF00
1455
1456 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK      0x0000FFFF
1457 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET     0
1458 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */
1459 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE       0x00000002 /* driver supports EEE parameter */
1460 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK      0xFFFF0000
1461 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET     16
1462
1463         u32 fw_mb_header;
1464 #define FW_MSG_CODE_MASK                        0xffff0000
1465 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
1466 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
1467 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1468 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1469 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
1470 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1      0x10210000
1471 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
1472 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
1473 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
1474 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
1475 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1476 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
1477 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
1478 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
1479 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1480 #define FW_MSG_CODE_INIT_PHY_DONE               0x21200000
1481 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS   0x21300000
1482 #define FW_MSG_CODE_LINK_RESET_DONE             0x23000000
1483 #define FW_MSG_CODE_SET_LLDP_DONE               0x24000000
1484 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000
1485 #define FW_MSG_CODE_SET_DCBX_DONE               0x25000000
1486 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE        0x26000000
1487 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE         0x27000000
1488 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE   0x28000000
1489 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE    0x29000000
1490 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE    0x31000000
1491 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1492 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE  0x33000000
1493 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
1494 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
1495 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
1496 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR      0x37000000
1497 #define FW_MSG_CODE_UPDATE_WOL_DONE             0x38000000
1498 #define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE    0x39000000
1499 #define FW_MSG_CODE_UPDATE_ERR                  0x3a010000
1500 #define FW_MSG_CODE_UPDATE_PARAM_ERR            0x3a020000
1501 #define FW_MSG_CODE_UPDATE_NOT_ALLOWED          0x3a030000
1502 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE       0x3b000000
1503 #define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE       0x3c000000
1504 #define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE        0x3d000000
1505 #define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE        0x3e000000
1506 #define FW_MSG_CODE_RESET_TO_DEFAULT_ACK        0x3f000000
1507 #define FW_MSG_CODE_OV_GET_CURR_CFG_DONE        0x40000000
1508
1509 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
1510 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1511 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
1512 #define FW_MSG_CODE_FLR_ACK                     0x02000000
1513 #define FW_MSG_CODE_FLR_NACK                    0x02100000
1514 #define FW_MSG_CODE_SET_DRIVER_DONE             0x02200000
1515 #define FW_MSG_CODE_SET_VMAC_SUCCESS            0x02300000
1516 #define FW_MSG_CODE_SET_VMAC_FAIL               0x02400000
1517
1518 #define FW_MSG_CODE_NVM_OK                      0x00010000
1519 #define FW_MSG_CODE_NVM_INVALID_MODE            0x00020000
1520 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED       0x00030000
1521 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1522 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND       0x00050000
1523 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND          0x00060000
1524 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1525 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1526 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC     0x00090000
1527 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR     0x000a0000
1528 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE     0x000b0000
1529 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND          0x000c0000
1530 #define FW_MSG_CODE_NVM_OPERATION_FAILED        0x000d0000
1531 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED        0x000e0000
1532 #define FW_MSG_CODE_NVM_BAD_OFFSET              0x000f0000
1533 #define FW_MSG_CODE_NVM_BAD_SIGNATURE           0x00100000
1534 #define FW_MSG_CODE_NVM_FILE_READ_ONLY          0x00200000
1535 #define FW_MSG_CODE_NVM_UNKNOWN_FILE            0x00300000
1536 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK      0x00400000
1537 #define FW_MSG_CODE_MCP_RESET_REJECT            0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */
1538 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH        0x00310000
1539 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING      0x00320000
1540 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY      0x00330000
1541
1542 #define FW_MSG_CODE_PHY_OK                      0x00110000
1543 #define FW_MSG_CODE_PHY_ERROR                   0x00120000
1544 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR       0x00130000
1545 #define FW_MSG_CODE_SET_SECURE_MODE_OK          0x00140000
1546 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR         0x00150000
1547 #define FW_MSG_CODE_OK                          0x00160000
1548 #define FW_MSG_CODE_LED_MODE_INVALID            0x00170000
1549 #define FW_MSG_CODE_PHY_DIAG_OK                 0x00160000
1550 #define FW_MSG_CODE_PHY_DIAG_ERROR              0x00170000
1551 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE     0x00040000
1552 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE    0x00170000
1553 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1554 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE     0x000c0000
1555 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH     0x00100000
1556 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK         0x00160000
1557 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR      0x00170000
1558 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT     0x00020000
1559 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1560 #define FW_MSG_CODE_GPIO_OK                     0x00160000
1561 #define FW_MSG_CODE_GPIO_DIRECTION_ERR          0x00170000
1562 #define FW_MSG_CODE_GPIO_CTRL_ERR               0x00020000
1563 #define FW_MSG_CODE_GPIO_INVALID                0x000f0000
1564 #define FW_MSG_CODE_GPIO_INVALID_VALUE          0x00050000
1565 #define FW_MSG_CODE_BIST_TEST_INVALID           0x000f0000
1566 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000
1567 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE     0x00710000
1568 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED     0x00720000
1569 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED      0x00730000
1570 #define FW_MSG_CODE_RECOVERY_MODE               0x00740000
1571
1572         /* mdump related response codes */
1573 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND        0x00010000
1574 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED          0x00020000
1575 #define FW_MSG_CODE_MDUMP_INVALID_CMD           0x00030000
1576 #define FW_MSG_CODE_MDUMP_IN_PROGRESS           0x00040000
1577 #define FW_MSG_CODE_MDUMP_WRITE_FAILED          0x00050000
1578
1579 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
1580 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
1581
1582 #define FW_MSG_CODE_WOL_READ_WRITE_OK           0x00820000
1583 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL  0x00830000
1584 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000
1585 #define FW_MSG_CODE_WOL_READ_BUFFER_OK          0x00850000
1586 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000
1587
1588
1589 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE     0x00870000
1590 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
1591
1592 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1593
1594
1595         u32 fw_mb_param;
1596 /* Resource Allocation params - MFW version support */
1597 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK   0xFFFF0000
1598 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET         16
1599 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK   0x0000FFFF
1600 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET         0
1601
1602 /* get pf rdma protocol command response */
1603 #define FW_MB_PARAM_GET_PF_RDMA_NONE            0x0
1604 #define FW_MB_PARAM_GET_PF_RDMA_ROCE            0x1
1605 #define FW_MB_PARAM_GET_PF_RDMA_IWARP           0x2
1606 #define FW_MB_PARAM_GET_PF_RDMA_BOTH            0x3
1607
1608 /* get MFW feature support response */
1609 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001 /* MFW supports SmartLinQ */
1610 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002 /* MFW supports EEE */
1611
1612 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR   (1<<0)
1613
1614         u32 drv_pulse_mb;
1615 #define DRV_PULSE_SEQ_MASK                      0x00007fff
1616 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1617         /*
1618          * The system time is in the format of
1619          * (year-2001)*12*32 + month*32 + day.
1620          */
1621 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1622         /*
1623          * Indicate to the firmware not to go into the
1624          * OS-absent when it is not getting driver pulse.
1625          * This is used for debugging as well for PXE(MBA).
1626          */
1627
1628         u32 mcp_pulse_mb;
1629 #define MCP_PULSE_SEQ_MASK                      0x00007fff
1630 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1631         /* Indicates to the driver not to assert due to lack
1632          * of MCP response */
1633 #define MCP_EVENT_MASK                          0xffff0000
1634 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1635
1636         /* The union data is used by the driver to pass parameters to the scratchpad. */
1637         union drv_union_data union_data;
1638
1639 };
1640
1641 /* MFW - DRV MB */
1642 /**********************************************************************
1643  * Description
1644  *   Incremental Aggregative
1645  *   8-bit MFW counter per message
1646  *   8-bit ack-counter per message
1647  * Capabilities
1648  *   Provides up to 256 aggregative message per type
1649  *   Provides 4 message types in dword
1650  *   Message type pointers to byte offset
1651  *   Backward Compatibility by using sizeof for the counters.
1652  *   No lock requires for 32bit messages
1653  * Limitations:
1654  * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1655  * is required to prevent data corruption.
1656  **********************************************************************/
1657 enum MFW_DRV_MSG_TYPE {
1658         MFW_DRV_MSG_LINK_CHANGE,
1659         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1660         MFW_DRV_MSG_VF_DISABLED,
1661         MFW_DRV_MSG_LLDP_DATA_UPDATED,
1662         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1663         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1664         MFW_DRV_MSG_ERROR_RECOVERY,
1665         MFW_DRV_MSG_BW_UPDATE,
1666         MFW_DRV_MSG_S_TAG_UPDATE,
1667         MFW_DRV_MSG_GET_LAN_STATS,
1668         MFW_DRV_MSG_GET_FCOE_STATS,
1669         MFW_DRV_MSG_GET_ISCSI_STATS,
1670         MFW_DRV_MSG_GET_RDMA_STATS,
1671         MFW_DRV_MSG_FAILURE_DETECTED,
1672         MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1673         MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1674         MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE,
1675         MFW_DRV_MSG_GET_TLV_REQ,
1676         MFW_DRV_MSG_MAX
1677 };
1678
1679 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
1680 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
1681 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
1682 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1683
1684 #ifdef BIG_ENDIAN               /* Like MFW */
1685 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++;
1686 #else
1687 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;
1688 #endif
1689
1690 #define MFW_DRV_UPDATE(shmem_func, msg_id)      (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++;
1691
1692 struct public_mfw_mb {
1693         u32 sup_msgs;       /* Assigend with MFW_DRV_MSG_MAX */
1694         u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];   /* Incremented by the MFW */
1695         u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];   /* Incremented by the driver */
1696 };
1697
1698 /**************************************/
1699 /*                                    */
1700 /*     P U B L I C       D A T A      */
1701 /*                                    */
1702 /**************************************/
1703 enum public_sections {
1704         PUBLIC_DRV_MB,      /* Points to the first drv_mb of path0 */
1705         PUBLIC_MFW_MB,      /* Points to the first mfw_mb of path0 */
1706         PUBLIC_GLOBAL,
1707         PUBLIC_PATH,
1708         PUBLIC_PORT,
1709         PUBLIC_FUNC,
1710         PUBLIC_MAX_SECTIONS
1711 };
1712
1713 struct drv_ver_info_stc {
1714         u32 ver;
1715         u8 name[32];
1716 };
1717
1718 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1719  * Please make sure data does not exceed this size.
1720  */
1721 #define NUM_RUNTIME_DWORDS 16
1722 struct drv_init_hw_stc {
1723         u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1724         u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1725 };
1726
1727 struct mcp_public_data {
1728         /* The sections fields is an array */
1729         u32 num_sections;
1730         offsize_t sections[PUBLIC_MAX_SECTIONS];
1731         struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1732         struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1733         struct public_global global;
1734         struct public_path path[MCP_GLOB_PATH_MAX];
1735         struct public_port port[MCP_GLOB_PORT_MAX];
1736         struct public_func func[MCP_GLOB_FUNC_MAX];
1737 };
1738
1739 #define I2C_TRANSCEIVER_ADDR    0xa0
1740 #define MAX_I2C_TRANSACTION_SIZE        16
1741 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE   256
1742
1743 /* OCBB definitions */
1744 enum tlvs {
1745         /* Category 1: Device Properties */
1746         DRV_TLV_CLP_STR,
1747         DRV_TLV_CLP_STR_CTD,
1748         /* Category 6: Device Configuration */
1749         DRV_TLV_SCSI_TO,
1750         DRV_TLV_R_T_TOV,
1751         DRV_TLV_R_A_TOV,
1752         DRV_TLV_E_D_TOV,
1753         DRV_TLV_CR_TOV,
1754         DRV_TLV_BOOT_TYPE,
1755         /* Category 8: Port Configuration */
1756         DRV_TLV_NPIV_ENABLED,
1757         /* Category 10: Function Configuration */
1758         DRV_TLV_FEATURE_FLAGS,
1759         DRV_TLV_LOCAL_ADMIN_ADDR,
1760         DRV_TLV_ADDITIONAL_MAC_ADDR_1,
1761         DRV_TLV_ADDITIONAL_MAC_ADDR_2,
1762         DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
1763         DRV_TLV_LSO_MIN_SEGMENT_COUNT,
1764         DRV_TLV_PROMISCUOUS_MODE,
1765         DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
1766         DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
1767         DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
1768         DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
1769         DRV_TLV_OS_DRIVER_STATES,
1770         DRV_TLV_PXE_BOOT_PROGRESS,
1771         /* Category 12: FC/FCoE Configuration */
1772         DRV_TLV_NPIV_STATE,
1773         DRV_TLV_NUM_OF_NPIV_IDS,
1774         DRV_TLV_SWITCH_NAME,
1775         DRV_TLV_SWITCH_PORT_NUM,
1776         DRV_TLV_SWITCH_PORT_ID,
1777         DRV_TLV_VENDOR_NAME,
1778         DRV_TLV_SWITCH_MODEL,
1779         DRV_TLV_SWITCH_FW_VER,
1780         DRV_TLV_QOS_PRIORITY_PER_802_1P,
1781         DRV_TLV_PORT_ALIAS,
1782         DRV_TLV_PORT_STATE,
1783         DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
1784         DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
1785         DRV_TLV_LINK_FAILURE_COUNT,
1786         DRV_TLV_FCOE_BOOT_PROGRESS,
1787         /* Category 13: iSCSI Configuration */
1788         DRV_TLV_TARGET_LLMNR_ENABLED,
1789         DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
1790         DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
1791         DRV_TLV_AUTHENTICATION_METHOD,
1792         DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
1793         DRV_TLV_MAX_FRAME_SIZE,
1794         DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
1795         DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
1796         DRV_TLV_ISCSI_BOOT_PROGRESS,
1797         /* Category 20: Device Data */
1798         DRV_TLV_PCIE_BUS_RX_UTILIZATION,
1799         DRV_TLV_PCIE_BUS_TX_UTILIZATION,
1800         DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
1801         DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
1802         DRV_TLV_NCSI_RX_BYTES_RECEIVED,
1803         DRV_TLV_NCSI_TX_BYTES_SENT,
1804         /* Category 22: Base Port Data */
1805         DRV_TLV_RX_DISCARDS,
1806         DRV_TLV_RX_ERRORS,
1807         DRV_TLV_TX_ERRORS,
1808         DRV_TLV_TX_DISCARDS,
1809         DRV_TLV_RX_FRAMES_RECEIVED,
1810         DRV_TLV_TX_FRAMES_SENT,
1811         /* Category 23: FC/FCoE Port Data */
1812         DRV_TLV_RX_BROADCAST_PACKETS,
1813         DRV_TLV_TX_BROADCAST_PACKETS,
1814         /* Category 28: Base Function Data */
1815         DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
1816         DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
1817         DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1818         DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1819         DRV_TLV_PF_RX_FRAMES_RECEIVED,
1820         DRV_TLV_RX_BYTES_RECEIVED,
1821         DRV_TLV_PF_TX_FRAMES_SENT,
1822         DRV_TLV_TX_BYTES_SENT,
1823         DRV_TLV_IOV_OFFLOAD,
1824         DRV_TLV_PCI_ERRORS_CAP_ID,
1825         DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
1826         DRV_TLV_UNCORRECTABLE_ERROR_MASK,
1827         DRV_TLV_CORRECTABLE_ERROR_STATUS,
1828         DRV_TLV_CORRECTABLE_ERROR_MASK,
1829         DRV_TLV_PCI_ERRORS_AECC_REGISTER,
1830         DRV_TLV_TX_QUEUES_EMPTY,
1831         DRV_TLV_RX_QUEUES_EMPTY,
1832         DRV_TLV_TX_QUEUES_FULL,
1833         DRV_TLV_RX_QUEUES_FULL,
1834         /* Category 29: FC/FCoE Function Data */
1835         DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1836         DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1837         DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
1838         DRV_TLV_FCOE_RX_BYTES_RECEIVED,
1839         DRV_TLV_FCOE_TX_FRAMES_SENT,
1840         DRV_TLV_FCOE_TX_BYTES_SENT,
1841         DRV_TLV_CRC_ERROR_COUNT,
1842         DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
1843         DRV_TLV_CRC_ERROR_1_TIMESTAMP,
1844         DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
1845         DRV_TLV_CRC_ERROR_2_TIMESTAMP,
1846         DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
1847         DRV_TLV_CRC_ERROR_3_TIMESTAMP,
1848         DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
1849         DRV_TLV_CRC_ERROR_4_TIMESTAMP,
1850         DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
1851         DRV_TLV_CRC_ERROR_5_TIMESTAMP,
1852         DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
1853         DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
1854         DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
1855         DRV_TLV_DISPARITY_ERROR_COUNT,
1856         DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
1857         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
1858         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
1859         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
1860         DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
1861         DRV_TLV_LAST_FLOGI_TIMESTAMP,
1862         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
1863         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
1864         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
1865         DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
1866         DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
1867         DRV_TLV_LAST_FLOGI_RJT,
1868         DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
1869         DRV_TLV_FDISCS_SENT_COUNT,
1870         DRV_TLV_FDISC_ACCS_RECEIVED,
1871         DRV_TLV_FDISC_RJTS_RECEIVED,
1872         DRV_TLV_PLOGI_SENT_COUNT,
1873         DRV_TLV_PLOGI_ACCS_RECEIVED,
1874         DRV_TLV_PLOGI_RJTS_RECEIVED,
1875         DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
1876         DRV_TLV_PLOGI_1_TIMESTAMP,
1877         DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
1878         DRV_TLV_PLOGI_2_TIMESTAMP,
1879         DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
1880         DRV_TLV_PLOGI_3_TIMESTAMP,
1881         DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
1882         DRV_TLV_PLOGI_4_TIMESTAMP,
1883         DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
1884         DRV_TLV_PLOGI_5_TIMESTAMP,
1885         DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
1886         DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
1887         DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
1888         DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
1889         DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
1890         DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
1891         DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
1892         DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
1893         DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
1894         DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
1895         DRV_TLV_LOGOS_ISSUED,
1896         DRV_TLV_LOGO_ACCS_RECEIVED,
1897         DRV_TLV_LOGO_RJTS_RECEIVED,
1898         DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
1899         DRV_TLV_LOGO_1_TIMESTAMP,
1900         DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
1901         DRV_TLV_LOGO_2_TIMESTAMP,
1902         DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
1903         DRV_TLV_LOGO_3_TIMESTAMP,
1904         DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
1905         DRV_TLV_LOGO_4_TIMESTAMP,
1906         DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
1907         DRV_TLV_LOGO_5_TIMESTAMP,
1908         DRV_TLV_LOGOS_RECEIVED,
1909         DRV_TLV_ACCS_ISSUED,
1910         DRV_TLV_PRLIS_ISSUED,
1911         DRV_TLV_ACCS_RECEIVED,
1912         DRV_TLV_ABTS_SENT_COUNT,
1913         DRV_TLV_ABTS_ACCS_RECEIVED,
1914         DRV_TLV_ABTS_RJTS_RECEIVED,
1915         DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
1916         DRV_TLV_ABTS_1_TIMESTAMP,
1917         DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
1918         DRV_TLV_ABTS_2_TIMESTAMP,
1919         DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
1920         DRV_TLV_ABTS_3_TIMESTAMP,
1921         DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
1922         DRV_TLV_ABTS_4_TIMESTAMP,
1923         DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
1924         DRV_TLV_ABTS_5_TIMESTAMP,
1925         DRV_TLV_RSCNS_RECEIVED,
1926         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
1927         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
1928         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
1929         DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
1930         DRV_TLV_LUN_RESETS_ISSUED,
1931         DRV_TLV_ABORT_TASK_SETS_ISSUED,
1932         DRV_TLV_TPRLOS_SENT,
1933         DRV_TLV_NOS_SENT_COUNT,
1934         DRV_TLV_NOS_RECEIVED_COUNT,
1935         DRV_TLV_OLS_COUNT,
1936         DRV_TLV_LR_COUNT,
1937         DRV_TLV_LRR_COUNT,
1938         DRV_TLV_LIP_SENT_COUNT,
1939         DRV_TLV_LIP_RECEIVED_COUNT,
1940         DRV_TLV_EOFA_COUNT,
1941         DRV_TLV_EOFNI_COUNT,
1942         DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
1943         DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
1944         DRV_TLV_SCSI_STATUS_BUSY_COUNT,
1945         DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
1946         DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
1947         DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
1948         DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
1949         DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
1950         DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
1951         DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
1952         DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
1953         DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
1954         DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
1955         DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
1956         DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
1957         DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
1958         DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
1959         DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
1960         DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
1961         /* Category 30: iSCSI Function Data */
1962         DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1963         DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1964         DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
1965         DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
1966         DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
1967         DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
1968 };
1969
1970 #endif                          /* MCP_PUBLIC_H */