2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 /****************************************************************************
35 * Description: MCP public data
37 * Created: 13/01/2013 yanivr
39 ****************************************************************************/
44 #define VF_MAX_STATIC 192 /* In case of AH */
46 #define MCP_GLOB_PATH_MAX 2
47 #define MCP_PORT_MAX 2 /* Global */
48 #define MCP_GLOB_PORT_MAX 4 /* Global */
49 #define MCP_GLOB_FUNC_MAX 16 /* Global */
51 typedef u32 offsize_t; /* In DWORDS !!! */
52 /* Offset from the beginning of the MCP scratchpad */
53 #define OFFSIZE_OFFSET_OFFSET 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 /* Size of specific element (not the whole array if any) */
56 #define OFFSIZE_SIZE_OFFSET 16
57 #define OFFSIZE_SIZE_MASK 0xffff0000
59 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
60 #define SECTION_OFFSET(_offsize) ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2))
62 /* SECTION_SIZE is calculating the size in bytes out of offsize */
63 #define SECTION_SIZE(_offsize) (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2)
65 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */
66 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
68 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */
69 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
70 /* PHY configuration */
72 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
73 #define ETH_SPEED_AUTONEG 0
74 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
76 u32 pause; /* bitmask */
77 #define ETH_PAUSE_NONE 0x0
78 #define ETH_PAUSE_AUTONEG 0x1
79 #define ETH_PAUSE_RX 0x2
80 #define ETH_PAUSE_TX 0x4
82 u32 adv_speed; /* Default should be the speed_cap_mask */
84 #define ETH_LOOPBACK_NONE (0)
85 #define ETH_LOOPBACK_INT_PHY (1) /* Serdes loopback. In AH, it refers to Near End */
86 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */
87 #define ETH_LOOPBACK_EXT (3) /* External Loopback (Require loopback plug) */
88 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */
89 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */
90 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */
91 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */
92 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */
93 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */
96 #define EEE_CFG_EEE_ENABLED (1<<0) /* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */
97 #define EEE_CFG_TX_LPI (1<<1)
98 #define EEE_CFG_ADV_SPEED_1G (1<<2)
99 #define EEE_CFG_ADV_SPEED_10G (1<<3)
100 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
101 #define EEE_TX_TIMER_USEC_OFFSET 4
102 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
103 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
104 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
106 u32 link_modes; /* Additional link modes */
107 #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */
112 u32 dynamic_cfg; /* device control channel */
113 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
114 #define PORT_MF_CFG_OV_TAG_OFFSET 0
115 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
120 /* DO NOT add new fields in the middle
121 * MUST be synced with struct pmm_stats_map
124 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
125 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
126 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
127 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
128 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
129 u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
132 u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
133 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
134 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
135 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
136 u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
141 u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/
147 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
148 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
149 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
150 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
151 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
152 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
153 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
154 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
155 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
156 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
157 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
158 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
159 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
160 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
161 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
162 u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
165 u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
166 u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
167 u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
168 u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
171 u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */
177 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
178 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
181 u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
182 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
189 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
190 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
191 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
192 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
193 u64 rxpok; /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
194 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
195 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
196 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
197 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
198 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
199 /* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */
208 struct brb_stats brb;
209 struct eth_stats eth;
212 /*-----+-----------------------------------------------------------------------------
213 * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
214 * | rate of physical | team #1 | team #2 |are used|per path | (paths) enabled
216 *======+==================+=========+=========+========+==========+=================
217 * BB | 1x100G | This is special mode, where there are actually 2 HW func
218 * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1
219 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
220 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
221 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional)
222 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional)
223 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional)
224 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
225 * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA
226 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
227 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
228 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
229 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
230 *======+==================+=========+=========+========+==========+===================
235 #define CMT_TEAM_MAX 2
237 struct couple_mode_teaming {
238 u8 port_cmt[MCP_GLOB_PORT_MAX];
239 #define PORT_CMT_IN_TEAM (1<<0)
241 #define PORT_CMT_PORT_ROLE (1<<1)
242 #define PORT_CMT_PORT_INACTIVE (0<<1)
243 #define PORT_CMT_PORT_ACTIVE (1<<1)
245 #define PORT_CMT_TEAM_MASK (1<<2)
246 #define PORT_CMT_TEAM0 (0<<2)
247 #define PORT_CMT_TEAM1 (1<<2)
250 /**************************************
251 * LLDP and DCBX HSI structures
252 **************************************/
253 #define LLDP_CHASSIS_ID_STAT_LEN 4
254 #define LLDP_PORT_ID_STAT_LEN 4
255 #define DCBX_MAX_APP_PROTOCOL 32
256 #define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/
257 #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/
258 typedef enum _lldp_agent_e {
259 LLDP_NEAREST_BRIDGE = 0,
260 LLDP_NEAREST_NON_TPMR_BRIDGE,
261 LLDP_NEAREST_CUSTOMER_BRIDGE,
265 struct lldp_config_params_s {
267 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
268 #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0
269 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
270 #define LLDP_CONFIG_HOLD_OFFSET 8
271 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
272 #define LLDP_CONFIG_MAX_CREDIT_OFFSET 12
273 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
274 #define LLDP_CONFIG_ENABLE_RX_OFFSET 30
275 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
276 #define LLDP_CONFIG_ENABLE_TX_OFFSET 31
277 /* Holds local Chassis ID TLV header, subtype and 9B of payload.
278 If firtst byte is 0, then we will use default chassis ID */
279 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
280 /* Holds local Port ID TLV header, subtype and 9B of payload.
281 If firtst byte is 0, then we will use default port ID */
282 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
285 struct lldp_status_params_s {
287 u32 status; /* TBD */
288 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
289 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
290 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
291 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
295 struct dcbx_ets_feature {
297 #define DCBX_ETS_ENABLED_MASK 0x00000001
298 #define DCBX_ETS_ENABLED_OFFSET 0
299 #define DCBX_ETS_WILLING_MASK 0x00000002
300 #define DCBX_ETS_WILLING_OFFSET 1
301 #define DCBX_ETS_ERROR_MASK 0x00000004
302 #define DCBX_ETS_ERROR_OFFSET 2
303 #define DCBX_ETS_CBS_MASK 0x00000008
304 #define DCBX_ETS_CBS_OFFSET 3
305 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
306 #define DCBX_ETS_MAX_TCS_OFFSET 4
307 #define DCBX_OOO_TC_MASK 0x00000f00
308 #define DCBX_OOO_TC_OFFSET 8
309 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
311 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */
312 #define DCBX_TCP_OOO_TC (4)
313 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
315 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
316 #define DCBX_CEE_STRICT_PRIORITY 0xf
317 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
319 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
321 #define DCBX_ETS_TSA_STRICT 0
322 #define DCBX_ETS_TSA_CBS 1
323 #define DCBX_ETS_TSA_ETS 2
326 struct dcbx_app_priority_entry {
328 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
329 #define DCBX_APP_PRI_MAP_OFFSET 0
330 #define DCBX_APP_PRI_0 0x01
331 #define DCBX_APP_PRI_1 0x02
332 #define DCBX_APP_PRI_2 0x04
333 #define DCBX_APP_PRI_3 0x08
334 #define DCBX_APP_PRI_4 0x10
335 #define DCBX_APP_PRI_5 0x20
336 #define DCBX_APP_PRI_6 0x40
337 #define DCBX_APP_PRI_7 0x80
338 #define DCBX_APP_SF_MASK 0x00000300
339 #define DCBX_APP_SF_OFFSET 8
340 #define DCBX_APP_SF_ETHTYPE 0
341 #define DCBX_APP_SF_PORT 1
342 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
343 #define DCBX_APP_SF_IEEE_OFFSET 12
344 #define DCBX_APP_SF_IEEE_RESERVED 0
345 #define DCBX_APP_SF_IEEE_ETHTYPE 1
346 #define DCBX_APP_SF_IEEE_TCP_PORT 2
347 #define DCBX_APP_SF_IEEE_UDP_PORT 3
348 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
350 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
351 #define DCBX_APP_PROTOCOL_ID_OFFSET 16
355 /* FW structure in BE */
356 struct dcbx_app_priority_feature {
358 #define DCBX_APP_ENABLED_MASK 0x00000001
359 #define DCBX_APP_ENABLED_OFFSET 0
360 #define DCBX_APP_WILLING_MASK 0x00000002
361 #define DCBX_APP_WILLING_OFFSET 1
362 #define DCBX_APP_ERROR_MASK 0x00000004
363 #define DCBX_APP_ERROR_OFFSET 2
365 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
366 #define DCBX_APP_DEFAULT_PRI_OFFSET 8
368 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
369 #define DCBX_APP_MAX_TCS_OFFSET 12
370 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
371 #define DCBX_APP_NUM_ENTRIES_OFFSET 16
372 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
375 /* FW structure in BE */
376 struct dcbx_features {
378 struct dcbx_ets_feature ets;
381 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
382 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0
383 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
384 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
385 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
386 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
387 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
388 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
389 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
390 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
392 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
393 #define DCBX_PFC_FLAGS_OFFSET 8
394 #define DCBX_PFC_CAPS_MASK 0x00000f00
395 #define DCBX_PFC_CAPS_OFFSET 8
396 #define DCBX_PFC_MBC_MASK 0x00004000
397 #define DCBX_PFC_MBC_OFFSET 14
398 #define DCBX_PFC_WILLING_MASK 0x00008000
399 #define DCBX_PFC_WILLING_OFFSET 15
400 #define DCBX_PFC_ENABLED_MASK 0x00010000
401 #define DCBX_PFC_ENABLED_OFFSET 16
402 #define DCBX_PFC_ERROR_MASK 0x00020000
403 #define DCBX_PFC_ERROR_OFFSET 17
406 struct dcbx_app_priority_feature app;
409 struct dcbx_local_params {
411 #define DCBX_CONFIG_VERSION_MASK 0x00000007
412 #define DCBX_CONFIG_VERSION_OFFSET 0
413 #define DCBX_CONFIG_VERSION_DISABLED 0
414 #define DCBX_CONFIG_VERSION_IEEE 1
415 #define DCBX_CONFIG_VERSION_CEE 2
416 #define DCBX_CONFIG_VERSION_DYNAMIC (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE)
417 #define DCBX_CONFIG_VERSION_STATIC 4
420 struct dcbx_features features;
427 #define DCBX_CONFIG_VERSION_MASK 0x00000007
428 #define DCBX_CONFIG_VERSION_OFFSET 0
429 #define DCBX_CONFIG_VERSION_DISABLED 0
430 #define DCBX_CONFIG_VERSION_IEEE 1
431 #define DCBX_CONFIG_VERSION_CEE 2
432 #define DCBX_CONFIG_VERSION_STATIC 4
434 struct dcbx_features features;
438 struct lldp_system_tlvs_buffer_s {
440 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1
441 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0
442 /* This bit defines if system TLVs are instead of mandatory TLVS or in
443 * addition to them. Set 1 for replacing mandatory TLVs
445 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2
446 #define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1
447 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000
448 #define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16
449 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
452 /* Since this struct is written by MFW and read by driver need to add
453 * sequence guards (as in case of DCBX MIB)
455 struct lldp_received_tlvs_s {
458 u32 tlvs_buffer[MAX_TLV_BUFFER];
462 struct dcb_dscp_map {
464 #define DCB_DSCP_ENABLE_MASK 0x1
465 #define DCB_DSCP_ENABLE_OFFSET 0
466 #define DCB_DSCP_ENABLE 1
468 /* the map structure is the following:
469 each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp
470 Lowest dscp is at lsb
471 31 28 24 20 16 12 8 4 0
472 dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri |
473 dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri |
482 /* generic_idc_msg_t to be used for inter driver communication.
483 * source_pf specifies the originating PF that sent messages to all target PFs
484 * msg contains 64 bit value of the message - opaque to the MFW
486 struct generic_idc_msg_s {
488 struct mcp_val64 msg;
491 /**************************************
492 * Attributes commands
493 **************************************/
495 enum _attribute_commands_e {
496 ATTRIBUTE_CMD_READ = 0,
498 ATTRIBUTE_CMD_READ_CLEAR,
500 ATTRIBUTE_NUM_OF_COMMANDS
503 /**************************************/
505 /* P U B L I C G L O B A L */
507 /**************************************/
508 struct public_global {
509 u32 max_path; /* 32bit is wasty, but this will be used often */
510 u32 max_ports; /* (Global) 32bit is wasty, but this will be used often */
511 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
516 u32 phymod_dbg_mb_offset;
517 struct couple_mode_teaming cmt;
518 s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */
520 u32 running_bundle_id;
521 s32 external_temperature;
523 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0)
524 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1)
525 #define MDUMP_REASON_DUMP_AGED (1 << 2)
526 u32 ext_phy_upgrade_fw;
527 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff)
528 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0)
529 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1)
530 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2)
531 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3)
532 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000)
533 #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16)
535 u8 runtime_port_swap_map[MODE_4P];
540 /**************************************/
542 /* P U B L I C P A T H */
544 /**************************************/
546 /****************************************************************************
547 * Shared Memory 2 Region *
548 ****************************************************************************/
549 /* The fw_flr_ack is actually built in the following way: */
551 /* 128 bit: VF ack */
552 /* 8 bit: ios_dis_ack */
553 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
554 /* u32. The fw must have the VF right after the PF since this is how it */
555 /* access arrays(it expects always the VF to reside after the PF, and that */
556 /* makes the calculation much easier for it. ) */
557 /* In order to answer both limitations, and keep the struct small, the code */
558 /* will abuse the structure defined here to achieve the actual partition */
560 /****************************************************************************/
564 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
565 #define ACCUM_ACK_PF_BASE 0
566 #define ACCUM_ACK_PF_SHIFT 0
568 #define ACCUM_ACK_VF_BASE 8
569 #define ACCUM_ACK_VF_SHIFT 3
571 #define ACCUM_ACK_IOV_DIS_BASE 256
572 #define ACCUM_ACK_IOV_DIS_SHIFT 8
577 struct fw_flr_mb flr_mb;
579 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
580 * which were disabled/flred
582 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
584 u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */
585 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
586 #define PROCESS_KILL_COUNTER_OFFSET 0
587 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
588 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16
589 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit)
592 /**************************************/
594 /* P U B L I C P O R T */
596 /**************************************/
597 #define FC_NPIV_WWPN_SIZE 8
598 #define FC_NPIV_WWNN_SIZE 8
599 struct dci_npiv_settings {
600 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
601 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
604 struct dci_fc_npiv_cfg {
605 /* hdr used internally by the MFW */
610 #define MAX_NUMBER_NPIV 64
611 struct dci_fc_npiv_tbl {
612 struct dci_fc_npiv_cfg fc_npiv_cfg;
613 struct dci_npiv_settings settings[MAX_NUMBER_NPIV];
616 /****************************************************************************
617 * Driver <-> FW Mailbox *
618 ****************************************************************************/
621 u32 validity_map; /* 0x0 (4*2 = 0x8) */
624 #define MCP_VALIDITY_PCI_CFG 0x00100000
625 #define MCP_VALIDITY_MB 0x00200000
626 #define MCP_VALIDITY_DEV_INFO 0x00400000
627 #define MCP_VALIDITY_RESERVED 0x00000007
629 /* One licensing bit should be set */
630 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd ? license */
631 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
632 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
633 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
636 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
637 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
638 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
639 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
642 #define LINK_STATUS_LINK_UP 0x00000001
643 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
644 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1<<1)
645 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2<<1)
646 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3<<1)
647 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4<<1)
648 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5<<1)
649 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6<<1)
650 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7<<1)
651 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8<<1)
652 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
653 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
654 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
655 #define LINK_STATUS_PFC_ENABLED 0x00000100
656 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
657 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
658 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
659 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
660 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
661 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
662 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
663 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
664 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
665 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
666 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
667 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
668 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
669 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
670 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
671 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
672 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
673 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
674 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
675 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
676 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
677 #define LINK_STATUS_FEC_MODE_NONE (0<<27)
678 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1<<27)
679 #define LINK_STATUS_FEC_MODE_RS_CL91 (2<<27)
680 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000
683 #define LP_PRESENCE_STATUS_OFFSET 0
684 #define LP_PRESENCE_STATUS_MASK 0x3
685 #define LP_PRESENCE_UNKNOWN 0x0
686 #define LP_PRESENCE_PROBING 0x1
687 #define LP_PRESENT 0x2
688 #define LP_NOT_PRESENT 0x3
690 u32 ext_phy_fw_version;
691 u32 drv_phy_cfg_addr; /* Points to struct eth_phy_cfg (For READ-ONLY) */
697 struct port_mf_cfg port_mf_config;
698 struct port_stats stats;
701 #define MEDIA_UNSPECIFIED 0x0
702 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */
703 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */
704 #define MEDIA_DA_TWINAX 0x3
705 #define MEDIA_BASE_T 0x4
706 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */
707 #define MEDIA_MODULE_FIBER 0x6
708 #define MEDIA_KR 0xf0
709 #define MEDIA_NOT_PRESENT 0xff
712 #define LFA_LINK_FLAP_REASON_OFFSET 0
713 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
714 #define LFA_NO_REASON (0<<0)
715 #define LFA_LINK_DOWN (1<<0)
716 #define LFA_FORCE_INIT (1<<1)
717 #define LFA_LOOPBACK_MISMATCH (1<<2)
718 #define LFA_SPEED_MISMATCH (1<<3)
719 #define LFA_FLOW_CTRL_MISMATCH (1<<4)
720 #define LFA_ADV_SPEED_MISMATCH (1<<5)
721 #define LFA_EEE_MISMATCH (1<<6)
722 #define LFA_LINK_MODES_MISMATCH (1<<7)
723 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
724 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
725 #define LINK_FLAP_COUNT_OFFSET 16
726 #define LINK_FLAP_COUNT_MASK 0x00ff0000
728 u32 link_change_count;
731 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; // offset: 536 bytes?
732 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
733 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
735 /* DCBX related MIB */
736 struct dcbx_local_params local_admin_dcbx_mib;
737 struct dcbx_mib remote_dcbx_mib;
738 struct dcbx_mib operational_dcbx_mib;
740 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
741 u32 fc_npiv_nvram_tbl_addr;
742 #define NPIV_TBL_INVALID_ADDR 0xFFFFFFFF
744 u32 fc_npiv_nvram_tbl_size;
745 u32 transceiver_data;
746 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
747 #define ETH_TRANSCEIVER_STATE_OFFSET 0x0
748 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00
749 #define ETH_TRANSCEIVER_STATE_PRESENT 0x01
750 #define ETH_TRANSCEIVER_STATE_VALID 0x03
751 #define ETH_TRANSCEIVER_STATE_UPDATING 0x08
752 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
753 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
754 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
755 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF
756 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */
757 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */
758 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
759 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
760 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
761 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
762 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
763 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
764 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */
765 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */
766 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
767 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
768 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
769 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
770 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */
771 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
772 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
773 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
774 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */
775 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
776 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
777 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 /* 25G Passive copper cable - short */
778 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 /* 25G Active copper cable - short */
779 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 /* 25G Passive copper cable - medium */
780 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 /* 25G Active copper cable - medium */
781 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a /* 25G Passive copper cable - long */
782 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b /* 25G Active copper cable - long */
783 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
784 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
785 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
786 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
787 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
788 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
789 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
790 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
791 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
792 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
793 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
794 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
795 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
796 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
800 struct dcb_dscp_map dcb_dscp_map;
803 #define EEE_ACTIVE_BIT (1<<0) /* Set when EEE negotiation is complete. */
805 #define EEE_LD_ADV_STATUS_MASK 0x000000f0 /* Shows the Local Device EEE capabilities */
806 #define EEE_LD_ADV_STATUS_OFFSET 4
807 #define EEE_1G_ADV (1<<1)
808 #define EEE_10G_ADV (1<<2)
809 #define EEE_LP_ADV_STATUS_MASK 0x00000f00 /* Same values as in EEE_LD_ADV, but for Link Parter */
810 #define EEE_LP_ADV_STATUS_OFFSET 8
812 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 /* Supported speeds for EEE */
813 #define EEE_SUPPORTED_SPEED_OFFSET 12
814 #define EEE_1G_SUPPORTED (1 << 1)
815 #define EEE_10G_SUPPORTED (1 << 2)
817 u32 eee_remote; /* Used for EEE in LLDP */
818 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
819 #define EEE_REMOTE_TW_TX_OFFSET 0
820 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
821 #define EEE_REMOTE_TW_RX_OFFSET 16
824 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF
825 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0
826 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2)
827 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3)
828 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4)
829 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5)
830 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6)
831 #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00
832 #define ETH_TRANSCEIVER_IDENT_OFFSET 8
835 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
836 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
837 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
838 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
840 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
841 #define OEM_CFG_SCHED_TYPE_OFFSET 2
842 #define OEM_CFG_SCHED_TYPE_ETS 0x1
843 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
845 struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS];
846 u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA];
849 /**************************************/
851 /* P U B L I C F U N C */
853 /**************************************/
857 u32 iscsi_boot_signature;
858 u32 iscsi_boot_block_offset;
860 /* MTU size per funciton is needed for the OV feature */
862 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
863 /* For PCP values 0-3 use the map lower */
864 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
865 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
867 u32 c2s_pcp_map_lower;
868 /* For PCP values 4-7 use the map upper */
869 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
870 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
872 u32 c2s_pcp_map_upper;
874 /* For PCP default value get the MSB byte of the map default */
875 u32 c2s_pcp_map_default;
877 /* For generic inter driver communication channel messages between PFs via MFW*/
878 struct generic_idc_msg_s generic_idc_msg;
882 // replace old mf_cfg
885 /* function 0 of each port cannot be hidden */
886 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
887 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
888 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001
891 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
892 #define FUNC_MF_CFG_PROTOCOL_OFFSET 4
893 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
894 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
895 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
896 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
897 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
900 /* value range - 0..100, increments in 1 % */
901 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
902 #define FUNC_MF_CFG_MIN_BW_OFFSET 8
903 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
904 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
905 #define FUNC_MF_CFG_MAX_BW_OFFSET 16
906 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
909 #define FUNC_MF_CFG_RDMA_PROTOCOL_MASK 0x03000000
910 #define FUNC_MF_CFG_RDMA_PROTOCOL_OFFSET 24
911 #define FUNC_MF_CFG_RDMA_PROTOCOL_NONE 0x00000000
912 #define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE 0x01000000
913 #define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP 0x02000000
914 /*for future support*/
915 #define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH 0x03000000
917 #define FUNC_MF_CFG_BOOT_MODE_MASK 0x0C000000
918 #define FUNC_MF_CFG_BOOT_MODE_OFFSET 26
919 #define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL 0x00000000
920 #define FUNC_MF_CFG_BOOT_MODE_DISABLED 0x04000000
921 #define FUNC_MF_CFG_BOOT_MODE_ENABLED 0x08000000
924 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
925 #define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002
926 #define FUNC_STATUS_FORCED_LINK 0x00000004
928 u32 mac_upper; /* MAC */
929 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
930 #define FUNC_MF_CFG_UPPERMAC_OFFSET 0
931 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
933 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
935 u32 fcoe_wwn_port_name_upper;
936 u32 fcoe_wwn_port_name_lower;
938 u32 fcoe_wwn_node_name_upper;
939 u32 fcoe_wwn_node_name_lower;
941 u32 ovlan_stag; /* tags */
942 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
943 #define FUNC_MF_CFG_OV_STAG_OFFSET 0
944 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
946 u32 pf_allocation; /* vf per pf */
948 u32 preserve_data; /* Will be used bt CCM */
950 u32 driver_last_activity_ts;
953 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
956 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
959 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
960 #define DRV_ID_PDA_COMP_VER_OFFSET 0
962 #define LOAD_REQ_HSI_VERSION 2
963 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
964 #define DRV_ID_MCP_HSI_VER_OFFSET 16
965 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_OFFSET)
967 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
968 #define DRV_ID_DRV_TYPE_OFFSET 24
969 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET)
970 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET)
971 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET)
972 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET)
973 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET)
974 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET)
975 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET)
976 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET)
977 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET)
979 #define DRV_ID_DRV_TYPE_OS (DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \
980 DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \
981 DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX)
983 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
984 #define DRV_ID_DRV_INIT_HW_OFFSET 31
985 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET)
988 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
989 #define OEM_CFG_FUNC_TC_OFFSET 0
990 #define OEM_CFG_FUNC_TC_0 0x0
991 #define OEM_CFG_FUNC_TC_1 0x1
992 #define OEM_CFG_FUNC_TC_2 0x2
993 #define OEM_CFG_FUNC_TC_3 0x3
994 #define OEM_CFG_FUNC_TC_4 0x4
995 #define OEM_CFG_FUNC_TC_5 0x5
996 #define OEM_CFG_FUNC_TC_6 0x6
997 #define OEM_CFG_FUNC_TC_7 0x7
999 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
1000 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4
1001 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
1002 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
1005 /**************************************/
1007 /* P U B L I C M B */
1009 /**************************************/
1010 /* This is the only section that the driver can write to, and each */
1011 /* Basically each driver request to set feature parameters,
1012 * will be done using a different command, which will be linked
1013 * to a specific data structure from the union below.
1014 * For huge strucuture, the common blank structure should be used.
1018 u32 mac_upper; /* Upper 16 bits are always zeroes */
1022 struct mcp_file_att {
1027 struct bist_nvm_image_att {
1029 u32 image_type; /* Image type */
1030 u32 nvm_start_addr; /* NVM address of the image */
1031 u32 len; /* Include CRC */
1034 #define MCP_DRV_VER_STR_SIZE 16
1035 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
1036 #define MCP_DRV_NVM_BUF_LEN 32
1037 struct drv_version_stc {
1039 u8 name[MCP_DRV_VER_STR_SIZE - 4];
1042 /* statistics for ncsi */
1043 struct lan_stats_stc {
1050 struct fcoe_stats_stc {
1057 struct iscsi_stats_stc {
1064 struct rdma_stats_stc {
1071 struct ocbb_data_stc {
1074 u32 ocsd_req_update_interval;
1077 #define MAX_NUM_OF_SENSORS 7
1078 #define MFW_SENSOR_LOCATION_INTERNAL 1
1079 #define MFW_SENSOR_LOCATION_EXTERNAL 2
1080 #define MFW_SENSOR_LOCATION_SFP 3
1082 #define SENSOR_LOCATION_OFFSET 0
1083 #define SENSOR_LOCATION_MASK 0x000000ff
1084 #define THRESHOLD_HIGH_OFFSET 8
1085 #define THRESHOLD_HIGH_MASK 0x0000ff00
1086 #define CRITICAL_TEMPERATURE_OFFSET 16
1087 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000
1088 #define CURRENT_TEMP_OFFSET 24
1089 #define CURRENT_TEMP_MASK 0xff000000
1090 struct temperature_status_stc {
1092 u32 sensor[MAX_NUM_OF_SENSORS];
1095 /* crash dump configuration header */
1096 struct mdump_config_stc {
1104 enum resource_id_enum {
1105 RESOURCE_NUM_SB_E = 0,
1106 RESOURCE_NUM_L2_QUEUE_E = 1,
1107 RESOURCE_NUM_VPORT_E = 2,
1108 RESOURCE_NUM_VMQ_E = 3,
1109 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, /* Not a real resource!! it's a factor used to calculate others */
1110 RESOURCE_FACTOR_RSS_PER_VF_E = 5, /* Not a real resource!! it's a factor used to calculate others */
1111 RESOURCE_NUM_RL_E = 6,
1112 RESOURCE_NUM_PQ_E = 7,
1113 RESOURCE_NUM_VF_E = 8,
1114 RESOURCE_VFC_FILTER_E = 9,
1115 RESOURCE_ILT_E = 10,
1116 RESOURCE_CQS_E = 11,
1117 RESOURCE_GFT_PROFILES_E = 12,
1118 RESOURCE_NUM_TC_E = 13,
1119 RESOURCE_NUM_RSS_ENGINES_E = 14,
1120 RESOURCE_LL2_QUEUE_E = 15,
1121 RESOURCE_RDMA_STATS_QUEUE_E = 16,
1122 RESOURCE_BDQ_E = 17,
1124 RESOURCE_NUM_INVALID = 0xFFFFFFFF
1127 /* Resource ID is to be filled by the driver in the MB request
1128 * Size, offset & flags to be filled by the MFW in the MB response
1130 struct resource_info {
1131 enum resource_id_enum res_id;
1132 u32 size; /* number of allocated resources */
1133 u32 offset; /* Offset of the 1st resource */
1137 #define RESOURCE_ELEMENT_STRICT (1 << 0)
1145 #define DRV_ROLE_NONE 0
1146 #define DRV_ROLE_PREBOOT 1
1147 #define DRV_ROLE_OS 2
1148 #define DRV_ROLE_KDUMP 3
1150 struct load_req_stc {
1155 #define LOAD_REQ_ROLE_MASK 0x000000FF
1156 #define LOAD_REQ_ROLE_OFFSET 0
1157 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
1158 #define LOAD_REQ_LOCK_TO_OFFSET 8
1159 #define LOAD_REQ_LOCK_TO_DEFAULT 0
1160 #define LOAD_REQ_LOCK_TO_NONE 255
1161 #define LOAD_REQ_FORCE_MASK 0x000F0000
1162 #define LOAD_REQ_FORCE_OFFSET 16
1163 #define LOAD_REQ_FORCE_NONE 0
1164 #define LOAD_REQ_FORCE_PF 1
1165 #define LOAD_REQ_FORCE_ALL 2
1166 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
1167 #define LOAD_REQ_FLAGS0_OFFSET 20
1168 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
1171 struct load_rsp_stc {
1176 #define LOAD_RSP_ROLE_MASK 0x000000FF
1177 #define LOAD_RSP_ROLE_OFFSET 0
1178 #define LOAD_RSP_HSI_MASK 0x0000FF00
1179 #define LOAD_RSP_HSI_OFFSET 8
1180 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
1181 #define LOAD_RSP_FLAGS0_OFFSET 16
1182 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
1185 struct mdump_retain_data_stc {
1192 struct attribute_cmd_write_stc {
1198 struct lldp_stats_stc {
1199 u32 tx_frames_total;
1200 u32 rx_frames_total;
1201 u32 rx_frames_discarded;
1205 union drv_union_data {
1206 struct mcp_mac wol_mac; /* UNLOAD_DONE */
1208 /* This configuration should be set by the driver for the LINK_SET command. */
1209 struct eth_phy_cfg drv_phy_cfg;
1211 struct mcp_val64 val64; /* For PHY / AVS commands */
1213 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
1215 struct mcp_file_att file_att;
1217 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
1219 struct drv_version_stc drv_version;
1221 struct lan_stats_stc lan_stats;
1222 struct fcoe_stats_stc fcoe_stats;
1223 struct iscsi_stats_stc iscsi_stats;
1224 struct rdma_stats_stc rdma_stats;
1225 struct ocbb_data_stc ocbb_info;
1226 struct temperature_status_stc temp_info;
1227 struct resource_info resource;
1228 struct bist_nvm_image_att nvm_image_att;
1229 struct mdump_config_stc mdump_config;
1230 struct mcp_mac lldp_mac;
1231 struct mcp_wwn fcoe_fabric_name;
1234 struct load_req_stc load_req;
1235 struct load_rsp_stc load_rsp;
1236 struct mdump_retain_data_stc mdump_retain;
1237 struct attribute_cmd_write_stc attribute_cmd_write;
1238 struct lldp_stats_stc lldp_stats;
1242 struct public_drv_mb {
1245 #define DRV_MSG_CODE_MASK 0xffff0000
1246 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1247 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1248 #define DRV_MSG_CODE_INIT_HW 0x12000000
1249 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
1250 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
1251 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1252 #define DRV_MSG_CODE_INIT_PHY 0x22000000
1253 /* Params - FORCE - Reinitialize the link regardless of LFA */
1254 /* - DONT_CARE - Don't flap the link if up */
1255 #define DRV_MSG_CODE_LINK_RESET 0x23000000
1257 #define DRV_MSG_CODE_SET_LLDP 0x24000000
1258 #define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000
1259 #define DRV_MSG_CODE_SET_DCBX 0x25000000
1260 /* OneView feature driver HSI*/
1261 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
1262 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
1263 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
1264 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
1265 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
1266 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
1267 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
1268 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
1269 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */
1270 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
1271 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
1272 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
1273 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
1274 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000
1275 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000
1276 #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000
1277 #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000
1278 #define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000
1279 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
1280 #define DRV_MSG_CODE_GET_LLDP_STATS 0x42000000
1281 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 /* params [31:8] - reserved, [7:0] - bitmap */
1283 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 /*deprecated don't use*/
1284 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
1285 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1286 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
1287 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
1288 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */
1289 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */
1290 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 /* MFW will place the file offset and len in file_att struct */
1291 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/
1292 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */
1293 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 /* Delete a file from nvram. Param is image_type. */
1294 #define DRV_MSG_CODE_MCP_RESET 0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */
1295 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */
1296 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/
1297 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */
1298 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 /* Param: [0:15] - Address, [30:31] - port */
1299 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:15] - Address, [30:31] - port */
1300 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */
1301 #define DRV_MSG_CODE_MCP_HALT 0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */
1302 #define DRV_MSG_CODE_SET_VMAC 0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1303 #define DRV_MSG_CODE_GET_VMAC 0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */
1304 #define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4
1305 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
1306 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
1307 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
1308 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
1310 #define DRV_MSG_CODE_GET_STATS 0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */
1311 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
1312 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
1313 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
1314 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
1315 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 /* Host shall provide buffer and size for MFW */
1316 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 /* Host shall provide buffer and size for MFW */
1317 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */
1318 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */
1319 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 /* indicate OCBB related information */
1320 #define DRV_MSG_CODE_SET_BW 0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */
1321 #define BW_MAX_MASK 0x000000ff
1322 #define BW_MAX_OFFSET 0
1323 #define BW_MIN_MASK 0x0000ff00
1324 #define BW_MIN_OFFSET 8
1326 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */
1327 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */
1328 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
1329 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1)
1330 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 /* Param: [0:15] - gpio number */
1331 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */
1332 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
1333 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
1334 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */
1335 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */
1336 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 /* This is an empty mailbox just return OK*/
1338 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */
1340 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
1341 #define RESOURCE_CMD_REQ_RESC_OFFSET 0
1342 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
1343 #define RESOURCE_CMD_REQ_OPCODE_OFFSET 5
1344 #define RESOURCE_OPCODE_REQ 1 /* request resource ownership with default aging */
1345 #define RESOURCE_OPCODE_REQ_WO_AGING 2 /* request resource ownership without aging */
1346 #define RESOURCE_OPCODE_REQ_W_AGING 3 /* request resource ownership with specific aging timer (in seconds) */
1347 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */
1348 #define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */
1349 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
1350 #define RESOURCE_CMD_REQ_AGE_OFFSET 8
1352 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
1353 #define RESOURCE_CMD_RSP_OWNER_OFFSET 0
1354 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
1355 #define RESOURCE_CMD_RSP_OPCODE_OFFSET 8
1356 #define RESOURCE_OPCODE_GNT 1 /* resource is free and granted to requester */
1357 #define RESOURCE_OPCODE_BUSY 2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */
1358 #define RESOURCE_OPCODE_RELEASED 3 /* indicate release request was acknowledged */
1359 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 /* indicate release request was previously received by other owner */
1360 #define RESOURCE_OPCODE_WRONG_OWNER 5 /* indicate wrong owner during release */
1361 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
1363 #define RESOURCE_DUMP 0 /* dedicate resource 0 for dump */
1365 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */
1366 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 /* Send crash dump commands with param[3:0] - opcode */
1367 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
1368 #define DRV_MSG_CODE_MDUMP_ACK 0x01 /* acknowledge reception of error indication */
1369 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */
1370 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 /* trigger crash dump procedure */
1371 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 /* Request valid logs and config words */
1372 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */
1373 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */
1374 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */
1375 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */
1376 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */
1377 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 /* Param: [0:15] - gpio number */
1378 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value will be placed in union */
1379 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 /* Value shoud be placed in union */
1380 #define DRV_MB_PARAM_ADDR_OFFSET 0
1381 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
1382 #define DRV_MB_PARAM_DEVAD_OFFSET 16
1383 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
1384 #define DRV_MB_PARAM_PORT_OFFSET 21
1385 #define DRV_MB_PARAM_PORT_MASK 0x00600000
1386 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000
1387 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
1388 #define DRV_MSG_CODE_SET_LLDP_MAC 0x002c0000
1389 #define DRV_MSG_CODE_GET_LLDP_MAC 0x002d0000
1390 #define DRV_MSG_CODE_OS_WOL 0x002e0000
1392 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */
1393 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
1394 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */
1396 #define DRV_MSG_CODE_READ_WOL_REG 0X00320000
1397 #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000
1398 #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000
1399 #define DRV_MSG_CODE_ATTRIBUTE 0x00350000 /* Param: [0:23] Attribute key, [24:31] Attribute sub command */
1401 #define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 /* Param: Password len. Union: Plain Password */
1402 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */
1404 /* Pmbus commands */
1405 #define DRV_MSG_CODE_PMBUS_READ 0x00380000 /* Param: [0:7] - Cmd, [8:9] - len */
1406 #define DRV_MSG_CODE_PMBUS_WRITE 0x00390000 /* Param: [0:7] - Cmd, [8:9] - len, [16:31] -data*/
1408 #define DRV_MB_PARAM_PMBUS_CMD_OFFSET 0
1409 #define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF
1410 #define DRV_MB_PARAM_PMBUS_LEN_OFFSET 8
1411 #define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300
1412 #define DRV_MB_PARAM_PMBUS_DATA_OFFSET 16
1413 #define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000
1415 #define DRV_MSG_CODE_GENERIC_IDC 0x003a0000
1417 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1420 /* UNLOAD_REQ params */
1421 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1422 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1423 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1424 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1426 /* UNLOAD_DONE_params */
1427 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1429 /* INIT_PHY params */
1430 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1431 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1433 /* LLDP / DCBX params*/
1434 /* To be used with SET_LLDP command */
1435 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1436 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0
1437 /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */
1438 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1439 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1
1440 /* To be used with REGISTER_LLDP_TLVS_RX command */
1441 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001
1442 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0
1443 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0
1444 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4
1445 /* To be used with SET_DCBX command */
1446 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1447 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3
1449 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1450 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0
1452 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1453 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1455 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
1456 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
1457 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24
1458 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
1460 #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0
1461 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
1462 #define DRV_MB_PARAM_PHY_LANE_OFFSET 16
1463 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
1464 #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29
1465 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
1466 #define DRV_MB_PARAM_PHY_PORT_OFFSET 30
1467 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
1469 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0
1470 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
1471 #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8
1472 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
1473 /* configure vf MSIX params BB */
1474 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0
1475 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1476 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8
1477 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1478 /* configure vf MSIX for PF params AH*/
1479 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0
1480 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF
1482 /* OneView configuration parametres */
1483 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0
1484 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1485 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1486 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
1487 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
1488 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
1489 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4
1490 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5
1491 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
1492 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7
1494 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0
1495 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
1496 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
1497 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1)
1498 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1)
1499 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
1500 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3)
1501 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3)
1502 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
1503 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
1504 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
1505 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
1507 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0
1508 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
1510 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0
1511 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1512 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1513 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1514 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1515 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1517 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0
1518 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1519 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1520 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 /* Not Installed*/
1521 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1522 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 /* installed but disabled by user/admin/OS */
1523 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 /* installed and active */
1525 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0
1526 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1528 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
1529 DRV_MB_PARAM_WOL_DISABLED | \
1530 DRV_MB_PARAM_WOL_ENABLED)
1531 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
1532 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
1533 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
1535 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
1536 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
1537 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
1538 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
1539 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
1540 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
1542 #define DRV_MB_PARAM_FCOE_CVID_MASK 0xFFF
1543 #define DRV_MB_PARAM_FCOE_CVID_OFFSET 0
1545 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
1546 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
1548 #define DRV_MB_PARAM_LLDP_STATS_AGENT_MASK 0xFF
1549 #define DRV_MB_PARAM_LLDP_STATS_AGENT_OFFSET 0
1551 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1552 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1553 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1555 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
1556 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1557 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
1558 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
1559 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
1560 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
1561 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
1562 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
1564 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0
1565 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
1566 #define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16
1567 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
1568 #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16
1569 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
1570 #define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24
1571 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
1573 /* Resource Allocation params - Driver version support*/
1574 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1575 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
1576 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1577 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1579 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1580 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
1581 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
1582 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
1583 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
1585 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1586 #define DRV_MB_PARAM_BIST_RC_PASSED 1
1587 #define DRV_MB_PARAM_BIST_RC_FAILED 2
1588 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
1590 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0
1591 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
1592 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8
1593 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
1595 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
1596 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
1597 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */
1598 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 /* driver supports EEE parameter */
1599 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000
1600 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16
1601 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 /* driver supports virtual link parameter */
1602 /* Driver attributes params */
1603 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
1604 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF
1605 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24
1606 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000
1609 #define FW_MSG_CODE_MASK 0xffff0000
1610 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
1611 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
1612 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1613 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1614 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
1615 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
1616 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
1617 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
1618 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
1619 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
1620 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1621 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
1622 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
1623 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
1624 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1625 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
1626 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
1627 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
1628 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
1629 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
1630 #define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000
1631 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
1632 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
1633 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
1634 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
1635 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
1636 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
1637 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1638 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
1639 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
1640 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
1641 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
1642 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000
1643 #define FW_MSG_CODE_UPDATE_WOL_DONE 0x38000000
1644 #define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE 0x39000000
1645 #define FW_MSG_CODE_UPDATE_ERR 0x3a010000
1646 #define FW_MSG_CODE_UPDATE_PARAM_ERR 0x3a020000
1647 #define FW_MSG_CODE_UPDATE_NOT_ALLOWED 0x3a030000
1648 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
1649 #define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE 0x3c000000
1650 #define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE 0x3d000000
1651 #define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE 0x3e000000
1652 #define FW_MSG_CODE_RESET_TO_DEFAULT_ACK 0x3f000000
1653 #define FW_MSG_CODE_OV_GET_CURR_CFG_DONE 0x40000000
1654 #define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000
1655 #define FW_MSG_CODE_GET_LLDP_STATS_DONE 0x42000000
1656 #define FW_MSG_CODE_GET_LLDP_STATS_ERROR 0x42010000
1658 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
1659 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1660 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
1661 #define FW_MSG_CODE_FLR_ACK 0x02000000
1662 #define FW_MSG_CODE_FLR_NACK 0x02100000
1663 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
1664 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
1665 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
1667 #define FW_MSG_CODE_NVM_OK 0x00010000
1668 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
1669 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
1670 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1671 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
1672 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
1673 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1674 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1675 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
1676 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
1677 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
1678 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
1679 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
1680 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
1681 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
1682 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
1683 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
1684 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
1685 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
1686 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */
1687 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000
1688 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000
1689 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000
1691 #define FW_MSG_CODE_PHY_OK 0x00110000
1692 #define FW_MSG_CODE_PHY_ERROR 0x00120000
1693 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
1694 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
1695 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
1696 #define FW_MSG_CODE_OK 0x00160000
1697 #define FW_MSG_CODE_ERROR 0x00170000
1698 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
1699 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
1700 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
1701 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
1702 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
1703 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1704 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
1705 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
1706 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
1707 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
1708 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
1709 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1710 #define FW_MSG_CODE_GPIO_OK 0x00160000
1711 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
1712 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
1713 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
1714 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
1715 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000
1716 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000
1717 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000
1718 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000
1719 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000
1720 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000
1722 /* mdump related response codes */
1723 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000
1724 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000
1725 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
1726 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000
1727 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000
1729 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
1730 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
1732 #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000
1733 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000
1734 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000
1735 #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000
1736 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000
1739 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
1740 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
1742 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1744 #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000
1745 #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000
1747 #define FW_MSG_CODE_IDC_BUSY 0x00010000
1750 /* Resource Allocation params - MFW version support */
1751 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1752 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
1753 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1754 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1756 /* get pf rdma protocol command response */
1757 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
1758 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
1759 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
1760 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
1762 /* get MFW feature support response */
1763 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports SmartLinQ */
1764 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 /* MFW supports EEE */
1765 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 /* MFW supports DRV_LOAD Timeout */
1766 #define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET 0x00000008 /* MFW supports early detection of LP Presence */
1767 #define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD 0x00000010 /* MFW supports relaxed ordering setting */
1768 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 /* MFW supports virtual link */
1770 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1<<0)
1772 #define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF
1773 #define FW_MB_PARAM_OEM_UPDATE_OFFSET 0
1774 #define FW_MB_PARAM_OEM_UPDATE_BW 0x01
1775 #define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02
1776 #define FW_MB_PARAM_OEM_UPDATE_CFG 0x04
1778 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
1779 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0
1780 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
1781 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1
1782 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
1783 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2
1784 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
1785 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3
1787 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF
1788 #define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0
1791 #define DRV_PULSE_SEQ_MASK 0x00007fff
1792 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1794 * The system time is in the format of
1795 * (year-2001)*12*32 + month*32 + day.
1797 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1799 * Indicate to the firmware not to go into the
1800 * OS-absent when it is not getting driver pulse.
1801 * This is used for debugging as well for PXE(MBA).
1805 #define MCP_PULSE_SEQ_MASK 0x00007fff
1806 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1807 /* Indicates to the driver not to assert due to lack
1808 * of MCP response */
1809 #define MCP_EVENT_MASK 0xffff0000
1810 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1812 /* The union data is used by the driver to pass parameters to the scratchpad. */
1813 union drv_union_data union_data;
1818 /**********************************************************************
1820 * Incremental Aggregative
1821 * 8-bit MFW counter per message
1822 * 8-bit ack-counter per message
1824 * Provides up to 256 aggregative message per type
1825 * Provides 4 message types in dword
1826 * Message type pointers to byte offset
1827 * Backward Compatibility by using sizeof for the counters.
1828 * No lock requires for 32bit messages
1830 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
1831 * is required to prevent data corruption.
1832 **********************************************************************/
1833 enum MFW_DRV_MSG_TYPE {
1834 MFW_DRV_MSG_LINK_CHANGE,
1835 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
1836 MFW_DRV_MSG_VF_DISABLED,
1837 MFW_DRV_MSG_LLDP_DATA_UPDATED,
1838 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
1839 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
1840 MFW_DRV_MSG_ERROR_RECOVERY,
1841 MFW_DRV_MSG_BW_UPDATE,
1842 MFW_DRV_MSG_S_TAG_UPDATE,
1843 MFW_DRV_MSG_GET_LAN_STATS,
1844 MFW_DRV_MSG_GET_FCOE_STATS,
1845 MFW_DRV_MSG_GET_ISCSI_STATS,
1846 MFW_DRV_MSG_GET_RDMA_STATS,
1847 MFW_DRV_MSG_FAILURE_DETECTED,
1848 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1849 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
1850 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE,
1851 MFW_DRV_MSG_GET_TLV_REQ,
1852 MFW_DRV_MSG_OEM_CFG_UPDATE,
1853 MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED,
1854 MFW_DRV_MSG_GENERIC_IDC, /* Generic Inter Driver Communication message */
1858 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
1859 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
1860 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
1861 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1863 #ifdef BIG_ENDIAN /* Like MFW */
1864 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++;
1866 #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;
1869 #define MFW_DRV_UPDATE(shmem_func, msg_id) (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++;
1871 struct public_mfw_mb {
1872 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */
1873 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the MFW */
1874 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the driver */
1877 /**************************************/
1879 /* P U B L I C D A T A */
1881 /**************************************/
1882 enum public_sections {
1883 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
1884 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
1892 struct drv_ver_info_stc {
1897 /* Runtime data needs about 1/2K. We use 2K to be on the safe side.
1898 * Please make sure data does not exceed this size.
1900 #define NUM_RUNTIME_DWORDS 16
1901 struct drv_init_hw_stc {
1902 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS];
1903 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32];
1906 struct mcp_public_data {
1907 /* The sections fields is an array */
1909 offsize_t sections[PUBLIC_MAX_SECTIONS];
1910 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
1911 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
1912 struct public_global global;
1913 struct public_path path[MCP_GLOB_PATH_MAX];
1914 struct public_port port[MCP_GLOB_PORT_MAX];
1915 struct public_func func[MCP_GLOB_FUNC_MAX];
1918 #define I2C_TRANSCEIVER_ADDR 0xa0
1919 #define MAX_I2C_TRANSACTION_SIZE 16
1920 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256
1922 /* OCBB definitions */
1924 /* Category 1: Device Properties */
1926 DRV_TLV_CLP_STR_CTD,
1927 /* Category 6: Device Configuration */
1934 /* Category 8: Port Configuration */
1935 DRV_TLV_NPIV_ENABLED,
1936 /* Category 10: Function Configuration */
1937 DRV_TLV_FEATURE_FLAGS,
1938 DRV_TLV_LOCAL_ADMIN_ADDR,
1939 DRV_TLV_ADDITIONAL_MAC_ADDR_1,
1940 DRV_TLV_ADDITIONAL_MAC_ADDR_2,
1941 DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
1942 DRV_TLV_LSO_MIN_SEGMENT_COUNT,
1943 DRV_TLV_PROMISCUOUS_MODE,
1944 DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
1945 DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
1946 DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
1947 DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
1948 DRV_TLV_OS_DRIVER_STATES,
1949 DRV_TLV_PXE_BOOT_PROGRESS,
1950 /* Category 12: FC/FCoE Configuration */
1952 DRV_TLV_NUM_OF_NPIV_IDS,
1953 DRV_TLV_SWITCH_NAME,
1954 DRV_TLV_SWITCH_PORT_NUM,
1955 DRV_TLV_SWITCH_PORT_ID,
1956 DRV_TLV_VENDOR_NAME,
1957 DRV_TLV_SWITCH_MODEL,
1958 DRV_TLV_SWITCH_FW_VER,
1959 DRV_TLV_QOS_PRIORITY_PER_802_1P,
1962 DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
1963 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
1964 DRV_TLV_LINK_FAILURE_COUNT,
1965 DRV_TLV_FCOE_BOOT_PROGRESS,
1966 /* Category 13: iSCSI Configuration */
1967 DRV_TLV_TARGET_LLMNR_ENABLED,
1968 DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
1969 DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
1970 DRV_TLV_AUTHENTICATION_METHOD,
1971 DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
1972 DRV_TLV_MAX_FRAME_SIZE,
1973 DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
1974 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
1975 DRV_TLV_ISCSI_BOOT_PROGRESS,
1976 /* Category 20: Device Data */
1977 DRV_TLV_PCIE_BUS_RX_UTILIZATION,
1978 DRV_TLV_PCIE_BUS_TX_UTILIZATION,
1979 DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
1980 DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
1981 DRV_TLV_NCSI_RX_BYTES_RECEIVED,
1982 DRV_TLV_NCSI_TX_BYTES_SENT,
1983 /* Category 22: Base Port Data */
1984 DRV_TLV_RX_DISCARDS,
1987 DRV_TLV_TX_DISCARDS,
1988 DRV_TLV_RX_FRAMES_RECEIVED,
1989 DRV_TLV_TX_FRAMES_SENT,
1990 /* Category 23: FC/FCoE Port Data */
1991 DRV_TLV_RX_BROADCAST_PACKETS,
1992 DRV_TLV_TX_BROADCAST_PACKETS,
1993 /* Category 28: Base Function Data */
1994 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
1995 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
1996 DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
1997 DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
1998 DRV_TLV_PF_RX_FRAMES_RECEIVED,
1999 DRV_TLV_RX_BYTES_RECEIVED,
2000 DRV_TLV_PF_TX_FRAMES_SENT,
2001 DRV_TLV_TX_BYTES_SENT,
2002 DRV_TLV_IOV_OFFLOAD,
2003 DRV_TLV_PCI_ERRORS_CAP_ID,
2004 DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
2005 DRV_TLV_UNCORRECTABLE_ERROR_MASK,
2006 DRV_TLV_CORRECTABLE_ERROR_STATUS,
2007 DRV_TLV_CORRECTABLE_ERROR_MASK,
2008 DRV_TLV_PCI_ERRORS_AECC_REGISTER,
2009 DRV_TLV_TX_QUEUES_EMPTY,
2010 DRV_TLV_RX_QUEUES_EMPTY,
2011 DRV_TLV_TX_QUEUES_FULL,
2012 DRV_TLV_RX_QUEUES_FULL,
2013 /* Category 29: FC/FCoE Function Data */
2014 DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
2015 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
2016 DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
2017 DRV_TLV_FCOE_RX_BYTES_RECEIVED,
2018 DRV_TLV_FCOE_TX_FRAMES_SENT,
2019 DRV_TLV_FCOE_TX_BYTES_SENT,
2020 DRV_TLV_CRC_ERROR_COUNT,
2021 DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
2022 DRV_TLV_CRC_ERROR_1_TIMESTAMP,
2023 DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
2024 DRV_TLV_CRC_ERROR_2_TIMESTAMP,
2025 DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
2026 DRV_TLV_CRC_ERROR_3_TIMESTAMP,
2027 DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
2028 DRV_TLV_CRC_ERROR_4_TIMESTAMP,
2029 DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
2030 DRV_TLV_CRC_ERROR_5_TIMESTAMP,
2031 DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
2032 DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
2033 DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
2034 DRV_TLV_DISPARITY_ERROR_COUNT,
2035 DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
2036 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
2037 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
2038 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
2039 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
2040 DRV_TLV_LAST_FLOGI_TIMESTAMP,
2041 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
2042 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
2043 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
2044 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
2045 DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
2046 DRV_TLV_LAST_FLOGI_RJT,
2047 DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
2048 DRV_TLV_FDISCS_SENT_COUNT,
2049 DRV_TLV_FDISC_ACCS_RECEIVED,
2050 DRV_TLV_FDISC_RJTS_RECEIVED,
2051 DRV_TLV_PLOGI_SENT_COUNT,
2052 DRV_TLV_PLOGI_ACCS_RECEIVED,
2053 DRV_TLV_PLOGI_RJTS_RECEIVED,
2054 DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
2055 DRV_TLV_PLOGI_1_TIMESTAMP,
2056 DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
2057 DRV_TLV_PLOGI_2_TIMESTAMP,
2058 DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
2059 DRV_TLV_PLOGI_3_TIMESTAMP,
2060 DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
2061 DRV_TLV_PLOGI_4_TIMESTAMP,
2062 DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
2063 DRV_TLV_PLOGI_5_TIMESTAMP,
2064 DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
2065 DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
2066 DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
2067 DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
2068 DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
2069 DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
2070 DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
2071 DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
2072 DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
2073 DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
2074 DRV_TLV_LOGOS_ISSUED,
2075 DRV_TLV_LOGO_ACCS_RECEIVED,
2076 DRV_TLV_LOGO_RJTS_RECEIVED,
2077 DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
2078 DRV_TLV_LOGO_1_TIMESTAMP,
2079 DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
2080 DRV_TLV_LOGO_2_TIMESTAMP,
2081 DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
2082 DRV_TLV_LOGO_3_TIMESTAMP,
2083 DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
2084 DRV_TLV_LOGO_4_TIMESTAMP,
2085 DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
2086 DRV_TLV_LOGO_5_TIMESTAMP,
2087 DRV_TLV_LOGOS_RECEIVED,
2088 DRV_TLV_ACCS_ISSUED,
2089 DRV_TLV_PRLIS_ISSUED,
2090 DRV_TLV_ACCS_RECEIVED,
2091 DRV_TLV_ABTS_SENT_COUNT,
2092 DRV_TLV_ABTS_ACCS_RECEIVED,
2093 DRV_TLV_ABTS_RJTS_RECEIVED,
2094 DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
2095 DRV_TLV_ABTS_1_TIMESTAMP,
2096 DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
2097 DRV_TLV_ABTS_2_TIMESTAMP,
2098 DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
2099 DRV_TLV_ABTS_3_TIMESTAMP,
2100 DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
2101 DRV_TLV_ABTS_4_TIMESTAMP,
2102 DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
2103 DRV_TLV_ABTS_5_TIMESTAMP,
2104 DRV_TLV_RSCNS_RECEIVED,
2105 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
2106 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
2107 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
2108 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
2109 DRV_TLV_LUN_RESETS_ISSUED,
2110 DRV_TLV_ABORT_TASK_SETS_ISSUED,
2111 DRV_TLV_TPRLOS_SENT,
2112 DRV_TLV_NOS_SENT_COUNT,
2113 DRV_TLV_NOS_RECEIVED_COUNT,
2117 DRV_TLV_LIP_SENT_COUNT,
2118 DRV_TLV_LIP_RECEIVED_COUNT,
2120 DRV_TLV_EOFNI_COUNT,
2121 DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
2122 DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
2123 DRV_TLV_SCSI_STATUS_BUSY_COUNT,
2124 DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
2125 DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
2126 DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
2127 DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
2128 DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
2129 DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
2130 DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
2131 DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
2132 DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
2133 DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
2134 DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
2135 DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
2136 DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
2137 DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
2138 DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
2139 DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
2140 /* Category 30: iSCSI Function Data */
2141 DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
2142 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
2143 DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
2144 DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
2145 DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
2146 DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
2149 #define I2C_DEV_ADDR_A2 0xa2
2150 #define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60
2151 #define SFP_EEPROM_A2_TEMPERATURE_SIZE 2
2152 #define SFP_EEPROM_A2_VCC_ADDR 0x62
2153 #define SFP_EEPROM_A2_VCC_SIZE 2
2154 #define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64
2155 #define SFP_EEPROM_A2_TX_BIAS_SIZE 2
2156 #define SFP_EEPROM_A2_TX_POWER_ADDR 0x66
2157 #define SFP_EEPROM_A2_TX_POWER_SIZE 2
2158 #define SFP_EEPROM_A2_RX_POWER_ADDR 0x68
2159 #define SFP_EEPROM_A2_RX_POWER_SIZE 2
2161 #define I2C_DEV_ADDR_A0 0xa0
2162 #define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16
2163 #define QSFP_EEPROM_A0_TEMPERATURE_SIZE 2
2164 #define QSFP_EEPROM_A0_VCC_ADDR 0x1a
2165 #define QSFP_EEPROM_A0_VCC_SIZE 2
2166 #define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a
2167 #define QSFP_EEPROM_A0_TX1_BIAS_SIZE 2
2168 #define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32
2169 #define QSFP_EEPROM_A0_TX1_POWER_SIZE 2
2170 #define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22
2171 #define QSFP_EEPROM_A0_RX1_POWER_SIZE 2
2173 /**************************************
2174 * eDiag NETWORK Mode (DON)
2175 **************************************/
2177 #define ETH_DON_TYPE 0x0911 /* NETWORK Mode for QeDiag */
2178 #define ETH_DON_TRACE_TYPE 0x0912 /* NETWORK Mode Continous Trace */
2180 #define DON_RESP_UNKNOWN_CMD_ID 0x10 /* Response Error */
2182 /* Op Codes, Response is Op Code+1 */
2184 #define DON_REG_READ_REQ_CMD_ID 0x11
2185 #define DON_REG_WRITE_REQ_CMD_ID 0x22
2186 #define DON_CHALLENGE_REQ_CMD_ID 0x33
2187 #define DON_NVM_READ_REQ_CMD_ID 0x44
2188 #define DON_BLOCK_READ_REQ_CMD_ID 0x55
2190 #define DON_MFW_MODE_TRACE_CONTINUOUS_ID 0x70
2192 #if defined(MFW) || defined(DIAG) || defined(WINEDIAG)
2195 #if defined(_MSC_VER)
2196 #pragma pack(push,1)
2207 /* DON Message data starts here, after L2 header */
2208 /* Do not change alignment to keep backward compatability */
2209 u16 cmd_id; /* Op code and response code */
2212 struct { /* DON Commands */
2217 struct { /* DON Traces */
2218 u16 mcp_clock; /* MCP Clock in MHz */
2219 u16 trace_size; /* Trace size in bytes */
2221 u32 seconds; /* Seconds since last reset */
2222 u32 ticks; /* Timestamp (NOW) */
2226 u8 digest[32]; /* SHA256 */
2233 #if defined(_MSC_VER)
2238 #endif /* #ifndef UEFI */
2240 #endif /* #if defined(MFW) || defined(DIAG) || defined(WINEDIAG) */
2242 #endif /* MCP_PUBLIC_H */