2 * Copyright (c) 2017-2018 Cavium, Inc.
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6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
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15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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25 * POSSIBILITY OF SUCH DAMAGE.
32 /****************************************************************************
36 * Description: NVM config file - Generated file from nvm cfg excel.
41 ****************************************************************************/
47 #define NVM_CFG_version 0x83306
49 #define NVM_CFG_new_option_seq 26
51 #define NVM_CFG_removed_option_seq 2
53 #define NVM_CFG_updated_value_seq 5
55 struct nvm_cfg_mac_address
58 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
59 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
63 /******************************************
65 ******************************************/
68 u32 generic_cont0; /* 0x0 */
69 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
70 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
71 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
72 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
73 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
74 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
75 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
76 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
77 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
78 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
79 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
80 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
81 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
82 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
83 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
84 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
85 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
86 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
87 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
88 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
89 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
90 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
91 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
92 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
93 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
94 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
95 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
96 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
97 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
98 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
99 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
100 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
101 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000
102 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31
103 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0
104 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1
105 u32 engineering_change[3]; /* 0x4 */
106 u32 manufacturing_id; /* 0x10 */
107 u32 serial_number[4]; /* 0x14 */
108 u32 pcie_cfg; /* 0x24 */
109 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
110 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
111 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
112 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
113 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
114 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
115 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
116 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
117 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
118 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
119 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
120 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
121 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
122 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
123 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
124 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020
125 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
126 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
127 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
128 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
129 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
130 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
131 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
132 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
133 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
134 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
135 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
136 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
137 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
138 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
139 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
140 /* Set the duration, in seconds, fan failure signal should be
142 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000
143 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
144 u32 mgmt_traffic; /* 0x28 */
145 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
146 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
147 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
148 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
149 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
150 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
151 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
152 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
153 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
154 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
155 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
156 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
157 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
158 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000
159 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27
160 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0
161 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1
162 /* Indicates whether external thermal sonsor is available */
163 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000
164 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31
165 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0
166 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1
167 u32 core_cfg; /* 0x2C */
168 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
169 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
170 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
171 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
172 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
173 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
174 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
175 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
176 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
177 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
178 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
179 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
180 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
181 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
182 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
183 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
184 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
185 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
186 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
187 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
188 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
189 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
190 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
191 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
192 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
193 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
194 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
195 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
196 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1
197 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2
198 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
199 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
200 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
201 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
202 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
203 #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000
204 #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31
205 #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0
206 #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1
207 u32 e_lane_cfg1; /* 0x30 */
208 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
209 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
210 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
211 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
212 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
213 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
214 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
215 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
216 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
217 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
218 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
219 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
220 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
221 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
222 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
223 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
224 u32 e_lane_cfg2; /* 0x34 */
225 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
226 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
227 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
228 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
229 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
230 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
231 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
232 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
233 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
234 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
235 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
236 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
237 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
238 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
239 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
240 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
241 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
242 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
243 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
244 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
245 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
246 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
247 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
248 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
249 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
250 /* Maximum advertised pcie link width */
251 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
252 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
253 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
254 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
255 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
256 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
257 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4
259 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000
260 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20
261 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0
262 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1
263 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000
264 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22
265 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0
266 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1
267 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2
268 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3
269 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000
270 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25
271 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0
272 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1
273 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2
274 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3
275 /* Set the PLDM sensor modes */
276 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000
277 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27
278 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0
279 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1
280 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2
281 /* Enable VDM interface */
282 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000
283 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30
284 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0
285 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1
287 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000
288 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31
289 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0
290 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1
291 u32 f_lane_cfg1; /* 0x38 */
292 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
293 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
294 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
295 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
296 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
297 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
298 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
299 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
300 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
301 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
302 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
303 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
304 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
305 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
306 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
307 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
308 u32 f_lane_cfg2; /* 0x3C */
309 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
310 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
311 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
312 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
313 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
314 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
315 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
316 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
317 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
318 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
319 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
320 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
321 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
322 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
323 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
324 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
325 /* Control the period between two successive checks */
326 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00
327 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8
328 /* Set shutdown temperature */
329 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000
330 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16
331 /* Set max. count for over operational temperature */
332 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
333 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
334 u32 mps10_preemphasis; /* 0x40 */
335 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
336 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
337 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
338 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
339 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
340 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
341 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
342 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
343 u32 mps10_driver_current; /* 0x44 */
344 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
345 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
346 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
347 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
348 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
349 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
350 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
351 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
352 u32 mps25_preemphasis; /* 0x48 */
353 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
354 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
355 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
356 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
357 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
358 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
359 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
360 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
361 u32 mps25_driver_current; /* 0x4C */
362 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
363 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
364 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
365 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
366 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
367 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
368 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
369 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
370 u32 pci_id; /* 0x50 */
371 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
372 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
373 /* Set caution temperature */
374 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000
375 #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16
376 /* Set external thermal sensor I2C address */
377 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000
378 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24
379 u32 pci_subsys_id; /* 0x54 */
380 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
381 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
382 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
383 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
385 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
386 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
387 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
388 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
389 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
390 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
391 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
392 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
393 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
401 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
402 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
403 /* BB VF BAR2 size */
404 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
405 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
406 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
407 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
408 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
409 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
410 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
411 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
420 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
421 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
422 /* BB BAR2 size (global) */
423 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
424 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
425 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
426 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
427 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
428 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
429 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
430 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
431 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
432 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
433 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
434 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
435 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
436 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
437 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
438 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
439 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
440 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
441 /* Set the duration, in seconds, fan failure signal should be
443 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
444 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
445 /* This field defines the board total budget for bar2 when disabled
446 the regular bar size is used. */
447 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
448 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
449 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
450 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
451 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
452 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
453 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
454 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
455 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
456 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
457 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
458 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
459 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
460 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
461 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
462 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
463 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
464 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
465 /* Enable/Disable Crash dump triggers */
466 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
467 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
468 u32 mps10_txfir_main; /* 0x5C */
469 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
470 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
471 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
472 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
473 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
474 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
475 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
476 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
477 u32 mps10_txfir_post; /* 0x60 */
478 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
479 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
480 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
481 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
482 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
483 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
484 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
485 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
486 u32 mps25_txfir_main; /* 0x64 */
487 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
488 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
489 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
490 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
491 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
492 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
493 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
494 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
495 u32 mps25_txfir_post; /* 0x68 */
496 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
497 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
498 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
499 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
500 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
501 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
502 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
503 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
504 u32 manufacture_ver; /* 0x6C */
505 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
506 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
507 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
508 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
509 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
510 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
511 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
512 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
513 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
514 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
515 /* Select package id method */
516 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000
517 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30
518 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0
519 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1
520 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000
521 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31
522 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0
523 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1
524 u32 manufacture_time; /* 0x70 */
525 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
526 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
527 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
528 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
529 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
530 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
531 /* Max MSIX for Ethernet in default mode */
532 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000
533 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18
535 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000
536 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26
537 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0
538 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1
539 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000
540 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28
541 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0
542 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1
543 /* Enable/Disable PCIE Relaxed Ordering */
544 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK 0x40000000
545 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_OFFSET 30
546 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED 0x0
547 #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED 0x1
548 u32 led_global_settings; /* 0x74 */
549 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
550 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
551 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
552 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
553 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
554 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
555 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
556 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
557 /* Max. continues operating temperature */
558 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000
559 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16
560 /* GPIO which triggers run-time port swap according to the map
561 specified in option 205 */
562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000
563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24
564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0
565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1
566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2
567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3
568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4
569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5
570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6
571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7
572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8
573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9
574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA
575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB
576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC
577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD
578 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE
579 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF
580 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10
581 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11
582 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12
583 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13
584 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14
585 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15
586 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16
587 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17
588 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18
589 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19
590 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A
591 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B
592 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C
593 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D
594 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E
595 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F
596 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20
597 u32 generic_cont1; /* 0x78 */
598 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
599 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
600 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
601 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
602 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
603 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
604 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
605 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
606 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
607 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
608 /* Enable option 195 - Overriding the PCIe Preset value */
609 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000
610 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18
611 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0
612 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1
613 /* PCIe Preset value - applies only if option 194 is enabled */
614 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000
615 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19
616 /* Port mapping to be used when the run-time GPIO for port-swap is
618 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000
619 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23
620 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000
621 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25
622 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000
623 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27
624 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000
625 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29
626 u32 mbi_version; /* 0x7C */
627 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
628 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
629 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
630 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
631 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
632 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
633 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event
635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000
636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24
637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0
638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1
639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2
640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3
641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4
642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5
643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6
644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7
645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8
646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9
647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA
648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB
649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC
650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD
651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE
652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF
653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10
654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11
655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12
656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13
657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14
658 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15
659 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16
660 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17
661 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18
662 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19
663 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A
664 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B
665 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C
666 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D
667 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E
668 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F
669 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20
670 u32 mbi_date; /* 0x80 */
671 u32 misc_sig; /* 0x84 */
672 /* Define the GPIO mapping to switch i2c mux */
673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
698 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
699 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
700 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
701 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
702 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
703 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
704 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
705 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
706 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
707 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
708 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
709 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
710 /* Interrupt signal used for SMBus/I2C management interface
712 0 = Interrupt event occurred
715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000
716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16
717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0
718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1
719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2
720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3
721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4
722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5
723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6
724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7
725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8
726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9
727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA
728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB
729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC
730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD
731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE
732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF
733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10
734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11
735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12
736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13
737 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14
738 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15
739 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16
740 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17
741 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18
742 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19
743 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A
744 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B
745 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C
746 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D
747 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E
748 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F
749 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20
750 /* Set aLOM FAN on GPIO */
751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000
752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24
753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0
754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1
755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2
756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3
757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4
758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5
759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6
760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7
761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8
762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9
763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA
764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB
765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC
766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD
767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE
768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF
769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10
770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11
771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12
772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13
773 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14
774 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15
775 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16
776 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17
777 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18
778 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19
779 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A
780 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B
781 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C
782 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D
783 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E
784 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F
785 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20
786 u32 device_capabilities; /* 0x88 */
787 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
788 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
789 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
790 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
791 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
792 u32 power_dissipated; /* 0x8C */
793 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
794 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
795 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00
796 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8
797 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000
798 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16
799 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000
800 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24
801 u32 power_consumed; /* 0x90 */
802 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF
803 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0
804 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00
805 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8
806 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000
807 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16
808 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
809 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
810 u32 efi_version; /* 0x94 */
811 u32 multi_network_modes_capability; /* 0x98 */
812 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
813 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
814 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
815 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
816 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
817 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
818 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
819 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80
820 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100
821 u32 nvm_cfg_version; /* 0x9C */
822 u32 nvm_cfg_new_option_seq; /* 0xA0 */
823 u32 nvm_cfg_removed_option_seq; /* 0xA4 */
824 u32 nvm_cfg_updated_value_seq; /* 0xA8 */
825 u32 extended_serial_number[8]; /* 0xAC */
826 u32 oem1_number[8]; /* 0xCC */
827 u32 oem2_number[8]; /* 0xEC */
828 u32 mps25_active_txfir_pre; /* 0x10C */
829 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF
830 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0
831 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00
832 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8
833 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000
834 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16
835 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000
836 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24
837 u32 mps25_active_txfir_main; /* 0x110 */
838 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF
839 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0
840 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00
841 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8
842 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000
843 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16
844 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000
845 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24
846 u32 mps25_active_txfir_post; /* 0x114 */
847 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF
848 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0
849 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00
850 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8
851 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000
852 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16
853 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000
854 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24
855 u32 features; /* 0x118 */
856 /* Set the Aux Fan on temperature */
857 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF
858 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0
859 /* Set NC-SI package ID */
860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00
861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8
862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0
863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1
864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2
865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3
866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4
867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5
868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6
869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7
870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8
871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9
872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA
873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB
874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC
875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD
876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE
877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF
878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10
879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11
880 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12
881 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13
882 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14
883 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15
884 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16
885 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17
886 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18
887 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19
888 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A
889 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B
890 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C
891 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D
892 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E
893 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F
894 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20
895 /* PMBUS Clock GPIO */
896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000
897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16
898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0
899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1
900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2
901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3
902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4
903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5
904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6
905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7
906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8
907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9
908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA
909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB
910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC
911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD
912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE
913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF
914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10
915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11
916 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12
917 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13
918 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14
919 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15
920 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16
921 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17
922 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18
923 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19
924 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A
925 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B
926 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C
927 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D
928 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E
929 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F
930 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20
931 /* PMBUS Data GPIO */
932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000
933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24
934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0
935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1
936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2
937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3
938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4
939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5
940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6
941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7
942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8
943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9
944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA
945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB
946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC
947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD
948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE
949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF
950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10
951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11
952 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12
953 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13
954 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14
955 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15
956 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16
957 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17
958 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18
959 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19
960 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A
961 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B
962 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C
963 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D
964 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E
965 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F
966 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20
967 u32 tx_rx_eq_25g_hlpc; /* 0x11C */
968 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF
969 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0
970 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00
971 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8
972 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000
973 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16
974 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000
975 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24
976 u32 tx_rx_eq_25g_llpc; /* 0x120 */
977 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF
978 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0
979 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00
980 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8
981 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000
982 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16
983 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000
984 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24
985 u32 tx_rx_eq_25g_ac; /* 0x124 */
986 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF
987 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0
988 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00
989 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8
990 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000
991 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16
992 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000
993 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24
994 u32 tx_rx_eq_10g_pc; /* 0x128 */
995 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF
996 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0
997 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00
998 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8
999 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000
1000 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16
1001 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000
1002 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24
1003 u32 tx_rx_eq_10g_ac; /* 0x12C */
1004 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF
1005 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0
1006 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00
1007 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8
1008 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000
1009 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16
1010 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000
1011 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24
1012 u32 tx_rx_eq_1g; /* 0x130 */
1013 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF
1014 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0
1015 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00
1016 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8
1017 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000
1018 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16
1019 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000
1020 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24
1021 u32 tx_rx_eq_25g_bt; /* 0x134 */
1022 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF
1023 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0
1024 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00
1025 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8
1026 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000
1027 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16
1028 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000
1029 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24
1030 u32 tx_rx_eq_10g_bt; /* 0x138 */
1031 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF
1032 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0
1033 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00
1034 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8
1035 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000
1036 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16
1037 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000
1038 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24
1039 u32 generic_cont4; /* 0x13C */
1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF
1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0
1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0
1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1
1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2
1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3
1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4
1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5
1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6
1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7
1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8
1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9
1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA
1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB
1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC
1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD
1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE
1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF
1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10
1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11
1060 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12
1061 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13
1062 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14
1063 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15
1064 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16
1065 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17
1066 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18
1067 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19
1068 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A
1069 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B
1070 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C
1071 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D
1072 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E
1073 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F
1074 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20
1075 u32 preboot_debug_mode_std; /* 0x140 */
1076 u32 preboot_debug_mode_ext; /* 0x144 */
1077 u32 ext_phy_cfg1; /* 0x148 */
1078 /* Ext PHY MDI pair swap value */
1079 #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF
1080 #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0
1081 u32 clocks; /* 0x14C */
1082 /* Sets core clock frequency */
1083 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF
1084 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0
1085 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0
1086 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1
1087 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2
1088 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3
1089 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4
1090 #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5
1091 /* Sets MAC clock frequency */
1092 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00
1093 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8
1094 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0
1095 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1
1096 #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2
1097 /* Sets storm clock frequency */
1098 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000
1099 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16
1100 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0
1101 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1
1102 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2
1103 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3
1104 #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4
1105 u32 reserved[54]; /* 0x150 */
1108 struct nvm_cfg1_path
1110 u32 reserved[1]; /* 0x0 */
1113 struct nvm_cfg1_port
1115 u32 reserved__m_relocated_to_option_123; /* 0x0 */
1116 u32 reserved__m_relocated_to_option_124; /* 0x4 */
1117 u32 generic_cont0; /* 0x8 */
1118 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
1119 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
1120 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
1121 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
1122 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
1123 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
1124 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
1125 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
1126 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
1127 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
1128 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
1129 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
1130 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
1131 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
1132 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
1133 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
1134 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
1135 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
1136 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
1137 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
1138 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
1139 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
1140 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
1141 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
1142 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
1143 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
1144 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
1145 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
1146 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
1147 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
1148 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
1149 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
1150 /* GPIO for HW reset the PHY. In case it is the same for all ports,
1151 need to set same value for all ports */
1152 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000
1153 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24
1154 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0
1155 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1
1156 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2
1157 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3
1158 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4
1159 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5
1160 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6
1161 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7
1162 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8
1163 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9
1164 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA
1165 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB
1166 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC
1167 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD
1168 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE
1169 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF
1170 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10
1171 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11
1172 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12
1173 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13
1174 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14
1175 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15
1176 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16
1177 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17
1178 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18
1179 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19
1180 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A
1181 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B
1182 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C
1183 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D
1184 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E
1185 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F
1186 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20
1187 u32 pcie_cfg; /* 0xC */
1188 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
1189 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
1190 u32 features; /* 0x10 */
1191 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
1192 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
1193 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
1194 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
1195 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
1196 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
1197 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
1198 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
1199 u32 speed_cap_mask; /* 0x14 */
1200 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1201 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1202 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1203 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1204 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1205 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1206 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1207 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1208 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1209 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1210 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1211 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1212 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1213 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1214 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1215 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1216 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1217 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1218 u32 link_settings; /* 0x18 */
1219 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
1220 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
1221 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
1222 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
1223 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
1224 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
1225 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
1226 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
1227 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
1228 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
1229 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
1230 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
1231 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
1232 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
1233 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
1234 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
1235 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
1236 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
1237 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
1238 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
1239 #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3
1240 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
1241 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
1242 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
1243 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
1244 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
1245 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
1246 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
1247 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
1248 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
1249 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
1250 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
1251 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
1252 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
1253 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
1254 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
1255 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
1256 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
1257 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
1258 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
1259 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
1260 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
1261 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
1262 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
1263 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000
1264 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20
1265 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0
1266 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1
1267 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2
1268 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3
1269 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4
1270 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5
1271 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6
1272 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000
1273 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23
1274 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0
1275 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1
1276 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000
1277 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24
1278 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0
1279 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1
1280 u32 phy_cfg; /* 0x1C */
1281 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
1282 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
1283 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
1284 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
1285 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
1286 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
1287 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
1288 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
1289 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
1290 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
1291 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
1292 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
1293 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
1294 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
1295 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
1296 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
1297 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
1298 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
1299 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
1300 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
1301 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
1302 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
1303 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
1304 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
1305 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
1306 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
1307 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
1308 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
1309 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
1310 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
1311 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
1312 u32 mgmt_traffic; /* 0x20 */
1313 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
1314 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
1315 u32 ext_phy; /* 0x24 */
1316 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
1317 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
1318 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
1319 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1
1320 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2
1321 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
1322 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
1323 /* EEE power saving mode */
1324 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
1325 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
1326 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
1327 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
1328 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
1329 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
1330 u32 mba_cfg1; /* 0x28 */
1331 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
1332 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
1333 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
1334 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
1335 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
1336 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
1337 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
1338 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
1339 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
1340 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
1341 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
1342 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
1343 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
1344 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
1345 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
1346 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
1347 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
1348 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
1349 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
1350 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
1351 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
1352 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
1353 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
1354 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3
1355 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
1356 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
1357 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
1358 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
1359 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
1360 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
1361 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000
1362 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24
1363 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0
1364 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1
1365 u32 mba_cfg2; /* 0x2C */
1366 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
1367 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
1368 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
1369 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
1370 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000
1371 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17
1372 u32 vf_cfg; /* 0x30 */
1373 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
1374 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
1375 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
1376 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
1377 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
1378 u32 led_port_settings; /* 0x3C */
1379 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
1380 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
1381 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
1382 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
1383 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
1384 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
1385 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
1386 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
1387 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4
1388 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8
1389 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8
1390 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10
1391 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10
1392 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20
1393 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
1394 /* UID LED Blink Mode Settings */
1395 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK 0x0F000000
1396 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_OFFSET 24
1397 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED 0x1
1398 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0 0x2
1399 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1 0x4
1400 #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2 0x8
1401 u32 transceiver_00; /* 0x40 */
1402 /* Define for mapping of transceiver signal module absent */
1403 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
1404 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
1405 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
1406 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
1407 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
1408 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
1409 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
1410 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
1411 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
1412 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
1413 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
1414 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
1415 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
1416 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
1417 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
1418 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
1419 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
1420 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
1421 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
1422 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
1423 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
1424 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
1425 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
1426 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
1427 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
1428 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
1429 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
1430 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
1431 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
1432 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
1433 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
1434 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
1435 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
1436 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
1437 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
1438 /* Define the GPIO mux settings to switch i2c mux to this port */
1439 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
1440 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
1441 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
1442 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
1443 u32 device_ids; /* 0x44 */
1444 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
1445 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
1446 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
1447 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
1448 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
1449 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
1450 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
1451 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
1452 u32 board_cfg; /* 0x48 */
1453 /* This field defines the board technology
1454 (backpane,transceiver,external PHY) */
1455 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
1456 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
1457 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
1458 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
1459 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
1460 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
1461 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
1462 /* This field defines the GPIO mapped to tx_disable signal in SFP */
1463 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
1464 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
1465 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
1466 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
1467 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
1468 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
1469 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
1470 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
1471 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
1472 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
1473 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
1474 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
1475 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
1476 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
1477 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
1478 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
1479 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
1480 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
1481 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
1482 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
1483 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
1484 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
1485 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
1486 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
1487 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
1488 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
1489 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
1490 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
1491 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
1492 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
1493 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
1494 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
1495 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
1496 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
1497 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
1498 u32 mnm_10g_cap; /* 0x4C */
1499 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1500 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1501 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1502 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1503 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1504 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1505 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1506 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1507 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1508 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1509 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1510 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1511 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1512 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1513 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1514 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1515 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1516 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1517 u32 mnm_10g_ctrl; /* 0x50 */
1518 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
1519 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
1520 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
1521 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
1522 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
1523 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3
1524 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
1525 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
1526 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
1527 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
1528 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
1529 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
1530 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
1531 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
1532 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
1533 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3
1534 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
1535 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
1536 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
1537 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
1538 /* This field defines the board technology
1539 (backpane,transceiver,external PHY) */
1540 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
1541 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
1542 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
1543 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
1544 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
1545 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
1546 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
1547 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000
1548 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
1549 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
1550 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
1551 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
1552 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
1553 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
1554 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
1555 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
1556 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
1557 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
1558 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
1559 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
1560 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
1561 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
1562 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
1563 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
1564 u32 mnm_10g_misc; /* 0x54 */
1565 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
1566 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
1567 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
1568 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
1569 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
1570 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
1571 u32 mnm_25g_cap; /* 0x58 */
1572 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1573 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1574 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1575 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1576 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1577 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1578 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1579 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1580 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1581 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1582 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1583 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1584 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1585 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1586 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1587 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1588 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1589 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1590 u32 mnm_25g_ctrl; /* 0x5C */
1591 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
1592 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
1593 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
1594 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
1595 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
1596 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3
1597 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
1598 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
1599 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
1600 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
1601 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
1602 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
1603 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
1604 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
1605 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
1606 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3
1607 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
1608 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
1609 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
1610 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
1611 /* This field defines the board technology
1612 (backpane,transceiver,external PHY) */
1613 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
1614 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
1615 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
1616 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
1617 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
1618 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
1619 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
1620 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000
1621 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
1622 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
1623 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
1624 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
1625 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
1626 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
1627 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
1628 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
1629 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
1630 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
1631 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
1632 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
1633 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
1634 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
1635 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
1636 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
1637 u32 mnm_25g_misc; /* 0x60 */
1638 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
1639 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
1640 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
1641 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
1642 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
1643 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
1644 u32 mnm_40g_cap; /* 0x64 */
1645 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1646 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1647 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1648 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1649 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1650 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1651 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1652 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1653 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1654 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1655 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1656 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1657 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1658 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1659 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1660 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1661 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1662 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1663 u32 mnm_40g_ctrl; /* 0x68 */
1664 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
1665 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
1666 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
1667 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
1668 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
1669 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3
1670 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
1671 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
1672 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
1673 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
1674 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
1675 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
1676 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
1677 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
1678 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
1679 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3
1680 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
1681 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
1682 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
1683 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
1684 /* This field defines the board technology
1685 (backpane,transceiver,external PHY) */
1686 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
1687 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
1688 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
1689 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
1690 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
1691 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
1692 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
1693 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000
1694 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
1695 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
1696 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
1697 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
1698 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
1699 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
1700 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
1701 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
1702 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
1703 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
1704 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
1705 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
1706 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
1707 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
1708 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
1709 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
1710 u32 mnm_40g_misc; /* 0x6C */
1711 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
1712 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
1713 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
1714 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
1715 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
1716 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
1717 u32 mnm_50g_cap; /* 0x70 */
1718 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
1719 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
1720 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
1721 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
1722 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
1723 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
1724 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
1725 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
1726 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1727 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
1728 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
1729 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
1730 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
1731 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
1732 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
1733 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
1734 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
1735 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1736 u32 mnm_50g_ctrl; /* 0x74 */
1737 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
1738 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
1739 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
1740 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
1741 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
1742 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3
1743 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
1744 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
1745 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
1746 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
1747 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
1748 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
1749 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
1750 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
1751 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
1752 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3
1753 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
1754 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
1755 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
1756 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
1757 /* This field defines the board technology
1758 (backpane,transceiver,external PHY) */
1759 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
1760 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
1761 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
1762 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
1763 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
1764 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
1765 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
1766 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000
1767 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
1768 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
1769 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
1770 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
1771 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
1772 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
1773 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
1774 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
1775 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
1776 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
1777 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
1778 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
1779 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
1780 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
1781 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
1782 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
1783 u32 mnm_50g_misc; /* 0x78 */
1784 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
1785 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
1786 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
1787 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
1788 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
1789 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
1790 u32 mnm_100g_cap; /* 0x7C */
1791 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF
1792 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
1793 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
1794 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
1795 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4
1796 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
1797 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
1798 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
1799 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
1800 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000
1801 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
1802 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
1803 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
1804 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4
1805 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
1806 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
1807 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
1808 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
1809 u32 mnm_100g_ctrl; /* 0x80 */
1810 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
1811 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
1812 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
1813 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
1814 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
1815 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3
1816 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
1817 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
1818 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
1819 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
1820 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
1821 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
1822 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
1823 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
1824 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
1825 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3
1826 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
1827 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
1828 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
1829 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
1830 /* This field defines the board technology
1831 (backpane,transceiver,external PHY) */
1832 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
1833 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
1834 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
1835 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
1836 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
1837 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
1838 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
1839 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000
1840 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
1841 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
1842 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
1843 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
1844 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
1845 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
1846 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
1847 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
1848 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
1849 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
1850 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
1851 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
1852 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
1853 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
1854 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
1855 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
1856 u32 mnm_100g_misc; /* 0x84 */
1857 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
1858 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
1859 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
1860 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
1861 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
1862 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
1863 u32 temperature; /* 0x88 */
1864 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF
1865 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0
1866 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00
1867 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8
1868 u32 ext_phy_cfg1; /* 0x8C */
1869 /* Ext PHY MDI pair swap value */
1870 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF
1871 #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0
1872 u32 reserved[114]; /* 0x90 */
1875 struct nvm_cfg1_func
1877 struct nvm_cfg_mac_address mac_address; /* 0x0 */
1878 u32 rsrv1; /* 0x8 */
1879 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
1880 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
1881 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
1882 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
1883 u32 rsrv2; /* 0xC */
1884 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
1885 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
1886 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
1887 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
1888 u32 device_id; /* 0x10 */
1889 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
1890 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
1891 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
1892 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
1893 u32 cmn_cfg; /* 0x14 */
1894 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
1895 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
1896 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
1897 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
1898 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
1899 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
1900 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
1901 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
1902 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
1903 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
1904 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
1905 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
1906 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
1907 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
1908 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
1909 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
1910 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
1911 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
1912 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
1913 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
1914 u32 pci_cfg; /* 0x18 */
1915 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
1916 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
1917 /* AH VF BAR2 size */
1918 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
1919 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
1920 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
1921 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
1922 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
1923 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
1924 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
1925 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
1926 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
1927 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
1928 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
1929 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
1930 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
1931 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
1932 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
1933 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
1934 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
1935 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
1936 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
1937 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
1938 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
1939 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
1940 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
1941 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
1942 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
1943 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
1944 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
1945 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
1946 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
1947 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
1948 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
1949 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
1950 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
1951 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
1952 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
1953 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
1954 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
1955 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
1956 /* Hide function in npar mode */
1957 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
1958 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
1959 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
1960 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
1961 /* AH BAR2 size (per function) */
1962 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
1963 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
1964 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
1965 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
1966 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
1967 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
1968 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
1969 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
1970 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
1971 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
1972 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
1973 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
1974 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
1975 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
1976 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
1977 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
1978 u32 preboot_generic_cfg; /* 0x2C */
1979 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
1980 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0
1981 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000
1982 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16
1983 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000
1984 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17
1985 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1
1986 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2
1987 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4
1988 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8
1989 u32 features; /* 0x30 */
1990 /* RDMA protocol enablement */
1991 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003
1992 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0
1993 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0
1994 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1
1995 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2
1996 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3
1997 u32 reserved[7]; /* 0x34 */
2002 struct nvm_cfg1_glob glob; /* 0x0 */
2003 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */
2004 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
2005 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
2008 /******************************************
2010 ******************************************/
2019 char *friendly_name;
2022 enum nvm_cfg_sections
2024 NVM_CFG_SECTION_NVM_CFG1,
2031 u32 sections_offset[NVM_CFG_SECTION_MAX];
2032 struct nvm_cfg1 cfg1;
2035 #endif /* NVM_CFG_H */