2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef _QLNX_IOCTL_H_
32 #define _QLNX_IOCTL_H_
34 #include <sys/ioccom.h>
36 #define QLNX_MAX_HW_FUNCS 2
39 * Read grcdump and grcdump size
44 uint32_t grcdump_size[QLNX_MAX_HW_FUNCS];
45 void *grcdump[QLNX_MAX_HW_FUNCS];
46 uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS];
48 typedef struct qlnx_grcdump qlnx_grcdump_t;
51 * Read idle_chk and idle_chk size
53 struct qlnx_idle_chk {
55 uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS];
56 void *idle_chk[QLNX_MAX_HW_FUNCS];
57 uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS];
59 typedef struct qlnx_idle_chk qlnx_idle_chk_t;
68 #define QLNX_MCP_TRACE 0x01
69 #define QLNX_REG_FIFO 0x02
70 #define QLNX_IGU_FIFO 0x03
71 #define QLNX_PROTECTION_OVERRIDE 0x04
72 #define QLNX_FW_ASSERTS 0x05
74 uint32_t size[QLNX_MAX_HW_FUNCS];
75 void *buffer[QLNX_MAX_HW_FUNCS];
76 uint32_t dwords[QLNX_MAX_HW_FUNCS];
78 typedef struct qlnx_trace qlnx_trace_t;
84 #define QLNX_DRV_INFO_NAME_LENGTH 32
85 #define QLNX_DRV_INFO_VERSION_LENGTH 32
86 #define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32
87 #define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32
88 #define QLNX_DRV_INFO_BUS_INFO_LENGTH 32
91 char drv_name[QLNX_DRV_INFO_NAME_LENGTH];
92 char drv_version[QLNX_DRV_INFO_VERSION_LENGTH];
93 char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH];
94 char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH];
95 uint32_t eeprom_dump_len; /* in bytes */
96 uint32_t reg_dump_len; /* in bytes */
97 char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH];
99 typedef struct qlnx_drvinfo qlnx_drvinfo_t;
102 * Read Device Setting
104 struct qlnx_dev_setting {
105 uint32_t supported; /* Features this interface supports */
106 uint32_t advertising; /* Features this interface advertises */
107 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */
108 uint32_t duplex; /* Duplex, half or full */
109 uint32_t port; /* Which connector port */
110 uint32_t phy_address; /* port number*/
111 uint32_t autoneg; /* Enable or disable autonegotiation */
113 typedef struct qlnx_dev_setting qlnx_dev_setting_t;
118 struct qlnx_get_regs {
120 uint32_t reg_buf_len;
122 typedef struct qlnx_get_regs qlnx_get_regs_t;
129 #define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01
130 #define QLNX_NVRAM_CMD_READ_NVRAM 0x02
131 #define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03
132 #define QLNX_NVRAM_CMD_DEL_FILE 0x04
133 #define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05
134 #define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06
135 #define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07
142 typedef struct qlnx_nvram qlnx_nvram_t;
145 * Get/Set Device registers
147 struct qlnx_reg_rd_wr {
149 #define QLNX_REG_READ_CMD 0x01
150 #define QLNX_REG_WRITE_CMD 0x02
155 uint32_t access_type;
156 #define QLNX_REG_ACCESS_DIRECT 0x01
157 #define QLNX_REG_ACCESS_INDIRECT 0x02
161 typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t;
164 * Read/Write PCI Configuration
166 struct qlnx_pcicfg_rd_wr {
168 #define QLNX_PCICFG_READ 0x01
169 #define QLNX_PCICFG_WRITE 0x02
174 typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t;
179 struct qlnx_perm_mac_addr {
182 typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t;
186 * Read STORM statistics registers
188 struct qlnx_storm_stats {
191 uint32_t xstorm_active_cycles;
192 uint32_t xstorm_stall_cycles;
193 uint32_t xstorm_sleeping_cycles;
194 uint32_t xstorm_inactive_cycles;
197 uint32_t ystorm_active_cycles;
198 uint32_t ystorm_stall_cycles;
199 uint32_t ystorm_sleeping_cycles;
200 uint32_t ystorm_inactive_cycles;
203 uint32_t pstorm_active_cycles;
204 uint32_t pstorm_stall_cycles;
205 uint32_t pstorm_sleeping_cycles;
206 uint32_t pstorm_inactive_cycles;
209 uint32_t tstorm_active_cycles;
210 uint32_t tstorm_stall_cycles;
211 uint32_t tstorm_sleeping_cycles;
212 uint32_t tstorm_inactive_cycles;
215 uint32_t mstorm_active_cycles;
216 uint32_t mstorm_stall_cycles;
217 uint32_t mstorm_sleeping_cycles;
218 uint32_t mstorm_inactive_cycles;
221 uint32_t ustorm_active_cycles;
222 uint32_t ustorm_stall_cycles;
223 uint32_t ustorm_sleeping_cycles;
224 uint32_t ustorm_inactive_cycles;
227 typedef struct qlnx_storm_stats qlnx_storm_stats_t;
229 #define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000)
231 #define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \
232 QLNX_STORM_STATS_SAMPLES_PER_HWFN)
234 struct qlnx_storm_stats_dump {
237 void *buffer[QLNX_MAX_HW_FUNCS];
240 typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t;
242 #define QLNX_LLDP_TYPE_END_OF_LLDPDU 0
243 #define QLNX_LLDP_TYPE_CHASSIS_ID 1
244 #define QLNX_LLDP_TYPE_PORT_ID 2
245 #define QLNX_LLDP_TYPE_TTL 3
246 #define QLNX_LLDP_TYPE_PORT_DESC 4
247 #define QLNX_LLDP_TYPE_SYS_NAME 5
248 #define QLNX_LLDP_TYPE_SYS_DESC 6
249 #define QLNX_LLDP_TYPE_SYS_CAPS 7
250 #define QLNX_LLDP_TYPE_MGMT_ADDR 8
251 #define QLNX_LLDP_TYPE_ORG_SPECIFIC 127
253 #define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte
254 #define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC 0x04 //Mac Address
255 #define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes
256 #define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME 0x06 //Interface Name
258 #define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte
259 #define QLNX_LLDP_PORT_ID_SUBTYPE_MAC 0x03 //Mac Address
260 #define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes
261 #define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME 0x05 //Interface Name
263 #define QLNX_LLDP_SYS_TLV_SIZE 256
264 struct qlnx_lldp_sys_tlvs {
265 int discard_mandatory_tlv;
266 uint8_t buf[QLNX_LLDP_SYS_TLV_SIZE];
269 typedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t;
275 #define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t)
280 #define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t)
285 #define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t)
290 #define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t)
295 #define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t)
298 * Read Device Setting
300 #define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t)
305 #define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t)
310 #define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t)
313 * Get/Set Device registers
315 #define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t)
318 * Read/Write PCI Configuration
320 #define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t)
325 #define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t)
328 * Read STORM statistics
330 #define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t)
335 #define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t)
340 #define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t)
345 #define QLNX_SET_LLDP_TLVS _IOWR('q', 15, qlnx_lldp_sys_tlvs_t)
347 #endif /* #ifndef _QLNX_IOCTL_H_ */