2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 * Author : David C Somayajulu, Cavium, Inc., San Jose, CA 95131.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
40 #include "ecore_gtt_reg_addr.h"
42 #include "ecore_chain.h"
43 #include "ecore_status.h"
45 #include "ecore_rt_defs.h"
46 #include "ecore_init_ops.h"
47 #include "ecore_int.h"
48 #include "ecore_cxt.h"
49 #include "ecore_spq.h"
50 #include "ecore_init_fw_funcs.h"
51 #include "ecore_sp_commands.h"
52 #include "ecore_dev_api.h"
53 #include "ecore_l2_api.h"
54 #include "ecore_mcp.h"
55 #include "ecore_hw_defs.h"
56 #include "mcp_public.h"
57 #include "ecore_iro.h"
59 #include "ecore_dev_api.h"
60 #include "ecore_dbg_fw_funcs.h"
61 #include "ecore_iov_api.h"
62 #include "ecore_vf_api.h"
64 #include "qlnx_ioctl.h"
68 #ifdef QLNX_ENABLE_IWARP
69 #include "qlnx_rdma.h"
70 #endif /* #ifdef QLNX_ENABLE_IWARP */
79 * ioctl related functions
81 static void qlnx_add_sysctls(qlnx_host_t *ha);
86 static void qlnx_release(qlnx_host_t *ha);
87 static void qlnx_fp_isr(void *arg);
88 static void qlnx_init_ifnet(device_t dev, qlnx_host_t *ha);
89 static void qlnx_init(void *arg);
90 static void qlnx_init_locked(qlnx_host_t *ha);
91 static int qlnx_set_multi(qlnx_host_t *ha, uint32_t add_multi);
92 static int qlnx_set_promisc(qlnx_host_t *ha);
93 static int qlnx_set_allmulti(qlnx_host_t *ha);
94 static int qlnx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
95 static int qlnx_media_change(struct ifnet *ifp);
96 static void qlnx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr);
97 static void qlnx_stop(qlnx_host_t *ha);
98 static int qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp,
99 struct mbuf **m_headp);
100 static int qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha);
101 static uint32_t qlnx_get_optics(qlnx_host_t *ha,
102 struct qlnx_link_output *if_link);
103 static int qlnx_transmit(struct ifnet *ifp, struct mbuf *mp);
104 static int qlnx_transmit_locked(struct ifnet *ifp, struct qlnx_fastpath *fp,
106 static void qlnx_qflush(struct ifnet *ifp);
108 static int qlnx_alloc_parent_dma_tag(qlnx_host_t *ha);
109 static void qlnx_free_parent_dma_tag(qlnx_host_t *ha);
110 static int qlnx_alloc_tx_dma_tag(qlnx_host_t *ha);
111 static void qlnx_free_tx_dma_tag(qlnx_host_t *ha);
112 static int qlnx_alloc_rx_dma_tag(qlnx_host_t *ha);
113 static void qlnx_free_rx_dma_tag(qlnx_host_t *ha);
115 static int qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver);
116 static int qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size);
118 static int qlnx_nic_setup(struct ecore_dev *cdev,
119 struct ecore_pf_params *func_params);
120 static int qlnx_nic_start(struct ecore_dev *cdev);
121 static int qlnx_slowpath_start(qlnx_host_t *ha);
122 static int qlnx_slowpath_stop(qlnx_host_t *ha);
123 static int qlnx_init_hw(qlnx_host_t *ha);
124 static void qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
125 char ver_str[VER_SIZE]);
126 static void qlnx_unload(qlnx_host_t *ha);
127 static int qlnx_load(qlnx_host_t *ha);
128 static void qlnx_hw_set_multi(qlnx_host_t *ha, uint8_t *mta, uint32_t mcnt,
130 static void qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf,
132 static int qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq);
133 static void qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq);
134 static void qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn,
135 struct qlnx_rx_queue *rxq);
136 static int qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter);
137 static int qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords,
139 static int qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords,
141 static void qlnx_timer(void *arg);
142 static int qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
143 static void qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
144 static void qlnx_trigger_dump(qlnx_host_t *ha);
145 static uint16_t qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
146 struct qlnx_tx_queue *txq);
147 static void qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
148 struct qlnx_tx_queue *txq);
149 static int qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
151 static void qlnx_fp_taskqueue(void *context, int pending);
152 static void qlnx_sample_storm_stats(qlnx_host_t *ha);
153 static int qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
154 struct qlnx_agg_info *tpa);
155 static void qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa);
157 #if __FreeBSD_version >= 1100000
158 static uint64_t qlnx_get_counter(if_t ifp, ift_counter cnt);
163 * Hooks to the Operating Systems
165 static int qlnx_pci_probe (device_t);
166 static int qlnx_pci_attach (device_t);
167 static int qlnx_pci_detach (device_t);
171 #ifdef CONFIG_ECORE_SRIOV
173 static int qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params);
174 static void qlnx_iov_uninit(device_t dev);
175 static int qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params);
176 static void qlnx_initialize_sriov(qlnx_host_t *ha);
177 static void qlnx_pf_taskqueue(void *context, int pending);
178 static int qlnx_create_pf_taskqueues(qlnx_host_t *ha);
179 static void qlnx_destroy_pf_taskqueues(qlnx_host_t *ha);
180 static void qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha);
182 #endif /* #ifdef CONFIG_ECORE_SRIOV */
184 static device_method_t qlnx_pci_methods[] = {
185 /* Device interface */
186 DEVMETHOD(device_probe, qlnx_pci_probe),
187 DEVMETHOD(device_attach, qlnx_pci_attach),
188 DEVMETHOD(device_detach, qlnx_pci_detach),
190 #ifdef CONFIG_ECORE_SRIOV
191 DEVMETHOD(pci_iov_init, qlnx_iov_init),
192 DEVMETHOD(pci_iov_uninit, qlnx_iov_uninit),
193 DEVMETHOD(pci_iov_add_vf, qlnx_iov_add_vf),
194 #endif /* #ifdef CONFIG_ECORE_SRIOV */
198 static driver_t qlnx_pci_driver = {
199 "ql", qlnx_pci_methods, sizeof (qlnx_host_t),
202 static devclass_t qlnx_devclass;
204 MODULE_VERSION(if_qlnxe,1);
205 DRIVER_MODULE(if_qlnxe, pci, qlnx_pci_driver, qlnx_devclass, 0, 0);
207 MODULE_DEPEND(if_qlnxe, pci, 1, 1, 1);
208 MODULE_DEPEND(if_qlnxe, ether, 1, 1, 1);
212 static device_method_t qlnxv_pci_methods[] = {
213 /* Device interface */
214 DEVMETHOD(device_probe, qlnx_pci_probe),
215 DEVMETHOD(device_attach, qlnx_pci_attach),
216 DEVMETHOD(device_detach, qlnx_pci_detach),
220 static driver_t qlnxv_pci_driver = {
221 "ql", qlnxv_pci_methods, sizeof (qlnx_host_t),
224 static devclass_t qlnxv_devclass;
225 MODULE_VERSION(if_qlnxev,1);
226 DRIVER_MODULE(if_qlnxev, pci, qlnxv_pci_driver, qlnxv_devclass, 0, 0);
228 MODULE_DEPEND(if_qlnxev, pci, 1, 1, 1);
229 MODULE_DEPEND(if_qlnxev, ether, 1, 1, 1);
231 #endif /* #ifdef QLNX_VF */
233 MALLOC_DEFINE(M_QLNXBUF, "qlnxbuf", "Buffers for qlnx driver");
236 static char qlnx_dev_str[128];
237 static char qlnx_ver_str[VER_SIZE];
238 static char qlnx_name_str[NAME_SIZE];
241 * Some PCI Configuration Space Related Defines
244 #ifndef PCI_VENDOR_QLOGIC
245 #define PCI_VENDOR_QLOGIC 0x1077
248 /* 40G Adapter QLE45xxx*/
249 #ifndef QLOGIC_PCI_DEVICE_ID_1634
250 #define QLOGIC_PCI_DEVICE_ID_1634 0x1634
253 /* 100G Adapter QLE45xxx*/
254 #ifndef QLOGIC_PCI_DEVICE_ID_1644
255 #define QLOGIC_PCI_DEVICE_ID_1644 0x1644
258 /* 25G Adapter QLE45xxx*/
259 #ifndef QLOGIC_PCI_DEVICE_ID_1656
260 #define QLOGIC_PCI_DEVICE_ID_1656 0x1656
263 /* 50G Adapter QLE45xxx*/
264 #ifndef QLOGIC_PCI_DEVICE_ID_1654
265 #define QLOGIC_PCI_DEVICE_ID_1654 0x1654
268 /* 10G/25G/40G Adapter QLE41xxx*/
269 #ifndef QLOGIC_PCI_DEVICE_ID_8070
270 #define QLOGIC_PCI_DEVICE_ID_8070 0x8070
273 /* SRIOV Device (All Speeds) Adapter QLE41xxx*/
274 #ifndef QLOGIC_PCI_DEVICE_ID_8090
275 #define QLOGIC_PCI_DEVICE_ID_8090 0x8090
280 SYSCTL_NODE(_hw, OID_AUTO, qlnxe, CTLFLAG_RD, 0, "qlnxe driver parameters");
282 /* Number of Queues: 0 (Auto) or 1 to 32 (fixed queue number) */
283 static int qlnxe_queue_count = QLNX_DEFAULT_RSS;
285 #if __FreeBSD_version < 1100000
287 TUNABLE_INT("hw.qlnxe.queue_count", &qlnxe_queue_count);
291 SYSCTL_INT(_hw_qlnxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
292 &qlnxe_queue_count, 0, "Multi-Queue queue count");
296 * Note on RDMA personality setting
298 * Read the personality configured in NVRAM
299 * If the personality is ETH_ONLY, ETH_IWARP or ETH_ROCE and
300 * the configured personality in sysctl is QLNX_PERSONALITY_DEFAULT
301 * use the personality in NVRAM.
303 * Otherwise use t the personality configured in sysctl.
306 #define QLNX_PERSONALITY_DEFAULT 0x0 /* use personality in NVRAM */
307 #define QLNX_PERSONALITY_ETH_ONLY 0x1 /* Override with ETH_ONLY */
308 #define QLNX_PERSONALITY_ETH_IWARP 0x2 /* Override with ETH_IWARP */
309 #define QLNX_PERSONALITY_ETH_ROCE 0x3 /* Override with ETH_ROCE */
310 #define QLNX_PERSONALITY_BITS_PER_FUNC 4
311 #define QLNX_PERSONALIY_MASK 0xF
313 /* RDMA configuration; 64bit field allows setting for 16 physical functions*/
314 static uint64_t qlnxe_rdma_configuration = 0x22222222;
316 #if __FreeBSD_version < 1100000
318 TUNABLE_QUAD("hw.qlnxe.rdma_configuration", &qlnxe_rdma_configuration);
320 SYSCTL_UQUAD(_hw_qlnxe, OID_AUTO, rdma_configuration, CTLFLAG_RDTUN,
321 &qlnxe_rdma_configuration, 0, "RDMA Configuration");
325 SYSCTL_U64(_hw_qlnxe, OID_AUTO, rdma_configuration, CTLFLAG_RDTUN,
326 &qlnxe_rdma_configuration, 0, "RDMA Configuration");
328 #endif /* #if __FreeBSD_version < 1100000 */
331 qlnx_vf_device(qlnx_host_t *ha)
335 device_id = ha->device_id;
337 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
344 qlnx_valid_device(qlnx_host_t *ha)
348 device_id = ha->device_id;
351 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
352 (device_id == QLOGIC_PCI_DEVICE_ID_1644) ||
353 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
354 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
355 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
358 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
361 #endif /* #ifndef QLNX_VF */
365 #ifdef QLNX_ENABLE_IWARP
367 qlnx_rdma_supported(struct qlnx_host *ha)
371 device_id = pci_get_device(ha->pci_dev);
373 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
374 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
375 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
376 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
381 #endif /* #ifdef QLNX_ENABLE_IWARP */
384 * Name: qlnx_pci_probe
385 * Function: Validate the PCI device to be a QLA80XX device
388 qlnx_pci_probe(device_t dev)
390 snprintf(qlnx_ver_str, sizeof(qlnx_ver_str), "v%d.%d.%d",
391 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR, QLNX_VERSION_BUILD);
392 snprintf(qlnx_name_str, sizeof(qlnx_name_str), "qlnx");
394 if (pci_get_vendor(dev) != PCI_VENDOR_QLOGIC) {
398 switch (pci_get_device(dev)) {
402 case QLOGIC_PCI_DEVICE_ID_1644:
403 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
404 "Qlogic 100GbE PCI CNA Adapter-Ethernet Function",
405 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
407 device_set_desc_copy(dev, qlnx_dev_str);
411 case QLOGIC_PCI_DEVICE_ID_1634:
412 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
413 "Qlogic 40GbE PCI CNA Adapter-Ethernet Function",
414 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
416 device_set_desc_copy(dev, qlnx_dev_str);
420 case QLOGIC_PCI_DEVICE_ID_1656:
421 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
422 "Qlogic 25GbE PCI CNA Adapter-Ethernet Function",
423 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
425 device_set_desc_copy(dev, qlnx_dev_str);
429 case QLOGIC_PCI_DEVICE_ID_1654:
430 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
431 "Qlogic 50GbE PCI CNA Adapter-Ethernet Function",
432 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
434 device_set_desc_copy(dev, qlnx_dev_str);
438 case QLOGIC_PCI_DEVICE_ID_8070:
439 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
440 "Qlogic 10GbE/25GbE/40GbE PCI CNA (AH)"
441 " Adapter-Ethernet Function",
442 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
444 device_set_desc_copy(dev, qlnx_dev_str);
449 case QLOGIC_PCI_DEVICE_ID_8090:
450 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
451 "Qlogic SRIOV PCI CNA (AH) "
452 "Adapter-Ethernet Function",
453 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
455 device_set_desc_copy(dev, qlnx_dev_str);
459 #endif /* #ifndef QLNX_VF */
465 #ifdef QLNX_ENABLE_IWARP
467 #endif /* #ifdef QLNX_ENABLE_IWARP */
469 return (BUS_PROBE_DEFAULT);
473 qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
474 struct qlnx_tx_queue *txq)
480 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
482 ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl);
483 if (hw_bd_cons < ecore_cons_idx) {
484 diff = (1 << 16) - (ecore_cons_idx - hw_bd_cons);
486 diff = hw_bd_cons - ecore_cons_idx;
493 qlnx_sp_intr(void *arg)
495 struct ecore_hwfn *p_hwfn;
501 if (p_hwfn == NULL) {
502 printf("%s: spurious slowpath intr\n", __func__);
506 ha = (qlnx_host_t *)p_hwfn->p_dev;
508 QL_DPRINT2(ha, "enter\n");
510 for (i = 0; i < ha->cdev.num_hwfns; i++) {
511 if (&ha->cdev.hwfns[i] == p_hwfn) {
512 taskqueue_enqueue(ha->sp_taskqueue[i], &ha->sp_task[i]);
516 QL_DPRINT2(ha, "exit\n");
522 qlnx_sp_taskqueue(void *context, int pending)
524 struct ecore_hwfn *p_hwfn;
528 if (p_hwfn != NULL) {
535 qlnx_create_sp_taskqueues(qlnx_host_t *ha)
540 for (i = 0; i < ha->cdev.num_hwfns; i++) {
542 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
544 bzero(tq_name, sizeof (tq_name));
545 snprintf(tq_name, sizeof (tq_name), "ql_sp_tq_%d", i);
547 TASK_INIT(&ha->sp_task[i], 0, qlnx_sp_taskqueue, p_hwfn);
549 ha->sp_taskqueue[i] = taskqueue_create(tq_name, M_NOWAIT,
550 taskqueue_thread_enqueue, &ha->sp_taskqueue[i]);
552 if (ha->sp_taskqueue[i] == NULL)
555 taskqueue_start_threads(&ha->sp_taskqueue[i], 1, PI_NET, "%s",
558 QL_DPRINT1(ha, "%p\n", ha->sp_taskqueue[i]);
565 qlnx_destroy_sp_taskqueues(qlnx_host_t *ha)
569 for (i = 0; i < ha->cdev.num_hwfns; i++) {
570 if (ha->sp_taskqueue[i] != NULL) {
571 taskqueue_drain(ha->sp_taskqueue[i], &ha->sp_task[i]);
572 taskqueue_free(ha->sp_taskqueue[i]);
579 qlnx_fp_taskqueue(void *context, int pending)
581 struct qlnx_fastpath *fp;
590 ha = (qlnx_host_t *)fp->edev;
594 if(ifp->if_drv_flags & IFF_DRV_RUNNING) {
596 if (!drbr_empty(ifp, fp->tx_br)) {
598 if(mtx_trylock(&fp->tx_mtx)) {
600 #ifdef QLNX_TRACE_PERF_DATA
601 tx_pkts = fp->tx_pkts_transmitted;
602 tx_compl = fp->tx_pkts_completed;
605 qlnx_transmit_locked(ifp, fp, NULL);
607 #ifdef QLNX_TRACE_PERF_DATA
608 fp->tx_pkts_trans_fp +=
609 (fp->tx_pkts_transmitted - tx_pkts);
610 fp->tx_pkts_compl_fp +=
611 (fp->tx_pkts_completed - tx_compl);
613 mtx_unlock(&fp->tx_mtx);
618 QL_DPRINT2(ha, "exit \n");
623 qlnx_create_fp_taskqueues(qlnx_host_t *ha)
627 struct qlnx_fastpath *fp;
629 for (i = 0; i < ha->num_rss; i++) {
631 fp = &ha->fp_array[i];
633 bzero(tq_name, sizeof (tq_name));
634 snprintf(tq_name, sizeof (tq_name), "ql_fp_tq_%d", i);
636 TASK_INIT(&fp->fp_task, 0, qlnx_fp_taskqueue, fp);
638 fp->fp_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
639 taskqueue_thread_enqueue,
642 if (fp->fp_taskqueue == NULL)
645 taskqueue_start_threads(&fp->fp_taskqueue, 1, PI_NET, "%s",
648 QL_DPRINT1(ha, "%p\n",fp->fp_taskqueue);
655 qlnx_destroy_fp_taskqueues(qlnx_host_t *ha)
658 struct qlnx_fastpath *fp;
660 for (i = 0; i < ha->num_rss; i++) {
662 fp = &ha->fp_array[i];
664 if (fp->fp_taskqueue != NULL) {
666 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
667 taskqueue_free(fp->fp_taskqueue);
668 fp->fp_taskqueue = NULL;
675 qlnx_drain_fp_taskqueues(qlnx_host_t *ha)
678 struct qlnx_fastpath *fp;
680 for (i = 0; i < ha->num_rss; i++) {
681 fp = &ha->fp_array[i];
683 if (fp->fp_taskqueue != NULL) {
685 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
693 qlnx_get_params(qlnx_host_t *ha)
695 if ((qlnxe_queue_count < 0) || (qlnxe_queue_count > QLNX_MAX_RSS)) {
696 device_printf(ha->pci_dev, "invalid queue_count value (%d)\n",
698 qlnxe_queue_count = 0;
704 qlnx_error_recovery_taskqueue(void *context, int pending)
710 QL_DPRINT2(ha, "enter\n");
716 #ifdef QLNX_ENABLE_IWARP
717 qlnx_rdma_dev_remove(ha);
718 #endif /* #ifdef QLNX_ENABLE_IWARP */
720 qlnx_slowpath_stop(ha);
721 qlnx_slowpath_start(ha);
723 #ifdef QLNX_ENABLE_IWARP
724 qlnx_rdma_dev_add(ha);
725 #endif /* #ifdef QLNX_ENABLE_IWARP */
729 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
731 QL_DPRINT2(ha, "exit\n");
737 qlnx_create_error_recovery_taskqueue(qlnx_host_t *ha)
741 bzero(tq_name, sizeof (tq_name));
742 snprintf(tq_name, sizeof (tq_name), "ql_err_tq");
744 TASK_INIT(&ha->err_task, 0, qlnx_error_recovery_taskqueue, ha);
746 ha->err_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
747 taskqueue_thread_enqueue, &ha->err_taskqueue);
750 if (ha->err_taskqueue == NULL)
753 taskqueue_start_threads(&ha->err_taskqueue, 1, PI_NET, "%s", tq_name);
755 QL_DPRINT1(ha, "%p\n",ha->err_taskqueue);
761 qlnx_destroy_error_recovery_taskqueue(qlnx_host_t *ha)
763 if (ha->err_taskqueue != NULL) {
764 taskqueue_drain(ha->err_taskqueue, &ha->err_task);
765 taskqueue_free(ha->err_taskqueue);
768 ha->err_taskqueue = NULL;
774 * Name: qlnx_pci_attach
775 * Function: attaches the device to the operating system
778 qlnx_pci_attach(device_t dev)
780 qlnx_host_t *ha = NULL;
781 uint32_t rsrc_len_reg = 0;
782 uint32_t rsrc_len_dbells = 0;
783 uint32_t rsrc_len_msix = 0;
786 uint32_t num_sp_msix = 0;
787 uint32_t num_rdma_irqs = 0;
789 if ((ha = device_get_softc(dev)) == NULL) {
790 device_printf(dev, "cannot get softc\n");
794 memset(ha, 0, sizeof (qlnx_host_t));
796 ha->device_id = pci_get_device(dev);
798 if (qlnx_valid_device(ha) != 0) {
799 device_printf(dev, "device is not valid device\n");
802 ha->pci_func = pci_get_function(dev);
806 mtx_init(&ha->hw_lock, "qlnx_hw_lock", MTX_NETWORK_LOCK, MTX_DEF);
808 ha->flags.lock_init = 1;
810 pci_enable_busmaster(dev);
816 ha->reg_rid = PCIR_BAR(0);
817 ha->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ha->reg_rid,
820 if (ha->pci_reg == NULL) {
821 device_printf(dev, "unable to map BAR0\n");
822 goto qlnx_pci_attach_err;
825 rsrc_len_reg = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
828 ha->dbells_rid = PCIR_BAR(2);
829 rsrc_len_dbells = (uint32_t) bus_get_resource_count(dev,
832 if (rsrc_len_dbells) {
834 ha->pci_dbells = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
835 &ha->dbells_rid, RF_ACTIVE);
837 if (ha->pci_dbells == NULL) {
838 device_printf(dev, "unable to map BAR1\n");
839 goto qlnx_pci_attach_err;
841 ha->dbells_phys_addr = (uint64_t)
842 bus_get_resource_start(dev, SYS_RES_MEMORY, ha->dbells_rid);
844 ha->dbells_size = rsrc_len_dbells;
846 if (qlnx_vf_device(ha) != 0) {
847 device_printf(dev, " BAR1 size is zero\n");
848 goto qlnx_pci_attach_err;
852 ha->msix_rid = PCIR_BAR(4);
853 ha->msix_bar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
854 &ha->msix_rid, RF_ACTIVE);
856 if (ha->msix_bar == NULL) {
857 device_printf(dev, "unable to map BAR2\n");
858 goto qlnx_pci_attach_err;
861 rsrc_len_msix = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
864 ha->dbg_level = 0x0000;
866 QL_DPRINT1(ha, "\n\t\t\t"
867 "pci_dev = %p pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
868 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
869 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
870 " msix_avail = 0x%x "
871 "\n\t\t\t[ncpus = %d]\n",
872 ha->pci_dev, ha->pci_reg, rsrc_len_reg,
873 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
874 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
880 if (qlnx_alloc_parent_dma_tag(ha))
881 goto qlnx_pci_attach_err;
883 if (qlnx_alloc_tx_dma_tag(ha))
884 goto qlnx_pci_attach_err;
886 if (qlnx_alloc_rx_dma_tag(ha))
887 goto qlnx_pci_attach_err;
890 if (qlnx_init_hw(ha) != 0)
891 goto qlnx_pci_attach_err;
893 ha->flags.hw_init = 1;
897 if((pci_get_device(dev) == QLOGIC_PCI_DEVICE_ID_1644) &&
898 (qlnxe_queue_count == QLNX_DEFAULT_RSS)) {
899 qlnxe_queue_count = QLNX_MAX_RSS;
903 * Allocate MSI-x vectors
905 if (qlnx_vf_device(ha) != 0) {
907 if (qlnxe_queue_count == 0)
908 ha->num_rss = QLNX_DEFAULT_RSS;
910 ha->num_rss = qlnxe_queue_count;
912 num_sp_msix = ha->cdev.num_hwfns;
917 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_rxq);
918 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_txq);
920 if (max_rxq < max_txq)
921 ha->num_rss = max_rxq;
923 ha->num_rss = max_txq;
925 if (ha->num_rss > QLNX_MAX_VF_RSS)
926 ha->num_rss = QLNX_MAX_VF_RSS;
931 if (ha->num_rss > mp_ncpus)
932 ha->num_rss = mp_ncpus;
934 ha->num_tc = QLNX_MAX_TC;
936 ha->msix_count = pci_msix_count(dev);
938 #ifdef QLNX_ENABLE_IWARP
940 num_rdma_irqs = qlnx_rdma_get_num_irqs(ha);
942 #endif /* #ifdef QLNX_ENABLE_IWARP */
944 if (!ha->msix_count ||
945 (ha->msix_count < (num_sp_msix + 1 + num_rdma_irqs))) {
946 device_printf(dev, "%s: msix_count[%d] not enough\n", __func__,
948 goto qlnx_pci_attach_err;
951 if (ha->msix_count > (ha->num_rss + num_sp_msix + num_rdma_irqs))
952 ha->msix_count = ha->num_rss + num_sp_msix + num_rdma_irqs;
954 ha->num_rss = ha->msix_count - (num_sp_msix + num_rdma_irqs);
956 QL_DPRINT1(ha, "\n\t\t\t"
957 "pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
958 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
959 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
960 " msix_avail = 0x%x msix_alloc = 0x%x"
961 "\n\t\t\t[ncpus = %d][num_rss = 0x%x] [num_tc = 0x%x]\n",
962 ha->pci_reg, rsrc_len_reg,
963 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
964 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
965 ha->msix_count, mp_ncpus, ha->num_rss, ha->num_tc);
967 if (pci_alloc_msix(dev, &ha->msix_count)) {
968 device_printf(dev, "%s: pci_alloc_msix[%d] failed\n", __func__,
971 goto qlnx_pci_attach_err;
975 * Initialize slow path interrupt and task queue
980 if (qlnx_create_sp_taskqueues(ha) != 0)
981 goto qlnx_pci_attach_err;
983 for (i = 0; i < ha->cdev.num_hwfns; i++) {
985 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
987 ha->sp_irq_rid[i] = i + 1;
988 ha->sp_irq[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
990 (RF_ACTIVE | RF_SHAREABLE));
991 if (ha->sp_irq[i] == NULL) {
993 "could not allocate mbx interrupt\n");
994 goto qlnx_pci_attach_err;
997 if (bus_setup_intr(dev, ha->sp_irq[i],
998 (INTR_TYPE_NET | INTR_MPSAFE), NULL,
999 qlnx_sp_intr, p_hwfn, &ha->sp_handle[i])) {
1001 "could not setup slow path interrupt\n");
1002 goto qlnx_pci_attach_err;
1005 QL_DPRINT1(ha, "p_hwfn [%p] sp_irq_rid %d"
1006 " sp_irq %p sp_handle %p\n", p_hwfn,
1007 ha->sp_irq_rid[i], ha->sp_irq[i], ha->sp_handle[i]);
1012 * initialize fast path interrupt
1014 if (qlnx_create_fp_taskqueues(ha) != 0)
1015 goto qlnx_pci_attach_err;
1017 for (i = 0; i < ha->num_rss; i++) {
1018 ha->irq_vec[i].rss_idx = i;
1019 ha->irq_vec[i].ha = ha;
1020 ha->irq_vec[i].irq_rid = (1 + num_sp_msix) + i;
1022 ha->irq_vec[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1023 &ha->irq_vec[i].irq_rid,
1024 (RF_ACTIVE | RF_SHAREABLE));
1026 if (ha->irq_vec[i].irq == NULL) {
1028 "could not allocate interrupt[%d] irq_rid = %d\n",
1029 i, ha->irq_vec[i].irq_rid);
1030 goto qlnx_pci_attach_err;
1033 if (qlnx_alloc_tx_br(ha, &ha->fp_array[i])) {
1034 device_printf(dev, "could not allocate tx_br[%d]\n", i);
1035 goto qlnx_pci_attach_err;
1041 if (qlnx_vf_device(ha) != 0) {
1043 callout_init(&ha->qlnx_callout, 1);
1044 ha->flags.callout_init = 1;
1046 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1048 if (qlnx_grc_dumpsize(ha, &ha->grcdump_size[i], i) != 0)
1049 goto qlnx_pci_attach_err;
1050 if (ha->grcdump_size[i] == 0)
1051 goto qlnx_pci_attach_err;
1053 ha->grcdump_size[i] = ha->grcdump_size[i] << 2;
1054 QL_DPRINT1(ha, "grcdump_size[%d] = 0x%08x\n",
1055 i, ha->grcdump_size[i]);
1057 ha->grcdump[i] = qlnx_zalloc(ha->grcdump_size[i]);
1058 if (ha->grcdump[i] == NULL) {
1059 device_printf(dev, "grcdump alloc[%d] failed\n", i);
1060 goto qlnx_pci_attach_err;
1063 if (qlnx_idle_chk_size(ha, &ha->idle_chk_size[i], i) != 0)
1064 goto qlnx_pci_attach_err;
1065 if (ha->idle_chk_size[i] == 0)
1066 goto qlnx_pci_attach_err;
1068 ha->idle_chk_size[i] = ha->idle_chk_size[i] << 2;
1069 QL_DPRINT1(ha, "idle_chk_size[%d] = 0x%08x\n",
1070 i, ha->idle_chk_size[i]);
1072 ha->idle_chk[i] = qlnx_zalloc(ha->idle_chk_size[i]);
1074 if (ha->idle_chk[i] == NULL) {
1075 device_printf(dev, "idle_chk alloc failed\n");
1076 goto qlnx_pci_attach_err;
1080 if (qlnx_create_error_recovery_taskqueue(ha) != 0)
1081 goto qlnx_pci_attach_err;
1084 if (qlnx_slowpath_start(ha) != 0)
1085 goto qlnx_pci_attach_err;
1087 ha->flags.slowpath_start = 1;
1089 if (qlnx_vf_device(ha) != 0) {
1090 if (qlnx_get_flash_size(ha, &ha->flash_size) != 0) {
1091 qlnx_mdelay(__func__, 1000);
1092 qlnx_trigger_dump(ha);
1094 goto qlnx_pci_attach_err0;
1097 if (qlnx_get_mfw_version(ha, &mfw_ver) != 0) {
1098 qlnx_mdelay(__func__, 1000);
1099 qlnx_trigger_dump(ha);
1101 goto qlnx_pci_attach_err0;
1104 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
1105 ecore_mcp_get_mfw_ver(p_hwfn, NULL, &mfw_ver, NULL);
1108 snprintf(ha->mfw_ver, sizeof(ha->mfw_ver), "%d.%d.%d.%d",
1109 ((mfw_ver >> 24) & 0xFF), ((mfw_ver >> 16) & 0xFF),
1110 ((mfw_ver >> 8) & 0xFF), (mfw_ver & 0xFF));
1111 snprintf(ha->stormfw_ver, sizeof(ha->stormfw_ver), "%d.%d.%d.%d",
1112 FW_MAJOR_VERSION, FW_MINOR_VERSION, FW_REVISION_VERSION,
1113 FW_ENGINEERING_VERSION);
1115 QL_DPRINT1(ha, "STORM_FW version %s MFW version %s\n",
1116 ha->stormfw_ver, ha->mfw_ver);
1118 qlnx_init_ifnet(dev, ha);
1123 qlnx_add_sysctls(ha);
1125 qlnx_pci_attach_err0:
1127 * create ioctl device interface
1129 if (qlnx_vf_device(ha) != 0) {
1131 if (qlnx_make_cdev(ha)) {
1132 device_printf(dev, "%s: ql_make_cdev failed\n", __func__);
1133 goto qlnx_pci_attach_err;
1136 #ifdef QLNX_ENABLE_IWARP
1137 qlnx_rdma_dev_add(ha);
1138 #endif /* #ifdef QLNX_ENABLE_IWARP */
1142 #ifdef CONFIG_ECORE_SRIOV
1144 if (qlnx_vf_device(ha) != 0)
1145 qlnx_initialize_sriov(ha);
1147 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1148 #endif /* #ifdef QLNX_VF */
1150 QL_DPRINT2(ha, "success\n");
1154 qlnx_pci_attach_err:
1162 * Name: qlnx_pci_detach
1163 * Function: Unhooks the device from the operating system
1166 qlnx_pci_detach(device_t dev)
1168 qlnx_host_t *ha = NULL;
1170 if ((ha = device_get_softc(dev)) == NULL) {
1171 device_printf(dev, "%s: cannot get softc\n", __func__);
1175 if (qlnx_vf_device(ha) != 0) {
1176 #ifdef CONFIG_ECORE_SRIOV
1179 ret = pci_iov_detach(dev);
1181 device_printf(dev, "%s: SRIOV in use\n", __func__);
1185 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1187 #ifdef QLNX_ENABLE_IWARP
1188 if (qlnx_rdma_dev_remove(ha) != 0)
1190 #endif /* #ifdef QLNX_ENABLE_IWARP */
1202 #ifdef QLNX_ENABLE_IWARP
1205 qlnx_get_personality(uint8_t pci_func)
1207 uint8_t personality;
1209 personality = (qlnxe_rdma_configuration >>
1210 (pci_func * QLNX_PERSONALITY_BITS_PER_FUNC)) &
1211 QLNX_PERSONALIY_MASK;
1212 return (personality);
1216 qlnx_set_personality(qlnx_host_t *ha)
1218 struct ecore_hwfn *p_hwfn;
1219 uint8_t personality;
1221 p_hwfn = &ha->cdev.hwfns[0];
1223 personality = qlnx_get_personality(ha->pci_func);
1225 switch (personality) {
1227 case QLNX_PERSONALITY_DEFAULT:
1228 device_printf(ha->pci_dev, "%s: DEFAULT\n",
1230 ha->personality = ECORE_PCI_DEFAULT;
1233 case QLNX_PERSONALITY_ETH_ONLY:
1234 device_printf(ha->pci_dev, "%s: ETH_ONLY\n",
1236 ha->personality = ECORE_PCI_ETH;
1239 case QLNX_PERSONALITY_ETH_IWARP:
1240 device_printf(ha->pci_dev, "%s: ETH_IWARP\n",
1242 ha->personality = ECORE_PCI_ETH_IWARP;
1245 case QLNX_PERSONALITY_ETH_ROCE:
1246 device_printf(ha->pci_dev, "%s: ETH_ROCE\n",
1248 ha->personality = ECORE_PCI_ETH_ROCE;
1255 #endif /* #ifdef QLNX_ENABLE_IWARP */
1258 qlnx_init_hw(qlnx_host_t *ha)
1261 struct ecore_hw_prepare_params params;
1263 ecore_init_struct(&ha->cdev);
1265 /* ha->dp_module = ECORE_MSG_PROBE |
1271 ha->dp_level = ECORE_LEVEL_VERBOSE;*/
1272 //ha->dp_module = ECORE_MSG_RDMA | ECORE_MSG_INTR | ECORE_MSG_LL2;
1273 ha->dp_level = ECORE_LEVEL_NOTICE;
1274 //ha->dp_level = ECORE_LEVEL_VERBOSE;
1276 ecore_init_dp(&ha->cdev, ha->dp_module, ha->dp_level, ha->pci_dev);
1278 ha->cdev.regview = ha->pci_reg;
1280 ha->personality = ECORE_PCI_DEFAULT;
1282 if (qlnx_vf_device(ha) == 0) {
1283 ha->cdev.b_is_vf = true;
1285 if (ha->pci_dbells != NULL) {
1286 ha->cdev.doorbells = ha->pci_dbells;
1287 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1288 ha->cdev.db_size = ha->dbells_size;
1290 ha->pci_dbells = ha->pci_reg;
1293 ha->cdev.doorbells = ha->pci_dbells;
1294 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1295 ha->cdev.db_size = ha->dbells_size;
1297 #ifdef QLNX_ENABLE_IWARP
1299 if (qlnx_rdma_supported(ha) == 0)
1300 qlnx_set_personality(ha);
1302 #endif /* #ifdef QLNX_ENABLE_IWARP */
1305 QL_DPRINT2(ha, "%s: %s\n", __func__,
1306 (ha->personality == ECORE_PCI_ETH_IWARP ? "iwarp": "ethernet"));
1308 bzero(¶ms, sizeof (struct ecore_hw_prepare_params));
1310 params.personality = ha->personality;
1312 params.drv_resc_alloc = false;
1313 params.chk_reg_fifo = false;
1314 params.initiate_pf_flr = true;
1317 ecore_hw_prepare(&ha->cdev, ¶ms);
1319 qlnx_set_id(&ha->cdev, qlnx_name_str, qlnx_ver_str);
1321 QL_DPRINT1(ha, "ha = %p cdev = %p p_hwfn = %p\n",
1322 ha, &ha->cdev, &ha->cdev.hwfns[0]);
1328 qlnx_release(qlnx_host_t *ha)
1335 QL_DPRINT2(ha, "enter\n");
1337 for (i = 0; i < QLNX_MAX_HW_FUNCS; i++) {
1338 if (ha->idle_chk[i] != NULL) {
1339 free(ha->idle_chk[i], M_QLNXBUF);
1340 ha->idle_chk[i] = NULL;
1343 if (ha->grcdump[i] != NULL) {
1344 free(ha->grcdump[i], M_QLNXBUF);
1345 ha->grcdump[i] = NULL;
1349 if (ha->flags.callout_init)
1350 callout_drain(&ha->qlnx_callout);
1352 if (ha->flags.slowpath_start) {
1353 qlnx_slowpath_stop(ha);
1356 if (ha->flags.hw_init)
1357 ecore_hw_remove(&ha->cdev);
1361 if (ha->ifp != NULL)
1362 ether_ifdetach(ha->ifp);
1364 qlnx_free_tx_dma_tag(ha);
1366 qlnx_free_rx_dma_tag(ha);
1368 qlnx_free_parent_dma_tag(ha);
1370 if (qlnx_vf_device(ha) != 0) {
1371 qlnx_destroy_error_recovery_taskqueue(ha);
1374 for (i = 0; i < ha->num_rss; i++) {
1375 struct qlnx_fastpath *fp = &ha->fp_array[i];
1377 if (ha->irq_vec[i].handle) {
1378 (void)bus_teardown_intr(dev, ha->irq_vec[i].irq,
1379 ha->irq_vec[i].handle);
1382 if (ha->irq_vec[i].irq) {
1383 (void)bus_release_resource(dev, SYS_RES_IRQ,
1384 ha->irq_vec[i].irq_rid,
1385 ha->irq_vec[i].irq);
1388 qlnx_free_tx_br(ha, fp);
1390 qlnx_destroy_fp_taskqueues(ha);
1392 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1393 if (ha->sp_handle[i])
1394 (void)bus_teardown_intr(dev, ha->sp_irq[i],
1398 (void) bus_release_resource(dev, SYS_RES_IRQ,
1399 ha->sp_irq_rid[i], ha->sp_irq[i]);
1402 qlnx_destroy_sp_taskqueues(ha);
1405 pci_release_msi(dev);
1407 if (ha->flags.lock_init) {
1408 mtx_destroy(&ha->hw_lock);
1412 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->reg_rid,
1415 if (ha->dbells_size && ha->pci_dbells)
1416 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->dbells_rid,
1420 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->msix_rid,
1423 QL_DPRINT2(ha, "exit\n");
1428 qlnx_trigger_dump(qlnx_host_t *ha)
1432 if (ha->ifp != NULL)
1433 ha->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE | IFF_DRV_RUNNING);
1435 QL_DPRINT2(ha, "enter\n");
1437 if (qlnx_vf_device(ha) == 0)
1440 ha->error_recovery = 1;
1442 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1443 qlnx_grc_dump(ha, &ha->grcdump_dwords[i], i);
1444 qlnx_idle_chk(ha, &ha->idle_chk_dwords[i], i);
1447 QL_DPRINT2(ha, "exit\n");
1453 qlnx_trigger_dump_sysctl(SYSCTL_HANDLER_ARGS)
1458 err = sysctl_handle_int(oidp, &ret, 0, req);
1460 if (err || !req->newptr)
1464 ha = (qlnx_host_t *)arg1;
1465 qlnx_trigger_dump(ha);
1471 qlnx_set_tx_coalesce(SYSCTL_HANDLER_ARGS)
1473 int err, i, ret = 0, usecs = 0;
1475 struct ecore_hwfn *p_hwfn;
1476 struct qlnx_fastpath *fp;
1478 err = sysctl_handle_int(oidp, &usecs, 0, req);
1480 if (err || !req->newptr || !usecs || (usecs > 255))
1483 ha = (qlnx_host_t *)arg1;
1485 if (qlnx_vf_device(ha) == 0)
1488 for (i = 0; i < ha->num_rss; i++) {
1490 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1492 fp = &ha->fp_array[i];
1494 if (fp->txq[0]->handle != NULL) {
1495 ret = ecore_set_queue_coalesce(p_hwfn, 0,
1496 (uint16_t)usecs, fp->txq[0]->handle);
1501 ha->tx_coalesce_usecs = (uint8_t)usecs;
1507 qlnx_set_rx_coalesce(SYSCTL_HANDLER_ARGS)
1509 int err, i, ret = 0, usecs = 0;
1511 struct ecore_hwfn *p_hwfn;
1512 struct qlnx_fastpath *fp;
1514 err = sysctl_handle_int(oidp, &usecs, 0, req);
1516 if (err || !req->newptr || !usecs || (usecs > 255))
1519 ha = (qlnx_host_t *)arg1;
1521 if (qlnx_vf_device(ha) == 0)
1524 for (i = 0; i < ha->num_rss; i++) {
1526 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1528 fp = &ha->fp_array[i];
1530 if (fp->rxq->handle != NULL) {
1531 ret = ecore_set_queue_coalesce(p_hwfn, (uint16_t)usecs,
1532 0, fp->rxq->handle);
1537 ha->rx_coalesce_usecs = (uint8_t)usecs;
1543 qlnx_add_sp_stats_sysctls(qlnx_host_t *ha)
1545 struct sysctl_ctx_list *ctx;
1546 struct sysctl_oid_list *children;
1547 struct sysctl_oid *ctx_oid;
1549 ctx = device_get_sysctl_ctx(ha->pci_dev);
1550 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1552 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "spstat",
1553 CTLFLAG_RD, NULL, "spstat");
1554 children = SYSCTL_CHILDREN(ctx_oid);
1556 SYSCTL_ADD_QUAD(ctx, children,
1557 OID_AUTO, "sp_interrupts",
1558 CTLFLAG_RD, &ha->sp_interrupts,
1559 "No. of slowpath interrupts");
1565 qlnx_add_fp_stats_sysctls(qlnx_host_t *ha)
1567 struct sysctl_ctx_list *ctx;
1568 struct sysctl_oid_list *children;
1569 struct sysctl_oid_list *node_children;
1570 struct sysctl_oid *ctx_oid;
1572 uint8_t name_str[16];
1574 ctx = device_get_sysctl_ctx(ha->pci_dev);
1575 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1577 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fpstat",
1578 CTLFLAG_RD, NULL, "fpstat");
1579 children = SYSCTL_CHILDREN(ctx_oid);
1581 for (i = 0; i < ha->num_rss; i++) {
1583 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1584 snprintf(name_str, sizeof(name_str), "%d", i);
1586 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
1587 CTLFLAG_RD, NULL, name_str);
1588 node_children = SYSCTL_CHILDREN(ctx_oid);
1592 SYSCTL_ADD_QUAD(ctx, node_children,
1593 OID_AUTO, "tx_pkts_processed",
1594 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_processed,
1595 "No. of packets processed for transmission");
1597 SYSCTL_ADD_QUAD(ctx, node_children,
1598 OID_AUTO, "tx_pkts_freed",
1599 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_freed,
1600 "No. of freed packets");
1602 SYSCTL_ADD_QUAD(ctx, node_children,
1603 OID_AUTO, "tx_pkts_transmitted",
1604 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_transmitted,
1605 "No. of transmitted packets");
1607 SYSCTL_ADD_QUAD(ctx, node_children,
1608 OID_AUTO, "tx_pkts_completed",
1609 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_completed,
1610 "No. of transmit completions");
1612 SYSCTL_ADD_QUAD(ctx, node_children,
1613 OID_AUTO, "tx_non_tso_pkts",
1614 CTLFLAG_RD, &ha->fp_array[i].tx_non_tso_pkts,
1615 "No. of non LSO transmited packets");
1617 #ifdef QLNX_TRACE_PERF_DATA
1619 SYSCTL_ADD_QUAD(ctx, node_children,
1620 OID_AUTO, "tx_pkts_trans_ctx",
1621 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_ctx,
1622 "No. of transmitted packets in transmit context");
1624 SYSCTL_ADD_QUAD(ctx, node_children,
1625 OID_AUTO, "tx_pkts_compl_ctx",
1626 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_ctx,
1627 "No. of transmit completions in transmit context");
1629 SYSCTL_ADD_QUAD(ctx, node_children,
1630 OID_AUTO, "tx_pkts_trans_fp",
1631 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_fp,
1632 "No. of transmitted packets in taskqueue");
1634 SYSCTL_ADD_QUAD(ctx, node_children,
1635 OID_AUTO, "tx_pkts_compl_fp",
1636 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_fp,
1637 "No. of transmit completions in taskqueue");
1639 SYSCTL_ADD_QUAD(ctx, node_children,
1640 OID_AUTO, "tx_pkts_compl_intr",
1641 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_intr,
1642 "No. of transmit completions in interrupt ctx");
1645 SYSCTL_ADD_QUAD(ctx, node_children,
1646 OID_AUTO, "tx_tso_pkts",
1647 CTLFLAG_RD, &ha->fp_array[i].tx_tso_pkts,
1648 "No. of LSO transmited packets");
1650 SYSCTL_ADD_QUAD(ctx, node_children,
1651 OID_AUTO, "tx_lso_wnd_min_len",
1652 CTLFLAG_RD, &ha->fp_array[i].tx_lso_wnd_min_len,
1653 "tx_lso_wnd_min_len");
1655 SYSCTL_ADD_QUAD(ctx, node_children,
1656 OID_AUTO, "tx_defrag",
1657 CTLFLAG_RD, &ha->fp_array[i].tx_defrag,
1660 SYSCTL_ADD_QUAD(ctx, node_children,
1661 OID_AUTO, "tx_nsegs_gt_elem_left",
1662 CTLFLAG_RD, &ha->fp_array[i].tx_nsegs_gt_elem_left,
1663 "tx_nsegs_gt_elem_left");
1665 SYSCTL_ADD_UINT(ctx, node_children,
1666 OID_AUTO, "tx_tso_max_nsegs",
1667 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_nsegs,
1668 ha->fp_array[i].tx_tso_max_nsegs, "tx_tso_max_nsegs");
1670 SYSCTL_ADD_UINT(ctx, node_children,
1671 OID_AUTO, "tx_tso_min_nsegs",
1672 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_nsegs,
1673 ha->fp_array[i].tx_tso_min_nsegs, "tx_tso_min_nsegs");
1675 SYSCTL_ADD_UINT(ctx, node_children,
1676 OID_AUTO, "tx_tso_max_pkt_len",
1677 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_pkt_len,
1678 ha->fp_array[i].tx_tso_max_pkt_len,
1679 "tx_tso_max_pkt_len");
1681 SYSCTL_ADD_UINT(ctx, node_children,
1682 OID_AUTO, "tx_tso_min_pkt_len",
1683 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_pkt_len,
1684 ha->fp_array[i].tx_tso_min_pkt_len,
1685 "tx_tso_min_pkt_len");
1687 for (j = 0; j < QLNX_FP_MAX_SEGS; j++) {
1689 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1690 snprintf(name_str, sizeof(name_str),
1691 "tx_pkts_nseg_%02d", (j+1));
1693 SYSCTL_ADD_QUAD(ctx, node_children,
1694 OID_AUTO, name_str, CTLFLAG_RD,
1695 &ha->fp_array[i].tx_pkts[j], name_str);
1698 #ifdef QLNX_TRACE_PERF_DATA
1699 for (j = 0; j < 18; j++) {
1701 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1702 snprintf(name_str, sizeof(name_str),
1703 "tx_pkts_hist_%02d", (j+1));
1705 SYSCTL_ADD_QUAD(ctx, node_children,
1706 OID_AUTO, name_str, CTLFLAG_RD,
1707 &ha->fp_array[i].tx_pkts_hist[j], name_str);
1709 for (j = 0; j < 5; j++) {
1711 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1712 snprintf(name_str, sizeof(name_str),
1713 "tx_comInt_%02d", (j+1));
1715 SYSCTL_ADD_QUAD(ctx, node_children,
1716 OID_AUTO, name_str, CTLFLAG_RD,
1717 &ha->fp_array[i].tx_comInt[j], name_str);
1719 for (j = 0; j < 18; j++) {
1721 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1722 snprintf(name_str, sizeof(name_str),
1723 "tx_pkts_q_%02d", (j+1));
1725 SYSCTL_ADD_QUAD(ctx, node_children,
1726 OID_AUTO, name_str, CTLFLAG_RD,
1727 &ha->fp_array[i].tx_pkts_q[j], name_str);
1731 SYSCTL_ADD_QUAD(ctx, node_children,
1732 OID_AUTO, "err_tx_nsegs_gt_elem_left",
1733 CTLFLAG_RD, &ha->fp_array[i].err_tx_nsegs_gt_elem_left,
1734 "err_tx_nsegs_gt_elem_left");
1736 SYSCTL_ADD_QUAD(ctx, node_children,
1737 OID_AUTO, "err_tx_dmamap_create",
1738 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_create,
1739 "err_tx_dmamap_create");
1741 SYSCTL_ADD_QUAD(ctx, node_children,
1742 OID_AUTO, "err_tx_defrag_dmamap_load",
1743 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag_dmamap_load,
1744 "err_tx_defrag_dmamap_load");
1746 SYSCTL_ADD_QUAD(ctx, node_children,
1747 OID_AUTO, "err_tx_non_tso_max_seg",
1748 CTLFLAG_RD, &ha->fp_array[i].err_tx_non_tso_max_seg,
1749 "err_tx_non_tso_max_seg");
1751 SYSCTL_ADD_QUAD(ctx, node_children,
1752 OID_AUTO, "err_tx_dmamap_load",
1753 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_load,
1754 "err_tx_dmamap_load");
1756 SYSCTL_ADD_QUAD(ctx, node_children,
1757 OID_AUTO, "err_tx_defrag",
1758 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag,
1761 SYSCTL_ADD_QUAD(ctx, node_children,
1762 OID_AUTO, "err_tx_free_pkt_null",
1763 CTLFLAG_RD, &ha->fp_array[i].err_tx_free_pkt_null,
1764 "err_tx_free_pkt_null");
1766 SYSCTL_ADD_QUAD(ctx, node_children,
1767 OID_AUTO, "err_tx_cons_idx_conflict",
1768 CTLFLAG_RD, &ha->fp_array[i].err_tx_cons_idx_conflict,
1769 "err_tx_cons_idx_conflict");
1771 SYSCTL_ADD_QUAD(ctx, node_children,
1772 OID_AUTO, "lro_cnt_64",
1773 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_64,
1776 SYSCTL_ADD_QUAD(ctx, node_children,
1777 OID_AUTO, "lro_cnt_128",
1778 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_128,
1781 SYSCTL_ADD_QUAD(ctx, node_children,
1782 OID_AUTO, "lro_cnt_256",
1783 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_256,
1786 SYSCTL_ADD_QUAD(ctx, node_children,
1787 OID_AUTO, "lro_cnt_512",
1788 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_512,
1791 SYSCTL_ADD_QUAD(ctx, node_children,
1792 OID_AUTO, "lro_cnt_1024",
1793 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_1024,
1798 SYSCTL_ADD_QUAD(ctx, node_children,
1799 OID_AUTO, "rx_pkts",
1800 CTLFLAG_RD, &ha->fp_array[i].rx_pkts,
1801 "No. of received packets");
1803 SYSCTL_ADD_QUAD(ctx, node_children,
1804 OID_AUTO, "tpa_start",
1805 CTLFLAG_RD, &ha->fp_array[i].tpa_start,
1806 "No. of tpa_start packets");
1808 SYSCTL_ADD_QUAD(ctx, node_children,
1809 OID_AUTO, "tpa_cont",
1810 CTLFLAG_RD, &ha->fp_array[i].tpa_cont,
1811 "No. of tpa_cont packets");
1813 SYSCTL_ADD_QUAD(ctx, node_children,
1814 OID_AUTO, "tpa_end",
1815 CTLFLAG_RD, &ha->fp_array[i].tpa_end,
1816 "No. of tpa_end packets");
1818 SYSCTL_ADD_QUAD(ctx, node_children,
1819 OID_AUTO, "err_m_getcl",
1820 CTLFLAG_RD, &ha->fp_array[i].err_m_getcl,
1823 SYSCTL_ADD_QUAD(ctx, node_children,
1824 OID_AUTO, "err_m_getjcl",
1825 CTLFLAG_RD, &ha->fp_array[i].err_m_getjcl,
1828 SYSCTL_ADD_QUAD(ctx, node_children,
1829 OID_AUTO, "err_rx_hw_errors",
1830 CTLFLAG_RD, &ha->fp_array[i].err_rx_hw_errors,
1831 "err_rx_hw_errors");
1833 SYSCTL_ADD_QUAD(ctx, node_children,
1834 OID_AUTO, "err_rx_alloc_errors",
1835 CTLFLAG_RD, &ha->fp_array[i].err_rx_alloc_errors,
1836 "err_rx_alloc_errors");
1843 qlnx_add_hw_stats_sysctls(qlnx_host_t *ha)
1845 struct sysctl_ctx_list *ctx;
1846 struct sysctl_oid_list *children;
1847 struct sysctl_oid *ctx_oid;
1849 ctx = device_get_sysctl_ctx(ha->pci_dev);
1850 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1852 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "hwstat",
1853 CTLFLAG_RD, NULL, "hwstat");
1854 children = SYSCTL_CHILDREN(ctx_oid);
1856 SYSCTL_ADD_QUAD(ctx, children,
1857 OID_AUTO, "no_buff_discards",
1858 CTLFLAG_RD, &ha->hw_stats.common.no_buff_discards,
1859 "No. of packets discarded due to lack of buffer");
1861 SYSCTL_ADD_QUAD(ctx, children,
1862 OID_AUTO, "packet_too_big_discard",
1863 CTLFLAG_RD, &ha->hw_stats.common.packet_too_big_discard,
1864 "No. of packets discarded because packet was too big");
1866 SYSCTL_ADD_QUAD(ctx, children,
1867 OID_AUTO, "ttl0_discard",
1868 CTLFLAG_RD, &ha->hw_stats.common.ttl0_discard,
1871 SYSCTL_ADD_QUAD(ctx, children,
1872 OID_AUTO, "rx_ucast_bytes",
1873 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_bytes,
1876 SYSCTL_ADD_QUAD(ctx, children,
1877 OID_AUTO, "rx_mcast_bytes",
1878 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_bytes,
1881 SYSCTL_ADD_QUAD(ctx, children,
1882 OID_AUTO, "rx_bcast_bytes",
1883 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_bytes,
1886 SYSCTL_ADD_QUAD(ctx, children,
1887 OID_AUTO, "rx_ucast_pkts",
1888 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_pkts,
1891 SYSCTL_ADD_QUAD(ctx, children,
1892 OID_AUTO, "rx_mcast_pkts",
1893 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_pkts,
1896 SYSCTL_ADD_QUAD(ctx, children,
1897 OID_AUTO, "rx_bcast_pkts",
1898 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_pkts,
1901 SYSCTL_ADD_QUAD(ctx, children,
1902 OID_AUTO, "mftag_filter_discards",
1903 CTLFLAG_RD, &ha->hw_stats.common.mftag_filter_discards,
1904 "mftag_filter_discards");
1906 SYSCTL_ADD_QUAD(ctx, children,
1907 OID_AUTO, "mac_filter_discards",
1908 CTLFLAG_RD, &ha->hw_stats.common.mac_filter_discards,
1909 "mac_filter_discards");
1911 SYSCTL_ADD_QUAD(ctx, children,
1912 OID_AUTO, "tx_ucast_bytes",
1913 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_bytes,
1916 SYSCTL_ADD_QUAD(ctx, children,
1917 OID_AUTO, "tx_mcast_bytes",
1918 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_bytes,
1921 SYSCTL_ADD_QUAD(ctx, children,
1922 OID_AUTO, "tx_bcast_bytes",
1923 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_bytes,
1926 SYSCTL_ADD_QUAD(ctx, children,
1927 OID_AUTO, "tx_ucast_pkts",
1928 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_pkts,
1931 SYSCTL_ADD_QUAD(ctx, children,
1932 OID_AUTO, "tx_mcast_pkts",
1933 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_pkts,
1936 SYSCTL_ADD_QUAD(ctx, children,
1937 OID_AUTO, "tx_bcast_pkts",
1938 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_pkts,
1941 SYSCTL_ADD_QUAD(ctx, children,
1942 OID_AUTO, "tx_err_drop_pkts",
1943 CTLFLAG_RD, &ha->hw_stats.common.tx_err_drop_pkts,
1944 "tx_err_drop_pkts");
1946 SYSCTL_ADD_QUAD(ctx, children,
1947 OID_AUTO, "tpa_coalesced_pkts",
1948 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_pkts,
1949 "tpa_coalesced_pkts");
1951 SYSCTL_ADD_QUAD(ctx, children,
1952 OID_AUTO, "tpa_coalesced_events",
1953 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_events,
1954 "tpa_coalesced_events");
1956 SYSCTL_ADD_QUAD(ctx, children,
1957 OID_AUTO, "tpa_aborts_num",
1958 CTLFLAG_RD, &ha->hw_stats.common.tpa_aborts_num,
1961 SYSCTL_ADD_QUAD(ctx, children,
1962 OID_AUTO, "tpa_not_coalesced_pkts",
1963 CTLFLAG_RD, &ha->hw_stats.common.tpa_not_coalesced_pkts,
1964 "tpa_not_coalesced_pkts");
1966 SYSCTL_ADD_QUAD(ctx, children,
1967 OID_AUTO, "tpa_coalesced_bytes",
1968 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_bytes,
1969 "tpa_coalesced_bytes");
1971 SYSCTL_ADD_QUAD(ctx, children,
1972 OID_AUTO, "rx_64_byte_packets",
1973 CTLFLAG_RD, &ha->hw_stats.common.rx_64_byte_packets,
1974 "rx_64_byte_packets");
1976 SYSCTL_ADD_QUAD(ctx, children,
1977 OID_AUTO, "rx_65_to_127_byte_packets",
1978 CTLFLAG_RD, &ha->hw_stats.common.rx_65_to_127_byte_packets,
1979 "rx_65_to_127_byte_packets");
1981 SYSCTL_ADD_QUAD(ctx, children,
1982 OID_AUTO, "rx_128_to_255_byte_packets",
1983 CTLFLAG_RD, &ha->hw_stats.common.rx_128_to_255_byte_packets,
1984 "rx_128_to_255_byte_packets");
1986 SYSCTL_ADD_QUAD(ctx, children,
1987 OID_AUTO, "rx_256_to_511_byte_packets",
1988 CTLFLAG_RD, &ha->hw_stats.common.rx_256_to_511_byte_packets,
1989 "rx_256_to_511_byte_packets");
1991 SYSCTL_ADD_QUAD(ctx, children,
1992 OID_AUTO, "rx_512_to_1023_byte_packets",
1993 CTLFLAG_RD, &ha->hw_stats.common.rx_512_to_1023_byte_packets,
1994 "rx_512_to_1023_byte_packets");
1996 SYSCTL_ADD_QUAD(ctx, children,
1997 OID_AUTO, "rx_1024_to_1518_byte_packets",
1998 CTLFLAG_RD, &ha->hw_stats.common.rx_1024_to_1518_byte_packets,
1999 "rx_1024_to_1518_byte_packets");
2001 SYSCTL_ADD_QUAD(ctx, children,
2002 OID_AUTO, "rx_1519_to_1522_byte_packets",
2003 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_1522_byte_packets,
2004 "rx_1519_to_1522_byte_packets");
2006 SYSCTL_ADD_QUAD(ctx, children,
2007 OID_AUTO, "rx_1523_to_2047_byte_packets",
2008 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_2047_byte_packets,
2009 "rx_1523_to_2047_byte_packets");
2011 SYSCTL_ADD_QUAD(ctx, children,
2012 OID_AUTO, "rx_2048_to_4095_byte_packets",
2013 CTLFLAG_RD, &ha->hw_stats.bb.rx_2048_to_4095_byte_packets,
2014 "rx_2048_to_4095_byte_packets");
2016 SYSCTL_ADD_QUAD(ctx, children,
2017 OID_AUTO, "rx_4096_to_9216_byte_packets",
2018 CTLFLAG_RD, &ha->hw_stats.bb.rx_4096_to_9216_byte_packets,
2019 "rx_4096_to_9216_byte_packets");
2021 SYSCTL_ADD_QUAD(ctx, children,
2022 OID_AUTO, "rx_9217_to_16383_byte_packets",
2023 CTLFLAG_RD, &ha->hw_stats.bb.rx_9217_to_16383_byte_packets,
2024 "rx_9217_to_16383_byte_packets");
2026 SYSCTL_ADD_QUAD(ctx, children,
2027 OID_AUTO, "rx_crc_errors",
2028 CTLFLAG_RD, &ha->hw_stats.common.rx_crc_errors,
2031 SYSCTL_ADD_QUAD(ctx, children,
2032 OID_AUTO, "rx_mac_crtl_frames",
2033 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_crtl_frames,
2034 "rx_mac_crtl_frames");
2036 SYSCTL_ADD_QUAD(ctx, children,
2037 OID_AUTO, "rx_pause_frames",
2038 CTLFLAG_RD, &ha->hw_stats.common.rx_pause_frames,
2041 SYSCTL_ADD_QUAD(ctx, children,
2042 OID_AUTO, "rx_pfc_frames",
2043 CTLFLAG_RD, &ha->hw_stats.common.rx_pfc_frames,
2046 SYSCTL_ADD_QUAD(ctx, children,
2047 OID_AUTO, "rx_align_errors",
2048 CTLFLAG_RD, &ha->hw_stats.common.rx_align_errors,
2051 SYSCTL_ADD_QUAD(ctx, children,
2052 OID_AUTO, "rx_carrier_errors",
2053 CTLFLAG_RD, &ha->hw_stats.common.rx_carrier_errors,
2054 "rx_carrier_errors");
2056 SYSCTL_ADD_QUAD(ctx, children,
2057 OID_AUTO, "rx_oversize_packets",
2058 CTLFLAG_RD, &ha->hw_stats.common.rx_oversize_packets,
2059 "rx_oversize_packets");
2061 SYSCTL_ADD_QUAD(ctx, children,
2062 OID_AUTO, "rx_jabbers",
2063 CTLFLAG_RD, &ha->hw_stats.common.rx_jabbers,
2066 SYSCTL_ADD_QUAD(ctx, children,
2067 OID_AUTO, "rx_undersize_packets",
2068 CTLFLAG_RD, &ha->hw_stats.common.rx_undersize_packets,
2069 "rx_undersize_packets");
2071 SYSCTL_ADD_QUAD(ctx, children,
2072 OID_AUTO, "rx_fragments",
2073 CTLFLAG_RD, &ha->hw_stats.common.rx_fragments,
2076 SYSCTL_ADD_QUAD(ctx, children,
2077 OID_AUTO, "tx_64_byte_packets",
2078 CTLFLAG_RD, &ha->hw_stats.common.tx_64_byte_packets,
2079 "tx_64_byte_packets");
2081 SYSCTL_ADD_QUAD(ctx, children,
2082 OID_AUTO, "tx_65_to_127_byte_packets",
2083 CTLFLAG_RD, &ha->hw_stats.common.tx_65_to_127_byte_packets,
2084 "tx_65_to_127_byte_packets");
2086 SYSCTL_ADD_QUAD(ctx, children,
2087 OID_AUTO, "tx_128_to_255_byte_packets",
2088 CTLFLAG_RD, &ha->hw_stats.common.tx_128_to_255_byte_packets,
2089 "tx_128_to_255_byte_packets");
2091 SYSCTL_ADD_QUAD(ctx, children,
2092 OID_AUTO, "tx_256_to_511_byte_packets",
2093 CTLFLAG_RD, &ha->hw_stats.common.tx_256_to_511_byte_packets,
2094 "tx_256_to_511_byte_packets");
2096 SYSCTL_ADD_QUAD(ctx, children,
2097 OID_AUTO, "tx_512_to_1023_byte_packets",
2098 CTLFLAG_RD, &ha->hw_stats.common.tx_512_to_1023_byte_packets,
2099 "tx_512_to_1023_byte_packets");
2101 SYSCTL_ADD_QUAD(ctx, children,
2102 OID_AUTO, "tx_1024_to_1518_byte_packets",
2103 CTLFLAG_RD, &ha->hw_stats.common.tx_1024_to_1518_byte_packets,
2104 "tx_1024_to_1518_byte_packets");
2106 SYSCTL_ADD_QUAD(ctx, children,
2107 OID_AUTO, "tx_1519_to_2047_byte_packets",
2108 CTLFLAG_RD, &ha->hw_stats.bb.tx_1519_to_2047_byte_packets,
2109 "tx_1519_to_2047_byte_packets");
2111 SYSCTL_ADD_QUAD(ctx, children,
2112 OID_AUTO, "tx_2048_to_4095_byte_packets",
2113 CTLFLAG_RD, &ha->hw_stats.bb.tx_2048_to_4095_byte_packets,
2114 "tx_2048_to_4095_byte_packets");
2116 SYSCTL_ADD_QUAD(ctx, children,
2117 OID_AUTO, "tx_4096_to_9216_byte_packets",
2118 CTLFLAG_RD, &ha->hw_stats.bb.tx_4096_to_9216_byte_packets,
2119 "tx_4096_to_9216_byte_packets");
2121 SYSCTL_ADD_QUAD(ctx, children,
2122 OID_AUTO, "tx_9217_to_16383_byte_packets",
2123 CTLFLAG_RD, &ha->hw_stats.bb.tx_9217_to_16383_byte_packets,
2124 "tx_9217_to_16383_byte_packets");
2126 SYSCTL_ADD_QUAD(ctx, children,
2127 OID_AUTO, "tx_pause_frames",
2128 CTLFLAG_RD, &ha->hw_stats.common.tx_pause_frames,
2131 SYSCTL_ADD_QUAD(ctx, children,
2132 OID_AUTO, "tx_pfc_frames",
2133 CTLFLAG_RD, &ha->hw_stats.common.tx_pfc_frames,
2136 SYSCTL_ADD_QUAD(ctx, children,
2137 OID_AUTO, "tx_lpi_entry_count",
2138 CTLFLAG_RD, &ha->hw_stats.bb.tx_lpi_entry_count,
2139 "tx_lpi_entry_count");
2141 SYSCTL_ADD_QUAD(ctx, children,
2142 OID_AUTO, "tx_total_collisions",
2143 CTLFLAG_RD, &ha->hw_stats.bb.tx_total_collisions,
2144 "tx_total_collisions");
2146 SYSCTL_ADD_QUAD(ctx, children,
2147 OID_AUTO, "brb_truncates",
2148 CTLFLAG_RD, &ha->hw_stats.common.brb_truncates,
2151 SYSCTL_ADD_QUAD(ctx, children,
2152 OID_AUTO, "brb_discards",
2153 CTLFLAG_RD, &ha->hw_stats.common.brb_discards,
2156 SYSCTL_ADD_QUAD(ctx, children,
2157 OID_AUTO, "rx_mac_bytes",
2158 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bytes,
2161 SYSCTL_ADD_QUAD(ctx, children,
2162 OID_AUTO, "rx_mac_uc_packets",
2163 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_uc_packets,
2164 "rx_mac_uc_packets");
2166 SYSCTL_ADD_QUAD(ctx, children,
2167 OID_AUTO, "rx_mac_mc_packets",
2168 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_mc_packets,
2169 "rx_mac_mc_packets");
2171 SYSCTL_ADD_QUAD(ctx, children,
2172 OID_AUTO, "rx_mac_bc_packets",
2173 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bc_packets,
2174 "rx_mac_bc_packets");
2176 SYSCTL_ADD_QUAD(ctx, children,
2177 OID_AUTO, "rx_mac_frames_ok",
2178 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_frames_ok,
2179 "rx_mac_frames_ok");
2181 SYSCTL_ADD_QUAD(ctx, children,
2182 OID_AUTO, "tx_mac_bytes",
2183 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bytes,
2186 SYSCTL_ADD_QUAD(ctx, children,
2187 OID_AUTO, "tx_mac_uc_packets",
2188 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_uc_packets,
2189 "tx_mac_uc_packets");
2191 SYSCTL_ADD_QUAD(ctx, children,
2192 OID_AUTO, "tx_mac_mc_packets",
2193 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_mc_packets,
2194 "tx_mac_mc_packets");
2196 SYSCTL_ADD_QUAD(ctx, children,
2197 OID_AUTO, "tx_mac_bc_packets",
2198 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bc_packets,
2199 "tx_mac_bc_packets");
2201 SYSCTL_ADD_QUAD(ctx, children,
2202 OID_AUTO, "tx_mac_ctrl_frames",
2203 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_ctrl_frames,
2204 "tx_mac_ctrl_frames");
2209 qlnx_add_sysctls(qlnx_host_t *ha)
2211 device_t dev = ha->pci_dev;
2212 struct sysctl_ctx_list *ctx;
2213 struct sysctl_oid_list *children;
2215 ctx = device_get_sysctl_ctx(dev);
2216 children = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
2218 qlnx_add_fp_stats_sysctls(ha);
2219 qlnx_add_sp_stats_sysctls(ha);
2221 if (qlnx_vf_device(ha) != 0)
2222 qlnx_add_hw_stats_sysctls(ha);
2224 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "Driver_Version",
2225 CTLFLAG_RD, qlnx_ver_str, 0,
2228 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "STORMFW_Version",
2229 CTLFLAG_RD, ha->stormfw_ver, 0,
2230 "STORM Firmware Version");
2232 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "MFW_Version",
2233 CTLFLAG_RD, ha->mfw_ver, 0,
2234 "Management Firmware Version");
2236 SYSCTL_ADD_UINT(ctx, children,
2237 OID_AUTO, "personality", CTLFLAG_RD,
2238 &ha->personality, ha->personality,
2239 "\tpersonality = 0 => Ethernet Only\n"
2240 "\tpersonality = 3 => Ethernet and RoCE\n"
2241 "\tpersonality = 4 => Ethernet and iWARP\n"
2242 "\tpersonality = 6 => Default in Shared Memory\n");
2245 SYSCTL_ADD_UINT(ctx, children,
2246 OID_AUTO, "debug", CTLFLAG_RW,
2247 &ha->dbg_level, ha->dbg_level, "Debug Level");
2249 ha->dp_level = 0x01;
2250 SYSCTL_ADD_UINT(ctx, children,
2251 OID_AUTO, "dp_level", CTLFLAG_RW,
2252 &ha->dp_level, ha->dp_level, "DP Level");
2254 ha->dbg_trace_lro_cnt = 0;
2255 SYSCTL_ADD_UINT(ctx, children,
2256 OID_AUTO, "dbg_trace_lro_cnt", CTLFLAG_RW,
2257 &ha->dbg_trace_lro_cnt, ha->dbg_trace_lro_cnt,
2258 "Trace LRO Counts");
2260 ha->dbg_trace_tso_pkt_len = 0;
2261 SYSCTL_ADD_UINT(ctx, children,
2262 OID_AUTO, "dbg_trace_tso_pkt_len", CTLFLAG_RW,
2263 &ha->dbg_trace_tso_pkt_len, ha->dbg_trace_tso_pkt_len,
2264 "Trace TSO packet lengths");
2267 SYSCTL_ADD_UINT(ctx, children,
2268 OID_AUTO, "dp_module", CTLFLAG_RW,
2269 &ha->dp_module, ha->dp_module, "DP Module");
2273 SYSCTL_ADD_UINT(ctx, children,
2274 OID_AUTO, "err_inject", CTLFLAG_RW,
2275 &ha->err_inject, ha->err_inject, "Error Inject");
2277 ha->storm_stats_enable = 0;
2279 SYSCTL_ADD_UINT(ctx, children,
2280 OID_AUTO, "storm_stats_enable", CTLFLAG_RW,
2281 &ha->storm_stats_enable, ha->storm_stats_enable,
2282 "Enable Storm Statistics Gathering");
2284 ha->storm_stats_index = 0;
2286 SYSCTL_ADD_UINT(ctx, children,
2287 OID_AUTO, "storm_stats_index", CTLFLAG_RD,
2288 &ha->storm_stats_index, ha->storm_stats_index,
2289 "Enable Storm Statistics Gathering Current Index");
2291 ha->grcdump_taken = 0;
2292 SYSCTL_ADD_UINT(ctx, children,
2293 OID_AUTO, "grcdump_taken", CTLFLAG_RD,
2294 &ha->grcdump_taken, ha->grcdump_taken,
2297 ha->idle_chk_taken = 0;
2298 SYSCTL_ADD_UINT(ctx, children,
2299 OID_AUTO, "idle_chk_taken", CTLFLAG_RD,
2300 &ha->idle_chk_taken, ha->idle_chk_taken,
2303 SYSCTL_ADD_UINT(ctx, children,
2304 OID_AUTO, "rx_coalesce_usecs", CTLFLAG_RD,
2305 &ha->rx_coalesce_usecs, ha->rx_coalesce_usecs,
2306 "rx_coalesce_usecs");
2308 SYSCTL_ADD_UINT(ctx, children,
2309 OID_AUTO, "tx_coalesce_usecs", CTLFLAG_RD,
2310 &ha->tx_coalesce_usecs, ha->tx_coalesce_usecs,
2311 "tx_coalesce_usecs");
2313 SYSCTL_ADD_PROC(ctx, children,
2314 OID_AUTO, "trigger_dump", (CTLTYPE_INT | CTLFLAG_RW),
2316 qlnx_trigger_dump_sysctl, "I", "trigger_dump");
2318 SYSCTL_ADD_PROC(ctx, children,
2319 OID_AUTO, "set_rx_coalesce_usecs",
2320 (CTLTYPE_INT | CTLFLAG_RW),
2322 qlnx_set_rx_coalesce, "I",
2323 "rx interrupt coalesce period microseconds");
2325 SYSCTL_ADD_PROC(ctx, children,
2326 OID_AUTO, "set_tx_coalesce_usecs",
2327 (CTLTYPE_INT | CTLFLAG_RW),
2329 qlnx_set_tx_coalesce, "I",
2330 "tx interrupt coalesce period microseconds");
2332 ha->rx_pkt_threshold = 128;
2333 SYSCTL_ADD_UINT(ctx, children,
2334 OID_AUTO, "rx_pkt_threshold", CTLFLAG_RW,
2335 &ha->rx_pkt_threshold, ha->rx_pkt_threshold,
2336 "No. of Rx Pkts to process at a time");
2338 ha->rx_jumbo_buf_eq_mtu = 0;
2339 SYSCTL_ADD_UINT(ctx, children,
2340 OID_AUTO, "rx_jumbo_buf_eq_mtu", CTLFLAG_RW,
2341 &ha->rx_jumbo_buf_eq_mtu, ha->rx_jumbo_buf_eq_mtu,
2342 "== 0 => Rx Jumbo buffers are capped to 4Kbytes\n"
2343 "otherwise Rx Jumbo buffers are set to >= MTU size\n");
2345 SYSCTL_ADD_QUAD(ctx, children,
2346 OID_AUTO, "err_illegal_intr", CTLFLAG_RD,
2347 &ha->err_illegal_intr, "err_illegal_intr");
2349 SYSCTL_ADD_QUAD(ctx, children,
2350 OID_AUTO, "err_fp_null", CTLFLAG_RD,
2351 &ha->err_fp_null, "err_fp_null");
2353 SYSCTL_ADD_QUAD(ctx, children,
2354 OID_AUTO, "err_get_proto_invalid_type", CTLFLAG_RD,
2355 &ha->err_get_proto_invalid_type, "err_get_proto_invalid_type");
2361 /*****************************************************************************
2362 * Operating System Network Interface Functions
2363 *****************************************************************************/
2366 qlnx_init_ifnet(device_t dev, qlnx_host_t *ha)
2371 ifp = ha->ifp = if_alloc(IFT_ETHER);
2374 panic("%s: cannot if_alloc()\n", device_get_nameunit(dev));
2376 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2378 device_id = pci_get_device(ha->pci_dev);
2380 #if __FreeBSD_version >= 1000000
2382 if (device_id == QLOGIC_PCI_DEVICE_ID_1634)
2383 ifp->if_baudrate = IF_Gbps(40);
2384 else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2385 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
2386 ifp->if_baudrate = IF_Gbps(25);
2387 else if (device_id == QLOGIC_PCI_DEVICE_ID_1654)
2388 ifp->if_baudrate = IF_Gbps(50);
2389 else if (device_id == QLOGIC_PCI_DEVICE_ID_1644)
2390 ifp->if_baudrate = IF_Gbps(100);
2392 ifp->if_capabilities = IFCAP_LINKSTATE;
2394 ifp->if_mtu = ETHERMTU;
2395 ifp->if_baudrate = (1 * 1000 * 1000 *1000);
2397 #endif /* #if __FreeBSD_version >= 1000000 */
2399 ifp->if_init = qlnx_init;
2401 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2402 ifp->if_ioctl = qlnx_ioctl;
2403 ifp->if_transmit = qlnx_transmit;
2404 ifp->if_qflush = qlnx_qflush;
2406 IFQ_SET_MAXLEN(&ifp->if_snd, qlnx_get_ifq_snd_maxlen(ha));
2407 ifp->if_snd.ifq_drv_maxlen = qlnx_get_ifq_snd_maxlen(ha);
2408 IFQ_SET_READY(&ifp->if_snd);
2410 #if __FreeBSD_version >= 1100036
2411 if_setgetcounterfn(ifp, qlnx_get_counter);
2414 ha->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2416 memcpy(ha->primary_mac, qlnx_get_mac_addr(ha), ETH_ALEN);
2418 if (!ha->primary_mac[0] && !ha->primary_mac[1] &&
2419 !ha->primary_mac[2] && !ha->primary_mac[3] &&
2420 !ha->primary_mac[4] && !ha->primary_mac[5]) {
2425 ha->primary_mac[0] = 0x00;
2426 ha->primary_mac[1] = 0x0e;
2427 ha->primary_mac[2] = 0x1e;
2428 ha->primary_mac[3] = rnd & 0xFF;
2429 ha->primary_mac[4] = (rnd >> 8) & 0xFF;
2430 ha->primary_mac[5] = (rnd >> 16) & 0xFF;
2433 ether_ifattach(ifp, ha->primary_mac);
2434 bcopy(IF_LLADDR(ha->ifp), ha->primary_mac, ETHER_ADDR_LEN);
2436 ifp->if_capabilities = IFCAP_HWCSUM;
2437 ifp->if_capabilities |= IFCAP_JUMBO_MTU;
2439 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2440 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
2441 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
2442 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2443 ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
2444 ifp->if_capabilities |= IFCAP_TSO4;
2445 ifp->if_capabilities |= IFCAP_TSO6;
2446 ifp->if_capabilities |= IFCAP_LRO;
2448 ifp->if_hw_tsomax = QLNX_MAX_TSO_FRAME_SIZE -
2449 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2450 ifp->if_hw_tsomaxsegcount = QLNX_MAX_SEGMENTS - 1 /* hdr */;
2451 ifp->if_hw_tsomaxsegsize = QLNX_MAX_TX_MBUF_SIZE;
2454 ifp->if_capenable = ifp->if_capabilities;
2456 ifp->if_hwassist = CSUM_IP;
2457 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
2458 ifp->if_hwassist |= CSUM_TCP_IPV6 | CSUM_UDP_IPV6;
2459 ifp->if_hwassist |= CSUM_TSO;
2461 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2463 ifmedia_init(&ha->media, IFM_IMASK, qlnx_media_change,\
2466 if (device_id == QLOGIC_PCI_DEVICE_ID_1634) {
2467 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_LR4), 0, NULL);
2468 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_SR4), 0, NULL);
2469 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_CR4), 0, NULL);
2470 } else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2471 (device_id == QLOGIC_PCI_DEVICE_ID_8070)) {
2472 ifmedia_add(&ha->media, (IFM_ETHER | QLNX_IFM_25G_SR), 0, NULL);
2473 ifmedia_add(&ha->media, (IFM_ETHER | QLNX_IFM_25G_CR), 0, NULL);
2474 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1654) {
2475 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_KR2), 0, NULL);
2476 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_CR2), 0, NULL);
2477 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1644) {
2478 ifmedia_add(&ha->media,
2479 (IFM_ETHER | QLNX_IFM_100G_LR4), 0, NULL);
2480 ifmedia_add(&ha->media,
2481 (IFM_ETHER | QLNX_IFM_100G_SR4), 0, NULL);
2482 ifmedia_add(&ha->media,
2483 (IFM_ETHER | QLNX_IFM_100G_CR4), 0, NULL);
2486 ifmedia_add(&ha->media, (IFM_ETHER | IFM_FDX), 0, NULL);
2487 ifmedia_add(&ha->media, (IFM_ETHER | IFM_AUTO), 0, NULL);
2490 ifmedia_set(&ha->media, (IFM_ETHER | IFM_AUTO));
2492 QL_DPRINT2(ha, "exit\n");
2498 qlnx_init_locked(qlnx_host_t *ha)
2500 struct ifnet *ifp = ha->ifp;
2502 QL_DPRINT1(ha, "Driver Initialization start \n");
2506 if (qlnx_load(ha) == 0) {
2508 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2509 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2511 #ifdef QLNX_ENABLE_IWARP
2512 if (qlnx_vf_device(ha) != 0) {
2513 qlnx_rdma_dev_open(ha);
2515 #endif /* #ifdef QLNX_ENABLE_IWARP */
2522 qlnx_init(void *arg)
2526 ha = (qlnx_host_t *)arg;
2528 QL_DPRINT2(ha, "enter\n");
2531 qlnx_init_locked(ha);
2534 QL_DPRINT2(ha, "exit\n");
2540 qlnx_config_mcast_mac_addr(qlnx_host_t *ha, uint8_t *mac_addr, uint32_t add_mac)
2542 struct ecore_filter_mcast *mcast;
2543 struct ecore_dev *cdev;
2548 mcast = &ha->ecore_mcast;
2549 bzero(mcast, sizeof(struct ecore_filter_mcast));
2552 mcast->opcode = ECORE_FILTER_ADD;
2554 mcast->opcode = ECORE_FILTER_REMOVE;
2556 mcast->num_mc_addrs = 1;
2557 memcpy(mcast->mac, mac_addr, ETH_ALEN);
2559 rc = ecore_filter_mcast_cmd(cdev, mcast, ECORE_SPQ_MODE_CB, NULL);
2565 qlnx_hw_add_mcast(qlnx_host_t *ha, uint8_t *mta)
2569 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2571 if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0)
2572 return 0; /* its been already added */
2575 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2577 if ((ha->mcast[i].addr[0] == 0) &&
2578 (ha->mcast[i].addr[1] == 0) &&
2579 (ha->mcast[i].addr[2] == 0) &&
2580 (ha->mcast[i].addr[3] == 0) &&
2581 (ha->mcast[i].addr[4] == 0) &&
2582 (ha->mcast[i].addr[5] == 0)) {
2584 if (qlnx_config_mcast_mac_addr(ha, mta, 1))
2587 bcopy(mta, ha->mcast[i].addr, ETH_ALEN);
2597 qlnx_hw_del_mcast(qlnx_host_t *ha, uint8_t *mta)
2601 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2602 if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) {
2604 if (qlnx_config_mcast_mac_addr(ha, mta, 0))
2607 ha->mcast[i].addr[0] = 0;
2608 ha->mcast[i].addr[1] = 0;
2609 ha->mcast[i].addr[2] = 0;
2610 ha->mcast[i].addr[3] = 0;
2611 ha->mcast[i].addr[4] = 0;
2612 ha->mcast[i].addr[5] = 0;
2623 * Name: qls_hw_set_multi
2624 * Function: Sets the Multicast Addresses provided the host O.S into the
2625 * hardware (for the given interface)
2628 qlnx_hw_set_multi(qlnx_host_t *ha, uint8_t *mta, uint32_t mcnt,
2633 for (i = 0; i < mcnt; i++) {
2635 if (qlnx_hw_add_mcast(ha, mta))
2638 if (qlnx_hw_del_mcast(ha, mta))
2642 mta += ETHER_HDR_LEN;
2648 #define QLNX_MCAST_ADDRS_SIZE (QLNX_MAX_NUM_MULTICAST_ADDRS * ETHER_HDR_LEN)
2650 qlnx_set_multi(qlnx_host_t *ha, uint32_t add_multi)
2652 uint8_t mta[QLNX_MCAST_ADDRS_SIZE];
2653 struct ifmultiaddr *ifma;
2655 struct ifnet *ifp = ha->ifp;
2658 if (qlnx_vf_device(ha) == 0)
2661 if_maddr_rlock(ifp);
2663 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2665 if (ifma->ifma_addr->sa_family != AF_LINK)
2668 if (mcnt == QLNX_MAX_NUM_MULTICAST_ADDRS)
2671 bcopy(LLADDR((struct sockaddr_dl *) ifma->ifma_addr),
2672 &mta[mcnt * ETHER_HDR_LEN], ETHER_HDR_LEN);
2677 if_maddr_runlock(ifp);
2680 qlnx_hw_set_multi(ha, mta, mcnt, add_multi);
2687 qlnx_set_promisc(qlnx_host_t *ha)
2692 if (qlnx_vf_device(ha) == 0)
2695 filter = ha->filter;
2696 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
2697 filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
2699 rc = qlnx_set_rx_accept_filter(ha, filter);
2704 qlnx_set_allmulti(qlnx_host_t *ha)
2709 if (qlnx_vf_device(ha) == 0)
2712 filter = ha->filter;
2713 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
2714 rc = qlnx_set_rx_accept_filter(ha, filter);
2721 qlnx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2724 struct ifreq *ifr = (struct ifreq *)data;
2725 struct ifaddr *ifa = (struct ifaddr *)data;
2728 ha = (qlnx_host_t *)ifp->if_softc;
2732 QL_DPRINT4(ha, "SIOCSIFADDR (0x%lx)\n", cmd);
2734 if (ifa->ifa_addr->sa_family == AF_INET) {
2735 ifp->if_flags |= IFF_UP;
2736 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2738 qlnx_init_locked(ha);
2741 QL_DPRINT4(ha, "SIOCSIFADDR (0x%lx) ipv4 [0x%08x]\n",
2742 cmd, ntohl(IA_SIN(ifa)->sin_addr.s_addr));
2744 arp_ifinit(ifp, ifa);
2746 ether_ioctl(ifp, cmd, data);
2751 QL_DPRINT4(ha, "SIOCSIFMTU (0x%lx)\n", cmd);
2753 if (ifr->ifr_mtu > QLNX_MAX_MTU) {
2757 ifp->if_mtu = ifr->ifr_mtu;
2758 ha->max_frame_size =
2759 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2760 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2761 qlnx_init_locked(ha);
2770 QL_DPRINT4(ha, "SIOCSIFFLAGS (0x%lx)\n", cmd);
2774 if (ifp->if_flags & IFF_UP) {
2775 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2776 if ((ifp->if_flags ^ ha->if_flags) &
2778 ret = qlnx_set_promisc(ha);
2779 } else if ((ifp->if_flags ^ ha->if_flags) &
2781 ret = qlnx_set_allmulti(ha);
2784 ha->max_frame_size = ifp->if_mtu +
2785 ETHER_HDR_LEN + ETHER_CRC_LEN;
2786 qlnx_init_locked(ha);
2789 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2791 ha->if_flags = ifp->if_flags;
2798 QL_DPRINT4(ha, "%s (0x%lx)\n", "SIOCADDMULTI", cmd);
2800 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2801 if (qlnx_set_multi(ha, 1))
2807 QL_DPRINT4(ha, "%s (0x%lx)\n", "SIOCDELMULTI", cmd);
2809 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2810 if (qlnx_set_multi(ha, 0))
2817 QL_DPRINT4(ha, "SIOCSIFMEDIA/SIOCGIFMEDIA (0x%lx)\n", cmd);
2819 ret = ifmedia_ioctl(ifp, ifr, &ha->media, cmd);
2824 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2826 QL_DPRINT4(ha, "SIOCSIFCAP (0x%lx)\n", cmd);
2828 if (mask & IFCAP_HWCSUM)
2829 ifp->if_capenable ^= IFCAP_HWCSUM;
2830 if (mask & IFCAP_TSO4)
2831 ifp->if_capenable ^= IFCAP_TSO4;
2832 if (mask & IFCAP_TSO6)
2833 ifp->if_capenable ^= IFCAP_TSO6;
2834 if (mask & IFCAP_VLAN_HWTAGGING)
2835 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2836 if (mask & IFCAP_VLAN_HWTSO)
2837 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2838 if (mask & IFCAP_LRO)
2839 ifp->if_capenable ^= IFCAP_LRO;
2843 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2844 qlnx_init_locked(ha);
2848 VLAN_CAPABILITIES(ifp);
2851 #if (__FreeBSD_version >= 1100101)
2855 struct ifi2creq i2c;
2856 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
2857 struct ecore_ptt *p_ptt;
2859 ret = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2864 if ((i2c.len > sizeof (i2c.data)) ||
2865 (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2)) {
2870 p_ptt = ecore_ptt_acquire(p_hwfn);
2873 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
2878 ret = ecore_mcp_phy_sfp_read(p_hwfn, p_ptt,
2879 (ha->pci_func & 0x1), i2c.dev_addr, i2c.offset,
2880 i2c.len, &i2c.data[0]);
2882 ecore_ptt_release(p_hwfn, p_ptt);
2889 ret = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2891 QL_DPRINT8(ha, "SIOCGI2C copyout ret = %d \
2892 len = %d addr = 0x%02x offset = 0x%04x \
2893 data[0..7]=0x%02x 0x%02x 0x%02x 0x%02x 0x%02x \
2894 0x%02x 0x%02x 0x%02x\n",
2895 ret, i2c.len, i2c.dev_addr, i2c.offset,
2896 i2c.data[0], i2c.data[1], i2c.data[2], i2c.data[3],
2897 i2c.data[4], i2c.data[5], i2c.data[6], i2c.data[7]);
2900 #endif /* #if (__FreeBSD_version >= 1100101) */
2903 QL_DPRINT4(ha, "default (0x%lx)\n", cmd);
2904 ret = ether_ioctl(ifp, cmd, data);
2912 qlnx_media_change(struct ifnet *ifp)
2915 struct ifmedia *ifm;
2918 ha = (qlnx_host_t *)ifp->if_softc;
2920 QL_DPRINT2(ha, "enter\n");
2924 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2927 QL_DPRINT2(ha, "exit\n");
2933 qlnx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2937 ha = (qlnx_host_t *)ifp->if_softc;
2939 QL_DPRINT2(ha, "enter\n");
2941 ifmr->ifm_status = IFM_AVALID;
2942 ifmr->ifm_active = IFM_ETHER;
2945 ifmr->ifm_status |= IFM_ACTIVE;
2947 (IFM_FDX | qlnx_get_optics(ha, &ha->if_link));
2949 if (ha->if_link.link_partner_caps &
2950 (QLNX_LINK_CAP_Pause | QLNX_LINK_CAP_Asym_Pause))
2952 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
2955 QL_DPRINT2(ha, "exit (%s)\n", (ha->link_up ? "link_up" : "link_down"));
2962 qlnx_free_tx_pkt(qlnx_host_t *ha, struct qlnx_fastpath *fp,
2963 struct qlnx_tx_queue *txq)
2969 struct eth_tx_bd *tx_data_bd;
2970 struct eth_tx_1st_bd *first_bd;
2973 idx = txq->sw_tx_cons;
2974 mp = txq->sw_tx_ring[idx].mp;
2975 map = txq->sw_tx_ring[idx].map;
2977 if ((mp == NULL) || QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL)){
2979 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL);
2981 QL_DPRINT1(ha, "(mp == NULL) "
2983 " ecore_prod_idx = 0x%x"
2984 " ecore_cons_idx = 0x%x"
2985 " hw_bd_cons = 0x%x"
2986 " txq_db_last = 0x%x"
2987 " elem_left = 0x%x\n",
2989 ecore_chain_get_prod_idx(&txq->tx_pbl),
2990 ecore_chain_get_cons_idx(&txq->tx_pbl),
2991 le16toh(*txq->hw_cons_ptr),
2993 ecore_chain_get_elem_left(&txq->tx_pbl));
2995 fp->err_tx_free_pkt_null++;
2998 qlnx_trigger_dump(ha);
3003 QLNX_INC_OPACKETS((ha->ifp));
3004 QLNX_INC_OBYTES((ha->ifp), (mp->m_pkthdr.len));
3006 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_POSTWRITE);
3007 bus_dmamap_unload(ha->tx_tag, map);
3009 fp->tx_pkts_freed++;
3010 fp->tx_pkts_completed++;
3015 first_bd = (struct eth_tx_1st_bd *)ecore_chain_consume(&txq->tx_pbl);
3016 nbds = first_bd->data.nbds;
3018 // BD_SET_UNMAP_ADDR_LEN(first_bd, 0, 0);
3020 for (i = 1; i < nbds; i++) {
3021 tx_data_bd = ecore_chain_consume(&txq->tx_pbl);
3022 // BD_SET_UNMAP_ADDR_LEN(tx_data_bd, 0, 0);
3024 txq->sw_tx_ring[idx].flags = 0;
3025 txq->sw_tx_ring[idx].mp = NULL;
3026 txq->sw_tx_ring[idx].map = (bus_dmamap_t)0;
3032 qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
3033 struct qlnx_tx_queue *txq)
3040 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
3042 while (hw_bd_cons !=
3043 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
3045 if (hw_bd_cons < ecore_cons_idx) {
3046 diff = (1 << 16) - (ecore_cons_idx - hw_bd_cons);
3048 diff = hw_bd_cons - ecore_cons_idx;
3050 if ((diff > TX_RING_SIZE) ||
3051 QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF)){
3053 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF);
3055 QL_DPRINT1(ha, "(diff = 0x%x) "
3057 " ecore_prod_idx = 0x%x"
3058 " ecore_cons_idx = 0x%x"
3059 " hw_bd_cons = 0x%x"
3060 " txq_db_last = 0x%x"
3061 " elem_left = 0x%x\n",
3064 ecore_chain_get_prod_idx(&txq->tx_pbl),
3065 ecore_chain_get_cons_idx(&txq->tx_pbl),
3066 le16toh(*txq->hw_cons_ptr),
3068 ecore_chain_get_elem_left(&txq->tx_pbl));
3070 fp->err_tx_cons_idx_conflict++;
3073 qlnx_trigger_dump(ha);
3076 idx = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
3077 idx2 = (txq->sw_tx_cons + 2) & (TX_RING_SIZE - 1);
3078 prefetch(txq->sw_tx_ring[idx].mp);
3079 prefetch(txq->sw_tx_ring[idx2].mp);
3081 qlnx_free_tx_pkt(ha, fp, txq);
3083 txq->sw_tx_cons = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
3089 qlnx_transmit_locked(struct ifnet *ifp,struct qlnx_fastpath *fp, struct mbuf *mp)
3092 struct qlnx_tx_queue *txq;
3097 ha = (qlnx_host_t *)fp->edev;
3100 if ((!(ifp->if_drv_flags & IFF_DRV_RUNNING)) || (!ha->link_up)) {
3102 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3107 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3109 mp = drbr_peek(ifp, fp->tx_br);
3111 while (mp != NULL) {
3113 if (qlnx_send(ha, fp, &mp)) {
3116 drbr_putback(ifp, fp->tx_br, mp);
3118 fp->tx_pkts_processed++;
3119 drbr_advance(ifp, fp->tx_br);
3121 goto qlnx_transmit_locked_exit;
3124 drbr_advance(ifp, fp->tx_br);
3125 fp->tx_pkts_transmitted++;
3126 fp->tx_pkts_processed++;
3129 mp = drbr_peek(ifp, fp->tx_br);
3132 qlnx_transmit_locked_exit:
3133 if((qlnx_num_tx_compl(ha,fp, fp->txq[0]) > QLNX_TX_COMPL_THRESH) ||
3134 ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))
3135 < QLNX_TX_ELEM_MAX_THRESH))
3136 (void)qlnx_tx_int(ha, fp, fp->txq[0]);
3138 QL_DPRINT2(ha, "%s: exit ret = %d\n", __func__, ret);
3144 qlnx_transmit(struct ifnet *ifp, struct mbuf *mp)
3146 qlnx_host_t *ha = (qlnx_host_t *)ifp->if_softc;
3147 struct qlnx_fastpath *fp;
3148 int rss_id = 0, ret = 0;
3150 #ifdef QLNX_TRACEPERF_DATA
3151 uint64_t tx_pkts = 0, tx_compl = 0;
3154 QL_DPRINT2(ha, "enter\n");
3156 #if __FreeBSD_version >= 1100000
3157 if (M_HASHTYPE_GET(mp) != M_HASHTYPE_NONE)
3159 if (mp->m_flags & M_FLOWID)
3161 rss_id = (mp->m_pkthdr.flowid % ECORE_RSS_IND_TABLE_SIZE) %
3164 fp = &ha->fp_array[rss_id];
3166 if (fp->tx_br == NULL) {
3168 goto qlnx_transmit_exit;
3171 if (mtx_trylock(&fp->tx_mtx)) {
3173 #ifdef QLNX_TRACEPERF_DATA
3174 tx_pkts = fp->tx_pkts_transmitted;
3175 tx_compl = fp->tx_pkts_completed;
3178 ret = qlnx_transmit_locked(ifp, fp, mp);
3180 #ifdef QLNX_TRACEPERF_DATA
3181 fp->tx_pkts_trans_ctx += (fp->tx_pkts_transmitted - tx_pkts);
3182 fp->tx_pkts_compl_ctx += (fp->tx_pkts_completed - tx_compl);
3184 mtx_unlock(&fp->tx_mtx);
3186 if (mp != NULL && (fp->fp_taskqueue != NULL)) {
3187 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3188 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);
3194 QL_DPRINT2(ha, "exit ret = %d\n", ret);
3199 qlnx_qflush(struct ifnet *ifp)
3202 struct qlnx_fastpath *fp;
3206 ha = (qlnx_host_t *)ifp->if_softc;
3208 QL_DPRINT2(ha, "enter\n");
3210 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
3212 fp = &ha->fp_array[rss_id];
3218 mtx_lock(&fp->tx_mtx);
3220 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
3221 fp->tx_pkts_freed++;
3224 mtx_unlock(&fp->tx_mtx);
3227 QL_DPRINT2(ha, "exit\n");
3233 qlnx_txq_doorbell_wr32(qlnx_host_t *ha, void *reg_addr, uint32_t value)
3235 struct ecore_dev *cdev;
3240 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)ha->pci_dbells);
3242 bus_write_4(ha->pci_dbells, offset, value);
3243 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_READ);
3244 bus_barrier(ha->pci_dbells, 0, 0, BUS_SPACE_BARRIER_READ);
3250 qlnx_tcp_offset(qlnx_host_t *ha, struct mbuf *mp)
3252 struct ether_vlan_header *eh = NULL;
3253 struct ip *ip = NULL;
3254 struct ip6_hdr *ip6 = NULL;
3255 struct tcphdr *th = NULL;
3256 uint32_t ehdrlen = 0, ip_hlen = 0, offset = 0;
3259 uint8_t buf[sizeof(struct ip6_hdr)];
3263 eh = mtod(mp, struct ether_vlan_header *);
3265 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3266 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3267 etype = ntohs(eh->evl_proto);
3269 ehdrlen = ETHER_HDR_LEN;
3270 etype = ntohs(eh->evl_encap_proto);
3276 ip = (struct ip *)(mp->m_data + ehdrlen);
3278 ip_hlen = sizeof (struct ip);
3280 if (mp->m_len < (ehdrlen + ip_hlen)) {
3281 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
3282 ip = (struct ip *)buf;
3285 th = (struct tcphdr *)(ip + 1);
3286 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3289 case ETHERTYPE_IPV6:
3290 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3292 ip_hlen = sizeof(struct ip6_hdr);
3294 if (mp->m_len < (ehdrlen + ip_hlen)) {
3295 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
3297 ip6 = (struct ip6_hdr *)buf;
3299 th = (struct tcphdr *)(ip6 + 1);
3300 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3311 qlnx_tso_check(struct qlnx_fastpath *fp, bus_dma_segment_t *segs, int nsegs,
3315 uint32_t sum, nbds_in_hdr = 1;
3317 bus_dma_segment_t *s_seg;
3319 /* If the header spans mulitple segments, skip those segments */
3321 if (nsegs < ETH_TX_LSO_WINDOW_BDS_NUM)
3326 while ((i < nsegs) && (offset >= segs->ds_len)) {
3327 offset = offset - segs->ds_len;
3333 window = ETH_TX_LSO_WINDOW_BDS_NUM - nbds_in_hdr;
3337 while (nsegs >= window) {
3342 for (i = 0; i < window; i++){
3343 sum += s_seg->ds_len;
3347 if (sum < ETH_TX_LSO_WINDOW_MIN_LEN) {
3348 fp->tx_lso_wnd_min_len++;
3360 qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp, struct mbuf **m_headp)
3362 bus_dma_segment_t *segs;
3363 bus_dmamap_t map = 0;
3366 struct mbuf *m_head = *m_headp;
3371 struct qlnx_tx_queue *txq;
3373 struct eth_tx_1st_bd *first_bd;
3374 struct eth_tx_2nd_bd *second_bd;
3375 struct eth_tx_3rd_bd *third_bd;
3376 struct eth_tx_bd *tx_data_bd;
3379 uint32_t nbds_in_hdr = 0;
3380 uint32_t offset = 0;
3382 #ifdef QLNX_TRACE_PERF_DATA
3386 QL_DPRINT8(ha, "enter[%d]\n", fp->rss_id);
3398 if ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl)) <
3399 QLNX_TX_ELEM_MIN_THRESH) {
3401 fp->tx_nsegs_gt_elem_left++;
3402 fp->err_tx_nsegs_gt_elem_left++;
3407 idx = txq->sw_tx_prod;
3409 map = txq->sw_tx_ring[idx].map;
3412 ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, segs, &nsegs,
3415 if (ha->dbg_trace_tso_pkt_len) {
3416 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3417 if (!fp->tx_tso_min_pkt_len) {
3418 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3419 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3421 if (fp->tx_tso_min_pkt_len > m_head->m_pkthdr.len)
3422 fp->tx_tso_min_pkt_len =
3423 m_head->m_pkthdr.len;
3424 if (fp->tx_tso_max_pkt_len < m_head->m_pkthdr.len)
3425 fp->tx_tso_max_pkt_len =
3426 m_head->m_pkthdr.len;
3431 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3432 offset = qlnx_tcp_offset(ha, m_head);
3434 if ((ret == EFBIG) ||
3435 ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) && (
3436 (!(m_head->m_pkthdr.csum_flags & CSUM_TSO)) ||
3437 ((m_head->m_pkthdr.csum_flags & CSUM_TSO) &&
3438 qlnx_tso_check(fp, segs, nsegs, offset))))) {
3442 QL_DPRINT8(ha, "EFBIG [%d]\n", m_head->m_pkthdr.len);
3446 m = m_defrag(m_head, M_NOWAIT);
3448 fp->err_tx_defrag++;
3449 fp->tx_pkts_freed++;
3452 QL_DPRINT1(ha, "m_defrag() = NULL [%d]\n", ret);
3459 if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head,
3460 segs, &nsegs, BUS_DMA_NOWAIT))) {
3462 fp->err_tx_defrag_dmamap_load++;
3465 "bus_dmamap_load_mbuf_sg failed0 [%d, %d]\n",
3466 ret, m_head->m_pkthdr.len);
3468 fp->tx_pkts_freed++;
3475 if ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) &&
3476 !(m_head->m_pkthdr.csum_flags & CSUM_TSO)) {
3478 fp->err_tx_non_tso_max_seg++;
3481 "(%d) nsegs too many for non-TSO [%d, %d]\n",
3482 ret, nsegs, m_head->m_pkthdr.len);
3484 fp->tx_pkts_freed++;
3490 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3491 offset = qlnx_tcp_offset(ha, m_head);
3495 fp->err_tx_dmamap_load++;
3497 QL_DPRINT1(ha, "bus_dmamap_load_mbuf_sg failed1 [%d, %d]\n",
3498 ret, m_head->m_pkthdr.len);
3499 fp->tx_pkts_freed++;
3505 QL_ASSERT(ha, (nsegs != 0), ("qlnx_send: empty packet"));
3507 if (ha->dbg_trace_tso_pkt_len) {
3508 if (nsegs < QLNX_FP_MAX_SEGS)
3509 fp->tx_pkts[(nsegs - 1)]++;
3511 fp->tx_pkts[(QLNX_FP_MAX_SEGS - 1)]++;
3514 #ifdef QLNX_TRACE_PERF_DATA
3515 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3516 if(m_head->m_pkthdr.len <= 2048)
3517 fp->tx_pkts_hist[0]++;
3518 else if((m_head->m_pkthdr.len > 2048) &&
3519 (m_head->m_pkthdr.len <= 4096))
3520 fp->tx_pkts_hist[1]++;
3521 else if((m_head->m_pkthdr.len > 4096) &&
3522 (m_head->m_pkthdr.len <= 8192))
3523 fp->tx_pkts_hist[2]++;
3524 else if((m_head->m_pkthdr.len > 8192) &&
3525 (m_head->m_pkthdr.len <= 12288 ))
3526 fp->tx_pkts_hist[3]++;
3527 else if((m_head->m_pkthdr.len > 11288) &&
3528 (m_head->m_pkthdr.len <= 16394))
3529 fp->tx_pkts_hist[4]++;
3530 else if((m_head->m_pkthdr.len > 16384) &&
3531 (m_head->m_pkthdr.len <= 20480))
3532 fp->tx_pkts_hist[5]++;
3533 else if((m_head->m_pkthdr.len > 20480) &&
3534 (m_head->m_pkthdr.len <= 24576))
3535 fp->tx_pkts_hist[6]++;
3536 else if((m_head->m_pkthdr.len > 24576) &&
3537 (m_head->m_pkthdr.len <= 28672))
3538 fp->tx_pkts_hist[7]++;
3539 else if((m_head->m_pkthdr.len > 28762) &&
3540 (m_head->m_pkthdr.len <= 32768))
3541 fp->tx_pkts_hist[8]++;
3542 else if((m_head->m_pkthdr.len > 32768) &&
3543 (m_head->m_pkthdr.len <= 36864))
3544 fp->tx_pkts_hist[9]++;
3545 else if((m_head->m_pkthdr.len > 36864) &&
3546 (m_head->m_pkthdr.len <= 40960))
3547 fp->tx_pkts_hist[10]++;
3548 else if((m_head->m_pkthdr.len > 40960) &&
3549 (m_head->m_pkthdr.len <= 45056))
3550 fp->tx_pkts_hist[11]++;
3551 else if((m_head->m_pkthdr.len > 45056) &&
3552 (m_head->m_pkthdr.len <= 49152))
3553 fp->tx_pkts_hist[12]++;
3554 else if((m_head->m_pkthdr.len > 49512) &&
3555 m_head->m_pkthdr.len <= 53248))
3556 fp->tx_pkts_hist[13]++;
3557 else if((m_head->m_pkthdr.len > 53248) &&
3558 (m_head->m_pkthdr.len <= 57344))
3559 fp->tx_pkts_hist[14]++;
3560 else if((m_head->m_pkthdr.len > 53248) &&
3561 (m_head->m_pkthdr.len <= 57344))
3562 fp->tx_pkts_hist[15]++;
3563 else if((m_head->m_pkthdr.len > 57344) &&
3564 (m_head->m_pkthdr.len <= 61440))
3565 fp->tx_pkts_hist[16]++;
3567 fp->tx_pkts_hist[17]++;
3570 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3572 elem_left = ecore_chain_get_elem_left(&txq->tx_pbl);
3573 bd_used = TX_RING_SIZE - elem_left;
3577 else if((bd_used > 100) && (bd_used <= 500))
3579 else if((bd_used > 500) && (bd_used <= 1000))
3581 else if((bd_used > 1000) && (bd_used <= 2000))
3583 else if((bd_used > 3000) && (bd_used <= 4000))
3585 else if((bd_used > 4000) && (bd_used <= 5000))
3587 else if((bd_used > 6000) && (bd_used <= 7000))
3589 else if((bd_used > 7000) && (bd_used <= 8000))
3591 else if((bd_used > 8000) && (bd_used <= 9000))
3593 else if((bd_used > 9000) && (bd_used <= 10000))
3595 else if((bd_used > 10000) && (bd_used <= 11000))
3596 fp->tx_pkts_q[10]++;
3597 else if((bd_used > 11000) && (bd_used <= 12000))
3598 fp->tx_pkts_q[11]++;
3599 else if((bd_used > 12000) && (bd_used <= 13000))
3600 fp->tx_pkts_q[12]++;
3601 else if((bd_used > 13000) && (bd_used <= 14000))
3602 fp->tx_pkts_q[13]++;
3603 else if((bd_used > 14000) && (bd_used <= 15000))
3604 fp->tx_pkts_q[14]++;
3605 else if((bd_used > 15000) && (bd_used <= 16000))
3606 fp->tx_pkts_q[15]++;
3608 fp->tx_pkts_q[16]++;
3611 #endif /* end of QLNX_TRACE_PERF_DATA */
3613 if ((nsegs + QLNX_TX_ELEM_RESERVE) >
3614 (int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))) {
3616 QL_DPRINT1(ha, "(%d, 0x%x) insuffient BDs"
3617 " in chain[%d] trying to free packets\n",
3618 nsegs, elem_left, fp->rss_id);
3620 fp->tx_nsegs_gt_elem_left++;
3622 (void)qlnx_tx_int(ha, fp, txq);
3624 if ((nsegs + QLNX_TX_ELEM_RESERVE) > (int)(elem_left =
3625 ecore_chain_get_elem_left(&txq->tx_pbl))) {
3628 "(%d, 0x%x) insuffient BDs in chain[%d]\n",
3629 nsegs, elem_left, fp->rss_id);
3631 fp->err_tx_nsegs_gt_elem_left++;
3632 fp->tx_ring_full = 1;
3633 if (ha->storm_stats_enable)
3634 ha->storm_stats_gather = 1;
3639 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE);
3641 txq->sw_tx_ring[idx].mp = m_head;
3643 first_bd = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
3645 memset(first_bd, 0, sizeof(*first_bd));
3647 first_bd->data.bd_flags.bitfields =
3648 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
3650 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, segs->ds_len);
3654 if (m_head->m_pkthdr.csum_flags & CSUM_IP) {
3655 first_bd->data.bd_flags.bitfields |=
3656 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3659 if (m_head->m_pkthdr.csum_flags &
3660 (CSUM_UDP | CSUM_TCP | CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) {
3661 first_bd->data.bd_flags.bitfields |=
3662 (1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT);
3665 if (m_head->m_flags & M_VLANTAG) {
3666 first_bd->data.vlan = m_head->m_pkthdr.ether_vtag;
3667 first_bd->data.bd_flags.bitfields |=
3668 (1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT);
3671 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3673 first_bd->data.bd_flags.bitfields |=
3674 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
3675 first_bd->data.bd_flags.bitfields |=
3676 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3680 if (offset == segs->ds_len) {
3681 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3685 second_bd = (struct eth_tx_2nd_bd *)
3686 ecore_chain_produce(&txq->tx_pbl);
3687 memset(second_bd, 0, sizeof(*second_bd));
3690 if (seg_idx < nsegs) {
3691 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3692 (segs->ds_addr), (segs->ds_len));
3697 third_bd = (struct eth_tx_3rd_bd *)
3698 ecore_chain_produce(&txq->tx_pbl);
3699 memset(third_bd, 0, sizeof(*third_bd));
3700 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3701 third_bd->data.bitfields |=
3702 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3705 if (seg_idx < nsegs) {
3706 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3707 (segs->ds_addr), (segs->ds_len));
3712 for (; seg_idx < nsegs; seg_idx++) {
3713 tx_data_bd = (struct eth_tx_bd *)
3714 ecore_chain_produce(&txq->tx_pbl);
3715 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3716 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3723 } else if (offset < segs->ds_len) {
3724 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3726 second_bd = (struct eth_tx_2nd_bd *)
3727 ecore_chain_produce(&txq->tx_pbl);
3728 memset(second_bd, 0, sizeof(*second_bd));
3729 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3730 (segs->ds_addr + offset),\
3731 (segs->ds_len - offset));
3735 third_bd = (struct eth_tx_3rd_bd *)
3736 ecore_chain_produce(&txq->tx_pbl);
3737 memset(third_bd, 0, sizeof(*third_bd));
3739 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3742 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3743 third_bd->data.bitfields |=
3744 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3748 for (seg_idx = 2; seg_idx < nsegs; seg_idx++) {
3749 tx_data_bd = (struct eth_tx_bd *)
3750 ecore_chain_produce(&txq->tx_pbl);
3751 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3752 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3760 offset = offset - segs->ds_len;
3763 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3768 tx_data_bd = (struct eth_tx_bd *)
3769 ecore_chain_produce(&txq->tx_pbl);
3770 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3772 if (second_bd == NULL) {
3773 second_bd = (struct eth_tx_2nd_bd *)
3775 } else if (third_bd == NULL) {
3776 third_bd = (struct eth_tx_3rd_bd *)
3780 if (offset && (offset < segs->ds_len)) {
3781 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3782 segs->ds_addr, offset);
3784 tx_data_bd = (struct eth_tx_bd *)
3785 ecore_chain_produce(&txq->tx_pbl);
3787 memset(tx_data_bd, 0,
3788 sizeof(*tx_data_bd));
3790 if (second_bd == NULL) {
3792 (struct eth_tx_2nd_bd *)tx_data_bd;
3793 } else if (third_bd == NULL) {
3795 (struct eth_tx_3rd_bd *)tx_data_bd;
3797 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3798 (segs->ds_addr + offset), \
3799 (segs->ds_len - offset));
3804 offset = offset - segs->ds_len;
3805 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3806 segs->ds_addr, segs->ds_len);
3812 if (third_bd == NULL) {
3813 third_bd = (struct eth_tx_3rd_bd *)
3814 ecore_chain_produce(&txq->tx_pbl);
3815 memset(third_bd, 0, sizeof(*third_bd));
3818 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3819 third_bd->data.bitfields |=
3820 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3825 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3826 tx_data_bd = (struct eth_tx_bd *)
3827 ecore_chain_produce(&txq->tx_pbl);
3828 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3829 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, segs->ds_addr,\
3834 first_bd->data.bitfields =
3835 (m_head->m_pkthdr.len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
3836 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
3837 first_bd->data.bitfields =
3838 htole16(first_bd->data.bitfields);
3839 fp->tx_non_tso_pkts++;
3843 first_bd->data.nbds = nbd;
3845 if (ha->dbg_trace_tso_pkt_len) {
3846 if (fp->tx_tso_max_nsegs < nsegs)
3847 fp->tx_tso_max_nsegs = nsegs;
3849 if ((nsegs < fp->tx_tso_min_nsegs) || (!fp->tx_tso_min_nsegs))
3850 fp->tx_tso_min_nsegs = nsegs;
3853 txq->sw_tx_ring[idx].nsegs = nsegs;
3854 txq->sw_tx_prod = (txq->sw_tx_prod + 1) & (TX_RING_SIZE - 1);
3856 txq->tx_db.data.bd_prod =
3857 htole16(ecore_chain_get_prod_idx(&txq->tx_pbl));
3859 qlnx_txq_doorbell_wr32(ha, txq->doorbell_addr, txq->tx_db.raw);
3861 QL_DPRINT8(ha, "exit[%d]\n", fp->rss_id);
3866 qlnx_stop(qlnx_host_t *ha)
3868 struct ifnet *ifp = ha->ifp;
3874 ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE | IFF_DRV_RUNNING);
3877 * We simply lock and unlock each fp->tx_mtx to
3878 * propagate the if_drv_flags
3879 * state to each tx thread
3881 QL_DPRINT1(ha, "QLNX STATE = %d\n",ha->state);
3883 if (ha->state == QLNX_STATE_OPEN) {
3884 for (i = 0; i < ha->num_rss; i++) {
3885 struct qlnx_fastpath *fp = &ha->fp_array[i];
3887 mtx_lock(&fp->tx_mtx);
3888 mtx_unlock(&fp->tx_mtx);
3890 if (fp->fp_taskqueue != NULL)
3891 taskqueue_enqueue(fp->fp_taskqueue,
3895 #ifdef QLNX_ENABLE_IWARP
3896 if (qlnx_vf_device(ha) != 0) {
3897 qlnx_rdma_dev_close(ha);
3899 #endif /* #ifdef QLNX_ENABLE_IWARP */
3907 qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha)
3909 return(TX_RING_SIZE - 1);
3913 qlnx_get_mac_addr(qlnx_host_t *ha)
3915 struct ecore_hwfn *p_hwfn;
3916 unsigned char mac[ETHER_ADDR_LEN];
3917 uint8_t p_is_forced;
3919 p_hwfn = &ha->cdev.hwfns[0];
3921 if (qlnx_vf_device(ha) != 0)
3922 return (p_hwfn->hw_info.hw_mac_addr);
3924 ecore_vf_read_bulletin(p_hwfn, &p_is_forced);
3925 if (ecore_vf_bulletin_get_forced_mac(p_hwfn, mac, &p_is_forced) ==
3927 device_printf(ha->pci_dev, "%s: p_is_forced = %d"
3928 " mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", __func__,
3929 p_is_forced, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3930 memcpy(ha->primary_mac, mac, ETH_ALEN);
3933 return (ha->primary_mac);
3937 qlnx_get_optics(qlnx_host_t *ha, struct qlnx_link_output *if_link)
3939 uint32_t ifm_type = 0;
3941 switch (if_link->media_type) {
3943 case MEDIA_MODULE_FIBER:
3944 case MEDIA_UNSPECIFIED:
3945 if (if_link->speed == (100 * 1000))
3946 ifm_type = QLNX_IFM_100G_SR4;
3947 else if (if_link->speed == (40 * 1000))
3948 ifm_type = IFM_40G_SR4;
3949 else if (if_link->speed == (25 * 1000))
3950 ifm_type = QLNX_IFM_25G_SR;
3951 else if (if_link->speed == (10 * 1000))
3952 ifm_type = (IFM_10G_LR | IFM_10G_SR);
3953 else if (if_link->speed == (1 * 1000))
3954 ifm_type = (IFM_1000_SX | IFM_1000_LX);
3958 case MEDIA_DA_TWINAX:
3959 if (if_link->speed == (100 * 1000))
3960 ifm_type = QLNX_IFM_100G_CR4;
3961 else if (if_link->speed == (40 * 1000))
3962 ifm_type = IFM_40G_CR4;
3963 else if (if_link->speed == (25 * 1000))
3964 ifm_type = QLNX_IFM_25G_CR;
3965 else if (if_link->speed == (10 * 1000))
3966 ifm_type = IFM_10G_TWINAX;
3971 ifm_type = IFM_UNKNOWN;
3979 /*****************************************************************************
3980 * Interrupt Service Functions
3981 *****************************************************************************/
3984 qlnx_rx_jumbo_chain(qlnx_host_t *ha, struct qlnx_fastpath *fp,
3985 struct mbuf *mp_head, uint16_t len)
3987 struct mbuf *mp, *mpf, *mpl;
3988 struct sw_rx_data *sw_rx_data;
3989 struct qlnx_rx_queue *rxq;
3990 uint16_t len_in_buffer;
3993 mpf = mpl = mp = NULL;
3997 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3999 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4000 mp = sw_rx_data->data;
4003 QL_DPRINT1(ha, "mp = NULL\n");
4004 fp->err_rx_mp_null++;
4006 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4013 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4014 BUS_DMASYNC_POSTREAD);
4016 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4018 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
4019 " incoming packet and reusing its buffer\n");
4021 qlnx_reuse_rx_data(rxq);
4022 fp->err_rx_alloc_errors++;
4029 ecore_chain_consume(&rxq->rx_bd_ring);
4031 if (len > rxq->rx_buf_size)
4032 len_in_buffer = rxq->rx_buf_size;
4034 len_in_buffer = len;
4036 len = len - len_in_buffer;
4038 mp->m_flags &= ~M_PKTHDR;
4040 mp->m_len = len_in_buffer;
4051 mp_head->m_next = mpf;
4057 qlnx_tpa_start(qlnx_host_t *ha,
4058 struct qlnx_fastpath *fp,
4059 struct qlnx_rx_queue *rxq,
4060 struct eth_fast_path_rx_tpa_start_cqe *cqe)
4063 struct ifnet *ifp = ha->ifp;
4065 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4066 struct sw_rx_data *sw_rx_data;
4069 struct eth_rx_bd *rx_bd;
4072 #if __FreeBSD_version >= 1100000
4074 #endif /* #if __FreeBSD_version >= 1100000 */
4077 agg_index = cqe->tpa_agg_index;
4079 QL_DPRINT7(ha, "[rss_id = %d]: enter\n \
4081 \t bitfields = 0x%x\n \
4082 \t seg_len = 0x%x\n \
4083 \t pars_flags = 0x%x\n \
4084 \t vlan_tag = 0x%x\n \
4085 \t rss_hash = 0x%x\n \
4086 \t len_on_first_bd = 0x%x\n \
4087 \t placement_offset = 0x%x\n \
4088 \t tpa_agg_index = 0x%x\n \
4089 \t header_len = 0x%x\n \
4090 \t ext_bd_len_list[0] = 0x%x\n \
4091 \t ext_bd_len_list[1] = 0x%x\n \
4092 \t ext_bd_len_list[2] = 0x%x\n \
4093 \t ext_bd_len_list[3] = 0x%x\n \
4094 \t ext_bd_len_list[4] = 0x%x\n",
4095 fp->rss_id, cqe->type, cqe->bitfields, cqe->seg_len,
4096 cqe->pars_flags.flags, cqe->vlan_tag,
4097 cqe->rss_hash, cqe->len_on_first_bd, cqe->placement_offset,
4098 cqe->tpa_agg_index, cqe->header_len,
4099 cqe->ext_bd_len_list[0], cqe->ext_bd_len_list[1],
4100 cqe->ext_bd_len_list[2], cqe->ext_bd_len_list[3],
4101 cqe->ext_bd_len_list[4]);
4103 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4104 fp->err_rx_tpa_invalid_agg_num++;
4108 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4109 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map, BUS_DMASYNC_POSTREAD);
4110 mp = sw_rx_data->data;
4112 QL_DPRINT7(ha, "[rss_id = %d]: mp = %p \n ", fp->rss_id, mp);
4115 QL_DPRINT7(ha, "[%d]: mp = NULL\n", fp->rss_id);
4116 fp->err_rx_mp_null++;
4117 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4122 if ((le16toh(cqe->pars_flags.flags)) & CQE_FLAGS_ERR) {
4124 QL_DPRINT7(ha, "[%d]: CQE in CONS = %u has error,"
4125 " flags = %x, dropping incoming packet\n", fp->rss_id,
4126 rxq->sw_rx_cons, le16toh(cqe->pars_flags.flags));
4128 fp->err_rx_hw_errors++;
4130 qlnx_reuse_rx_data(rxq);
4132 QLNX_INC_IERRORS(ifp);
4137 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4139 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4140 " dropping incoming packet and reusing its buffer\n",
4143 fp->err_rx_alloc_errors++;
4144 QLNX_INC_IQDROPS(ifp);
4147 * Load the tpa mbuf into the rx ring and save the
4151 map = sw_rx_data->map;
4152 addr = sw_rx_data->dma_addr;
4154 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
4156 sw_rx_data->data = rxq->tpa_info[agg_index].rx_buf.data;
4157 sw_rx_data->dma_addr = rxq->tpa_info[agg_index].rx_buf.dma_addr;
4158 sw_rx_data->map = rxq->tpa_info[agg_index].rx_buf.map;
4160 rxq->tpa_info[agg_index].rx_buf.data = mp;
4161 rxq->tpa_info[agg_index].rx_buf.dma_addr = addr;
4162 rxq->tpa_info[agg_index].rx_buf.map = map;
4164 rx_bd = (struct eth_rx_bd *)
4165 ecore_chain_produce(&rxq->rx_bd_ring);
4167 rx_bd->addr.hi = htole32(U64_HI(sw_rx_data->dma_addr));
4168 rx_bd->addr.lo = htole32(U64_LO(sw_rx_data->dma_addr));
4170 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4171 BUS_DMASYNC_PREREAD);
4173 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
4174 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4176 ecore_chain_consume(&rxq->rx_bd_ring);
4178 /* Now reuse any buffers posted in ext_bd_len_list */
4179 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4181 if (cqe->ext_bd_len_list[i] == 0)
4184 qlnx_reuse_rx_data(rxq);
4187 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
4191 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4193 QL_DPRINT7(ha, "[%d]: invalid aggregation state,"
4194 " dropping incoming packet and reusing its buffer\n",
4197 QLNX_INC_IQDROPS(ifp);
4199 /* if we already have mbuf head in aggregation free it */
4200 if (rxq->tpa_info[agg_index].mpf) {
4201 m_freem(rxq->tpa_info[agg_index].mpf);
4202 rxq->tpa_info[agg_index].mpl = NULL;
4204 rxq->tpa_info[agg_index].mpf = mp;
4205 rxq->tpa_info[agg_index].mpl = NULL;
4207 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4208 ecore_chain_consume(&rxq->rx_bd_ring);
4210 /* Now reuse any buffers posted in ext_bd_len_list */
4211 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4213 if (cqe->ext_bd_len_list[i] == 0)
4216 qlnx_reuse_rx_data(rxq);
4218 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
4224 * first process the ext_bd_len_list
4225 * if this fails then we simply drop the packet
4227 ecore_chain_consume(&rxq->rx_bd_ring);
4228 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4230 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4232 QL_DPRINT7(ha, "[%d]: 4\n ", fp->rss_id);
4234 if (cqe->ext_bd_len_list[i] == 0)
4237 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4238 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4239 BUS_DMASYNC_POSTREAD);
4241 mpc = sw_rx_data->data;
4244 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4245 fp->err_rx_mp_null++;
4249 rxq->tpa_info[agg_index].agg_state =
4250 QLNX_AGG_STATE_ERROR;
4251 ecore_chain_consume(&rxq->rx_bd_ring);
4253 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4257 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4258 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4259 " dropping incoming packet and reusing its"
4260 " buffer\n", fp->rss_id);
4262 qlnx_reuse_rx_data(rxq);
4268 rxq->tpa_info[agg_index].agg_state =
4269 QLNX_AGG_STATE_ERROR;
4271 ecore_chain_consume(&rxq->rx_bd_ring);
4273 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4278 mpc->m_flags &= ~M_PKTHDR;
4280 mpc->m_len = cqe->ext_bd_len_list[i];
4286 mpl->m_len = ha->rx_buf_size;
4291 ecore_chain_consume(&rxq->rx_bd_ring);
4293 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4296 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4298 QL_DPRINT7(ha, "[%d]: invalid aggregation state, dropping"
4299 " incoming packet and reusing its buffer\n",
4302 QLNX_INC_IQDROPS(ifp);
4304 rxq->tpa_info[agg_index].mpf = mp;
4305 rxq->tpa_info[agg_index].mpl = NULL;
4310 rxq->tpa_info[agg_index].placement_offset = cqe->placement_offset;
4313 mp->m_len = ha->rx_buf_size;
4315 rxq->tpa_info[agg_index].mpf = mp;
4316 rxq->tpa_info[agg_index].mpl = mpl;
4318 mp->m_len = cqe->len_on_first_bd + cqe->placement_offset;
4319 rxq->tpa_info[agg_index].mpf = mp;
4320 rxq->tpa_info[agg_index].mpl = mp;
4324 mp->m_flags |= M_PKTHDR;
4326 /* assign packet to this interface interface */
4327 mp->m_pkthdr.rcvif = ifp;
4329 /* assume no hardware checksum has complated */
4330 mp->m_pkthdr.csum_flags = 0;
4332 //mp->m_pkthdr.flowid = fp->rss_id;
4333 mp->m_pkthdr.flowid = cqe->rss_hash;
4335 #if __FreeBSD_version >= 1100000
4337 hash_type = cqe->bitfields &
4338 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4339 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4341 switch (hash_type) {
4343 case RSS_HASH_TYPE_IPV4:
4344 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4347 case RSS_HASH_TYPE_TCP_IPV4:
4348 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4351 case RSS_HASH_TYPE_IPV6:
4352 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4355 case RSS_HASH_TYPE_TCP_IPV6:
4356 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4360 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4365 mp->m_flags |= M_FLOWID;
4368 mp->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | CSUM_IP_VALID |
4369 CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4371 mp->m_pkthdr.csum_data = 0xFFFF;
4373 if (CQE_HAS_VLAN(cqe->pars_flags.flags)) {
4374 mp->m_pkthdr.ether_vtag = le16toh(cqe->vlan_tag);
4375 mp->m_flags |= M_VLANTAG;
4378 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_START;
4380 QL_DPRINT7(ha, "[%d]: 5\n\tagg_state = %d\n\t mpf = %p mpl = %p\n",
4381 fp->rss_id, rxq->tpa_info[agg_index].agg_state,
4382 rxq->tpa_info[agg_index].mpf, rxq->tpa_info[agg_index].mpl);
4388 qlnx_tpa_cont(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4389 struct qlnx_rx_queue *rxq,
4390 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
4392 struct sw_rx_data *sw_rx_data;
4394 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4401 QL_DPRINT7(ha, "[%d]: enter\n \
4403 \t tpa_agg_index = 0x%x\n \
4404 \t len_list[0] = 0x%x\n \
4405 \t len_list[1] = 0x%x\n \
4406 \t len_list[2] = 0x%x\n \
4407 \t len_list[3] = 0x%x\n \
4408 \t len_list[4] = 0x%x\n \
4409 \t len_list[5] = 0x%x\n",
4410 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4411 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4412 cqe->len_list[3], cqe->len_list[4], cqe->len_list[5]);
4414 agg_index = cqe->tpa_agg_index;
4416 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4417 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4418 fp->err_rx_tpa_invalid_agg_num++;
4423 for (i = 0; i < ETH_TPA_CQE_CONT_LEN_LIST_SIZE; i++) {
4425 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4427 if (cqe->len_list[i] == 0)
4430 if (rxq->tpa_info[agg_index].agg_state !=
4431 QLNX_AGG_STATE_START) {
4432 qlnx_reuse_rx_data(rxq);
4436 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4437 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4438 BUS_DMASYNC_POSTREAD);
4440 mpc = sw_rx_data->data;
4444 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4446 fp->err_rx_mp_null++;
4450 rxq->tpa_info[agg_index].agg_state =
4451 QLNX_AGG_STATE_ERROR;
4452 ecore_chain_consume(&rxq->rx_bd_ring);
4454 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4458 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4460 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4461 " dropping incoming packet and reusing its"
4462 " buffer\n", fp->rss_id);
4464 qlnx_reuse_rx_data(rxq);
4470 rxq->tpa_info[agg_index].agg_state =
4471 QLNX_AGG_STATE_ERROR;
4473 ecore_chain_consume(&rxq->rx_bd_ring);
4475 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4480 mpc->m_flags &= ~M_PKTHDR;
4482 mpc->m_len = cqe->len_list[i];
4488 mpl->m_len = ha->rx_buf_size;
4493 ecore_chain_consume(&rxq->rx_bd_ring);
4495 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4498 QL_DPRINT7(ha, "[%d]: 2\n" "\tmpf = %p mpl = %p\n",
4499 fp->rss_id, mpf, mpl);
4502 mp = rxq->tpa_info[agg_index].mpl;
4503 mp->m_len = ha->rx_buf_size;
4505 rxq->tpa_info[agg_index].mpl = mpl;
4512 qlnx_tpa_end(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4513 struct qlnx_rx_queue *rxq,
4514 struct eth_fast_path_rx_tpa_end_cqe *cqe)
4516 struct sw_rx_data *sw_rx_data;
4518 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4522 struct ifnet *ifp = ha->ifp;
4527 QL_DPRINT7(ha, "[%d]: enter\n \
4529 \t tpa_agg_index = 0x%x\n \
4530 \t total_packet_len = 0x%x\n \
4531 \t num_of_bds = 0x%x\n \
4532 \t end_reason = 0x%x\n \
4533 \t num_of_coalesced_segs = 0x%x\n \
4534 \t ts_delta = 0x%x\n \
4535 \t len_list[0] = 0x%x\n \
4536 \t len_list[1] = 0x%x\n \
4537 \t len_list[2] = 0x%x\n \
4538 \t len_list[3] = 0x%x\n",
4539 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4540 cqe->total_packet_len, cqe->num_of_bds,
4541 cqe->end_reason, cqe->num_of_coalesced_segs, cqe->ts_delta,
4542 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4545 agg_index = cqe->tpa_agg_index;
4547 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4549 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4551 fp->err_rx_tpa_invalid_agg_num++;
4556 for (i = 0; i < ETH_TPA_CQE_END_LEN_LIST_SIZE; i++) {
4558 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4560 if (cqe->len_list[i] == 0)
4563 if (rxq->tpa_info[agg_index].agg_state !=
4564 QLNX_AGG_STATE_START) {
4566 QL_DPRINT7(ha, "[%d]: 2\n ", fp->rss_id);
4568 qlnx_reuse_rx_data(rxq);
4572 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4573 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4574 BUS_DMASYNC_POSTREAD);
4576 mpc = sw_rx_data->data;
4580 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4582 fp->err_rx_mp_null++;
4586 rxq->tpa_info[agg_index].agg_state =
4587 QLNX_AGG_STATE_ERROR;
4588 ecore_chain_consume(&rxq->rx_bd_ring);
4590 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4594 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4595 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4596 " dropping incoming packet and reusing its"
4597 " buffer\n", fp->rss_id);
4599 qlnx_reuse_rx_data(rxq);
4605 rxq->tpa_info[agg_index].agg_state =
4606 QLNX_AGG_STATE_ERROR;
4608 ecore_chain_consume(&rxq->rx_bd_ring);
4610 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4615 mpc->m_flags &= ~M_PKTHDR;
4617 mpc->m_len = cqe->len_list[i];
4623 mpl->m_len = ha->rx_buf_size;
4628 ecore_chain_consume(&rxq->rx_bd_ring);
4630 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4633 QL_DPRINT7(ha, "[%d]: 5\n ", fp->rss_id);
4637 QL_DPRINT7(ha, "[%d]: 6\n ", fp->rss_id);
4639 mp = rxq->tpa_info[agg_index].mpl;
4640 mp->m_len = ha->rx_buf_size;
4644 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_START) {
4646 QL_DPRINT7(ha, "[%d]: 7\n ", fp->rss_id);
4648 if (rxq->tpa_info[agg_index].mpf != NULL)
4649 m_freem(rxq->tpa_info[agg_index].mpf);
4650 rxq->tpa_info[agg_index].mpf = NULL;
4651 rxq->tpa_info[agg_index].mpl = NULL;
4652 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4656 mp = rxq->tpa_info[agg_index].mpf;
4657 m_adj(mp, rxq->tpa_info[agg_index].placement_offset);
4658 mp->m_pkthdr.len = cqe->total_packet_len;
4660 if (mp->m_next == NULL)
4661 mp->m_len = mp->m_pkthdr.len;
4663 /* compute the total packet length */
4665 while (mpf != NULL) {
4670 if (cqe->total_packet_len > len) {
4671 mpl = rxq->tpa_info[agg_index].mpl;
4672 mpl->m_len += (cqe->total_packet_len - len);
4676 QLNX_INC_IPACKETS(ifp);
4677 QLNX_INC_IBYTES(ifp, (cqe->total_packet_len));
4679 QL_DPRINT7(ha, "[%d]: 8 csum_data = 0x%x csum_flags = 0x%" PRIu64 "\n \
4680 m_len = 0x%x m_pkthdr_len = 0x%x\n",
4681 fp->rss_id, mp->m_pkthdr.csum_data,
4682 (uint64_t)mp->m_pkthdr.csum_flags, mp->m_len, mp->m_pkthdr.len);
4684 (*ifp->if_input)(ifp, mp);
4686 rxq->tpa_info[agg_index].mpf = NULL;
4687 rxq->tpa_info[agg_index].mpl = NULL;
4688 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4690 return (cqe->num_of_coalesced_segs);
4694 qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
4697 uint16_t hw_comp_cons, sw_comp_cons;
4699 struct qlnx_rx_queue *rxq = fp->rxq;
4700 struct ifnet *ifp = ha->ifp;
4701 struct ecore_dev *cdev = &ha->cdev;
4702 struct ecore_hwfn *p_hwfn;
4704 #ifdef QLNX_SOFT_LRO
4705 struct lro_ctrl *lro;
4708 #endif /* #ifdef QLNX_SOFT_LRO */
4710 hw_comp_cons = le16toh(*rxq->hw_cons_ptr);
4711 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4713 p_hwfn = &ha->cdev.hwfns[(fp->rss_id % cdev->num_hwfns)];
4715 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
4716 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
4717 * read before it is written by FW, then FW writes CQE and SB, and then
4718 * the CPU reads the hw_comp_cons, it will use an old CQE.
4721 /* Loop to complete all indicated BDs */
4722 while (sw_comp_cons != hw_comp_cons) {
4723 union eth_rx_cqe *cqe;
4724 struct eth_fast_path_rx_reg_cqe *fp_cqe;
4725 struct sw_rx_data *sw_rx_data;
4726 register struct mbuf *mp;
4727 enum eth_rx_cqe_type cqe_type;
4728 uint16_t len, pad, len_on_first_bd;
4730 #if __FreeBSD_version >= 1100000
4732 #endif /* #if __FreeBSD_version >= 1100000 */
4734 /* Get the CQE from the completion ring */
4735 cqe = (union eth_rx_cqe *)
4736 ecore_chain_consume(&rxq->rx_comp_ring);
4737 cqe_type = cqe->fast_path_regular.type;
4739 if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
4740 QL_DPRINT3(ha, "Got a slowath CQE\n");
4742 ecore_eth_cqe_completion(p_hwfn,
4743 (struct eth_slow_path_rx_cqe *)cqe);
4747 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
4751 case ETH_RX_CQE_TYPE_TPA_START:
4752 qlnx_tpa_start(ha, fp, rxq,
4753 &cqe->fast_path_tpa_start);
4757 case ETH_RX_CQE_TYPE_TPA_CONT:
4758 qlnx_tpa_cont(ha, fp, rxq,
4759 &cqe->fast_path_tpa_cont);
4763 case ETH_RX_CQE_TYPE_TPA_END:
4764 rx_pkt += qlnx_tpa_end(ha, fp, rxq,
4765 &cqe->fast_path_tpa_end);
4776 /* Get the data from the SW ring */
4777 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4778 mp = sw_rx_data->data;
4781 QL_DPRINT1(ha, "mp = NULL\n");
4782 fp->err_rx_mp_null++;
4784 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4787 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4788 BUS_DMASYNC_POSTREAD);
4791 fp_cqe = &cqe->fast_path_regular;/* MK CR TPA check assembly */
4792 len = le16toh(fp_cqe->pkt_len);
4793 pad = fp_cqe->placement_offset;
4795 QL_DPRINT3(ha, "CQE type = %x, flags = %x, vlan = %x,"
4796 " len %u, parsing flags = %d pad = %d\n",
4797 cqe_type, fp_cqe->bitfields,
4798 le16toh(fp_cqe->vlan_tag),
4799 len, le16toh(fp_cqe->pars_flags.flags), pad);
4801 data = mtod(mp, uint8_t *);
4805 qlnx_dump_buf8(ha, __func__, data, len);
4807 /* For every Rx BD consumed, we allocate a new BD so the BD ring
4808 * is always with a fixed size. If allocation fails, we take the
4809 * consumed BD and return it to the ring in the PROD position.
4810 * The packet that was received on that BD will be dropped (and
4811 * not passed to the upper stack).
4813 /* If this is an error packet then drop it */
4814 if ((le16toh(cqe->fast_path_regular.pars_flags.flags)) &
4817 QL_DPRINT1(ha, "CQE in CONS = %u has error, flags = %x,"
4818 " dropping incoming packet\n", sw_comp_cons,
4819 le16toh(cqe->fast_path_regular.pars_flags.flags));
4820 fp->err_rx_hw_errors++;
4822 qlnx_reuse_rx_data(rxq);
4824 QLNX_INC_IERRORS(ifp);
4829 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4831 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
4832 " incoming packet and reusing its buffer\n");
4833 qlnx_reuse_rx_data(rxq);
4835 fp->err_rx_alloc_errors++;
4837 QLNX_INC_IQDROPS(ifp);
4842 ecore_chain_consume(&rxq->rx_bd_ring);
4844 len_on_first_bd = fp_cqe->len_on_first_bd;
4846 mp->m_pkthdr.len = len;
4848 if ((len > 60 ) && (len > len_on_first_bd)) {
4850 mp->m_len = len_on_first_bd;
4852 if (qlnx_rx_jumbo_chain(ha, fp, mp,
4853 (len - len_on_first_bd)) != 0) {
4857 QLNX_INC_IQDROPS(ifp);
4862 } else if (len_on_first_bd < len) {
4863 fp->err_rx_jumbo_chain_pkts++;
4868 mp->m_flags |= M_PKTHDR;
4870 /* assign packet to this interface interface */
4871 mp->m_pkthdr.rcvif = ifp;
4873 /* assume no hardware checksum has complated */
4874 mp->m_pkthdr.csum_flags = 0;
4876 mp->m_pkthdr.flowid = fp_cqe->rss_hash;
4878 #if __FreeBSD_version >= 1100000
4880 hash_type = fp_cqe->bitfields &
4881 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4882 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4884 switch (hash_type) {
4886 case RSS_HASH_TYPE_IPV4:
4887 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4890 case RSS_HASH_TYPE_TCP_IPV4:
4891 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4894 case RSS_HASH_TYPE_IPV6:
4895 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4898 case RSS_HASH_TYPE_TCP_IPV6:
4899 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4903 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4908 mp->m_flags |= M_FLOWID;
4911 if (CQE_L3_PACKET(fp_cqe->pars_flags.flags)) {
4912 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4915 if (!(CQE_IP_HDR_ERR(fp_cqe->pars_flags.flags))) {
4916 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4919 if (CQE_L4_HAS_CSUM(fp_cqe->pars_flags.flags)) {
4920 mp->m_pkthdr.csum_data = 0xFFFF;
4921 mp->m_pkthdr.csum_flags |=
4922 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4925 if (CQE_HAS_VLAN(fp_cqe->pars_flags.flags)) {
4926 mp->m_pkthdr.ether_vtag = le16toh(fp_cqe->vlan_tag);
4927 mp->m_flags |= M_VLANTAG;
4930 QLNX_INC_IPACKETS(ifp);
4931 QLNX_INC_IBYTES(ifp, len);
4933 #ifdef QLNX_SOFT_LRO
4937 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
4939 tcp_lro_queue_mbuf(lro, mp);
4943 if (tcp_lro_rx(lro, mp, 0))
4944 (*ifp->if_input)(ifp, mp);
4946 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
4949 (*ifp->if_input)(ifp, mp);
4953 (*ifp->if_input)(ifp, mp);
4955 #endif /* #ifdef QLNX_SOFT_LRO */
4959 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4961 next_cqe: /* don't consume bd rx buffer */
4962 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
4963 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4965 /* CR TPA - revisit how to handle budget in TPA perhaps
4966 increase on "end" */
4967 if (rx_pkt == budget)
4969 } /* repeat while sw_comp_cons != hw_comp_cons... */
4971 /* Update producers */
4972 qlnx_update_rx_prod(p_hwfn, rxq);
4979 * fast path interrupt
4983 qlnx_fp_isr(void *arg)
4985 qlnx_ivec_t *ivec = arg;
4987 struct qlnx_fastpath *fp = NULL;
4992 if (ha->state != QLNX_STATE_OPEN) {
4996 idx = ivec->rss_idx;
4998 if ((idx = ivec->rss_idx) >= ha->num_rss) {
4999 QL_DPRINT1(ha, "illegal interrupt[%d]\n", idx);
5000 ha->err_illegal_intr++;
5003 fp = &ha->fp_array[idx];
5008 int rx_int = 0, total_rx_count = 0;
5010 struct qlnx_tx_queue *txq;
5013 lro_enable = ha->ifp->if_capenable & IFCAP_LRO;
5015 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
5018 for (tc = 0; tc < ha->num_tc; tc++) {
5022 if((int)(elem_left =
5023 ecore_chain_get_elem_left(&txq->tx_pbl)) <
5024 QLNX_TX_ELEM_THRESH) {
5026 if (mtx_trylock(&fp->tx_mtx)) {
5027 #ifdef QLNX_TRACE_PERF_DATA
5028 tx_compl = fp->tx_pkts_completed;
5031 qlnx_tx_int(ha, fp, fp->txq[tc]);
5032 #ifdef QLNX_TRACE_PERF_DATA
5033 fp->tx_pkts_compl_intr +=
5034 (fp->tx_pkts_completed - tx_compl);
5035 if ((fp->tx_pkts_completed - tx_compl) <= 32)
5037 else if (((fp->tx_pkts_completed - tx_compl) > 32) &&
5038 ((fp->tx_pkts_completed - tx_compl) <= 64))
5040 else if(((fp->tx_pkts_completed - tx_compl) > 64) &&
5041 ((fp->tx_pkts_completed - tx_compl) <= 128))
5043 else if(((fp->tx_pkts_completed - tx_compl) > 128))
5046 mtx_unlock(&fp->tx_mtx);
5051 rx_int = qlnx_rx_int(ha, fp, ha->rx_pkt_threshold,
5055 fp->rx_pkts += rx_int;
5056 total_rx_count += rx_int;
5061 #ifdef QLNX_SOFT_LRO
5063 struct lro_ctrl *lro;
5065 lro = &fp->rxq->lro;
5067 if (lro_enable && total_rx_count) {
5069 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
5071 #ifdef QLNX_TRACE_LRO_CNT
5072 if (lro->lro_mbuf_count & ~1023)
5074 else if (lro->lro_mbuf_count & ~511)
5076 else if (lro->lro_mbuf_count & ~255)
5078 else if (lro->lro_mbuf_count & ~127)
5080 else if (lro->lro_mbuf_count & ~63)
5082 #endif /* #ifdef QLNX_TRACE_LRO_CNT */
5084 tcp_lro_flush_all(lro);
5087 struct lro_entry *queued;
5089 while ((!SLIST_EMPTY(&lro->lro_active))) {
5090 queued = SLIST_FIRST(&lro->lro_active);
5091 SLIST_REMOVE_HEAD(&lro->lro_active, \
5093 tcp_lro_flush(lro, queued);
5095 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
5098 #endif /* #ifdef QLNX_SOFT_LRO */
5100 ecore_sb_update_sb_idx(fp->sb_info);
5102 ecore_sb_ack(fp->sb_info, IGU_INT_ENABLE, 1);
5110 * slow path interrupt processing function
5111 * can be invoked in polled mode or in interrupt mode via taskqueue.
5114 qlnx_sp_isr(void *arg)
5116 struct ecore_hwfn *p_hwfn;
5121 ha = (qlnx_host_t *)p_hwfn->p_dev;
5123 ha->sp_interrupts++;
5125 QL_DPRINT2(ha, "enter\n");
5127 ecore_int_sp_dpc(p_hwfn);
5129 QL_DPRINT2(ha, "exit\n");
5134 /*****************************************************************************
5135 * Support Functions for DMA'able Memory
5136 *****************************************************************************/
5139 qlnx_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
5141 *((bus_addr_t *)arg) = 0;
5144 printf("%s: bus_dmamap_load failed (%d)\n", __func__, error);
5148 *((bus_addr_t *)arg) = segs[0].ds_addr;
5154 qlnx_alloc_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
5162 ret = bus_dma_tag_create(
5163 ha->parent_tag,/* parent */
5165 ((bus_size_t)(1ULL << 32)),/* boundary */
5166 BUS_SPACE_MAXADDR, /* lowaddr */
5167 BUS_SPACE_MAXADDR, /* highaddr */
5168 NULL, NULL, /* filter, filterarg */
5169 dma_buf->size, /* maxsize */
5171 dma_buf->size, /* maxsegsize */
5173 NULL, NULL, /* lockfunc, lockarg */
5177 QL_DPRINT1(ha, "could not create dma tag\n");
5178 goto qlnx_alloc_dmabuf_exit;
5180 ret = bus_dmamem_alloc(dma_buf->dma_tag,
5181 (void **)&dma_buf->dma_b,
5182 (BUS_DMA_ZERO | BUS_DMA_COHERENT | BUS_DMA_NOWAIT),
5185 bus_dma_tag_destroy(dma_buf->dma_tag);
5186 QL_DPRINT1(ha, "bus_dmamem_alloc failed\n");
5187 goto qlnx_alloc_dmabuf_exit;
5190 ret = bus_dmamap_load(dma_buf->dma_tag,
5194 qlnx_dmamap_callback,
5195 &b_addr, BUS_DMA_NOWAIT);
5197 if (ret || !b_addr) {
5198 bus_dma_tag_destroy(dma_buf->dma_tag);
5199 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b,
5202 goto qlnx_alloc_dmabuf_exit;
5205 dma_buf->dma_addr = b_addr;
5207 qlnx_alloc_dmabuf_exit:
5213 qlnx_free_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
5215 bus_dmamap_unload(dma_buf->dma_tag, dma_buf->dma_map);
5216 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b, dma_buf->dma_map);
5217 bus_dma_tag_destroy(dma_buf->dma_tag);
5222 qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys, uint32_t size)
5229 ha = (qlnx_host_t *)ecore_dev;
5232 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5234 memset(&dma_buf, 0, sizeof (qlnx_dma_t));
5236 dma_buf.size = size + PAGE_SIZE;
5237 dma_buf.alignment = 8;
5239 if (qlnx_alloc_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf) != 0)
5241 bzero((uint8_t *)dma_buf.dma_b, dma_buf.size);
5243 *phys = dma_buf.dma_addr;
5245 dma_p = (qlnx_dma_t *)((uint8_t *)dma_buf.dma_b + size);
5247 memcpy(dma_p, &dma_buf, sizeof(qlnx_dma_t));
5249 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
5250 (void *)dma_buf.dma_map, (void *)dma_buf.dma_tag,
5251 dma_buf.dma_b, (void *)dma_buf.dma_addr, size);
5253 return (dma_buf.dma_b);
5257 qlnx_dma_free_coherent(void *ecore_dev, void *v_addr, bus_addr_t phys,
5260 qlnx_dma_t dma_buf, *dma_p;
5264 ha = (qlnx_host_t *)ecore_dev;
5270 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5272 dma_p = (qlnx_dma_t *)((uint8_t *)v_addr + size);
5274 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
5275 (void *)dma_p->dma_map, (void *)dma_p->dma_tag,
5276 dma_p->dma_b, (void *)dma_p->dma_addr, size);
5280 if (!ha->qlnxr_debug)
5281 qlnx_free_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf);
5286 qlnx_alloc_parent_dma_tag(qlnx_host_t *ha)
5294 * Allocate parent DMA Tag
5296 ret = bus_dma_tag_create(
5297 bus_get_dma_tag(dev), /* parent */
5298 1,((bus_size_t)(1ULL << 32)),/* alignment, boundary */
5299 BUS_SPACE_MAXADDR, /* lowaddr */
5300 BUS_SPACE_MAXADDR, /* highaddr */
5301 NULL, NULL, /* filter, filterarg */
5302 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
5304 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
5306 NULL, NULL, /* lockfunc, lockarg */
5310 QL_DPRINT1(ha, "could not create parent dma tag\n");
5314 ha->flags.parent_tag = 1;
5320 qlnx_free_parent_dma_tag(qlnx_host_t *ha)
5322 if (ha->parent_tag != NULL) {
5323 bus_dma_tag_destroy(ha->parent_tag);
5324 ha->parent_tag = NULL;
5330 qlnx_alloc_tx_dma_tag(qlnx_host_t *ha)
5332 if (bus_dma_tag_create(NULL, /* parent */
5333 1, 0, /* alignment, bounds */
5334 BUS_SPACE_MAXADDR, /* lowaddr */
5335 BUS_SPACE_MAXADDR, /* highaddr */
5336 NULL, NULL, /* filter, filterarg */
5337 QLNX_MAX_TSO_FRAME_SIZE, /* maxsize */
5338 QLNX_MAX_SEGMENTS, /* nsegments */
5339 QLNX_MAX_TX_MBUF_SIZE, /* maxsegsize */
5341 NULL, /* lockfunc */
5342 NULL, /* lockfuncarg */
5345 QL_DPRINT1(ha, "tx_tag alloc failed\n");
5353 qlnx_free_tx_dma_tag(qlnx_host_t *ha)
5355 if (ha->tx_tag != NULL) {
5356 bus_dma_tag_destroy(ha->tx_tag);
5363 qlnx_alloc_rx_dma_tag(qlnx_host_t *ha)
5365 if (bus_dma_tag_create(NULL, /* parent */
5366 1, 0, /* alignment, bounds */
5367 BUS_SPACE_MAXADDR, /* lowaddr */
5368 BUS_SPACE_MAXADDR, /* highaddr */
5369 NULL, NULL, /* filter, filterarg */
5370 MJUM9BYTES, /* maxsize */
5372 MJUM9BYTES, /* maxsegsize */
5374 NULL, /* lockfunc */
5375 NULL, /* lockfuncarg */
5378 QL_DPRINT1(ha, " rx_tag alloc failed\n");
5386 qlnx_free_rx_dma_tag(qlnx_host_t *ha)
5388 if (ha->rx_tag != NULL) {
5389 bus_dma_tag_destroy(ha->rx_tag);
5395 /*********************************
5396 * Exported functions
5397 *********************************/
5399 qlnx_pci_bus_get_bar_size(void *ecore_dev, uint8_t bar_id)
5403 bar_id = bar_id * 2;
5405 bar_size = bus_get_resource_count(((qlnx_host_t *)ecore_dev)->pci_dev,
5413 qlnx_pci_read_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t *reg_value)
5415 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5421 qlnx_pci_read_config_word(void *ecore_dev, uint32_t pci_reg,
5422 uint16_t *reg_value)
5424 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5430 qlnx_pci_read_config_dword(void *ecore_dev, uint32_t pci_reg,
5431 uint32_t *reg_value)
5433 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5439 qlnx_pci_write_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t reg_value)
5441 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5442 pci_reg, reg_value, 1);
5447 qlnx_pci_write_config_word(void *ecore_dev, uint32_t pci_reg,
5450 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5451 pci_reg, reg_value, 2);
5456 qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg,
5459 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5460 pci_reg, reg_value, 4);
5465 qlnx_pci_find_capability(void *ecore_dev, int cap)
5472 if (pci_find_cap(ha->pci_dev, PCIY_EXPRESS, ®) == 0)
5475 QL_DPRINT1(ha, "failed\n");
5481 qlnx_pci_find_ext_capability(void *ecore_dev, int ext_cap)
5488 if (pci_find_extcap(ha->pci_dev, ext_cap, ®) == 0)
5491 QL_DPRINT1(ha, "failed\n");
5497 qlnx_reg_rd32(void *hwfn, uint32_t reg_addr)
5500 struct ecore_hwfn *p_hwfn;
5504 data32 = bus_read_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5505 (bus_size_t)(p_hwfn->reg_offset + reg_addr));
5511 qlnx_reg_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5513 struct ecore_hwfn *p_hwfn = hwfn;
5515 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5516 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5522 qlnx_reg_wr16(void *hwfn, uint32_t reg_addr, uint16_t value)
5524 struct ecore_hwfn *p_hwfn = hwfn;
5526 bus_write_2(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5527 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5532 qlnx_dbell_wr32_db(void *hwfn, void *reg_addr, uint32_t value)
5534 struct ecore_dev *cdev;
5535 struct ecore_hwfn *p_hwfn;
5540 cdev = p_hwfn->p_dev;
5542 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)(p_hwfn->doorbells));
5543 bus_write_4(((qlnx_host_t *)cdev)->pci_dbells, offset, value);
5549 qlnx_dbell_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5551 struct ecore_hwfn *p_hwfn = hwfn;
5553 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_dbells, \
5554 (bus_size_t)(p_hwfn->db_offset + reg_addr), value);
5560 qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr)
5564 struct ecore_dev *cdev;
5566 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5567 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5569 data32 = bus_read_4(((qlnx_host_t *)cdev)->pci_reg, offset);
5575 qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value)
5578 struct ecore_dev *cdev;
5580 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5581 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5583 bus_write_4(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5589 qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value)
5592 struct ecore_dev *cdev;
5594 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5595 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5597 bus_write_8(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5602 qlnx_zalloc(uint32_t size)
5606 va = malloc((unsigned long)size, M_QLNXBUF, M_NOWAIT);
5608 return ((void *)va);
5612 qlnx_barrier(void *p_hwfn)
5616 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5617 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_WRITE);
5621 qlnx_link_update(void *p_hwfn)
5624 int prev_link_state;
5626 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5628 qlnx_fill_link(ha, p_hwfn, &ha->if_link);
5630 prev_link_state = ha->link_up;
5631 ha->link_up = ha->if_link.link_up;
5633 if (prev_link_state != ha->link_up) {
5635 if_link_state_change(ha->ifp, LINK_STATE_UP);
5637 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
5641 #ifdef CONFIG_ECORE_SRIOV
5643 if (qlnx_vf_device(ha) != 0) {
5644 if (ha->sriov_initialized)
5645 qlnx_inform_vf_link_state(p_hwfn, ha);
5648 #endif /* #ifdef CONFIG_ECORE_SRIOV */
5649 #endif /* #ifdef QLNX_VF */
5655 __qlnx_osal_vf_fill_acquire_resc_req(struct ecore_hwfn *p_hwfn,
5656 struct ecore_vf_acquire_sw_info *p_sw_info)
5658 p_sw_info->driver_version = (QLNX_VERSION_MAJOR << 24) |
5659 (QLNX_VERSION_MINOR << 16) |
5661 p_sw_info->os_type = VFPF_ACQUIRE_OS_FREEBSD;
5667 qlnx_osal_vf_fill_acquire_resc_req(void *p_hwfn, void *p_resc_req,
5670 __qlnx_osal_vf_fill_acquire_resc_req(p_hwfn, p_sw_info);
5676 qlnx_fill_link(qlnx_host_t *ha, struct ecore_hwfn *hwfn,
5677 struct qlnx_link_output *if_link)
5679 struct ecore_mcp_link_params link_params;
5680 struct ecore_mcp_link_state link_state;
5682 struct ecore_ptt *p_ptt = NULL;
5685 memset(if_link, 0, sizeof(*if_link));
5686 memset(&link_params, 0, sizeof(struct ecore_mcp_link_params));
5687 memset(&link_state, 0, sizeof(struct ecore_mcp_link_state));
5689 ha = (qlnx_host_t *)hwfn->p_dev;
5691 /* Prepare source inputs */
5692 /* we only deal with physical functions */
5693 if (qlnx_vf_device(ha) != 0) {
5695 p_ptt = ecore_ptt_acquire(hwfn);
5697 if (p_ptt == NULL) {
5698 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
5702 ecore_mcp_get_media_type(hwfn, p_ptt, &if_link->media_type);
5703 ecore_ptt_release(hwfn, p_ptt);
5705 memcpy(&link_params, ecore_mcp_get_link_params(hwfn),
5706 sizeof(link_params));
5707 memcpy(&link_state, ecore_mcp_get_link_state(hwfn),
5708 sizeof(link_state));
5710 ecore_mcp_get_media_type(hwfn, NULL, &if_link->media_type);
5711 ecore_vf_read_bulletin(hwfn, &p_change);
5712 ecore_vf_get_link_params(hwfn, &link_params);
5713 ecore_vf_get_link_state(hwfn, &link_state);
5716 /* Set the link parameters to pass to protocol driver */
5717 if (link_state.link_up) {
5718 if_link->link_up = true;
5719 if_link->speed = link_state.speed;
5722 if_link->supported_caps = QLNX_LINK_CAP_FIBRE;
5724 if (link_params.speed.autoneg)
5725 if_link->supported_caps |= QLNX_LINK_CAP_Autoneg;
5727 if (link_params.pause.autoneg ||
5728 (link_params.pause.forced_rx && link_params.pause.forced_tx))
5729 if_link->supported_caps |= QLNX_LINK_CAP_Asym_Pause;
5731 if (link_params.pause.autoneg || link_params.pause.forced_rx ||
5732 link_params.pause.forced_tx)
5733 if_link->supported_caps |= QLNX_LINK_CAP_Pause;
5735 if (link_params.speed.advertised_speeds &
5736 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
5737 if_link->supported_caps |= QLNX_LINK_CAP_1000baseT_Half |
5738 QLNX_LINK_CAP_1000baseT_Full;
5740 if (link_params.speed.advertised_speeds &
5741 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
5742 if_link->supported_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5744 if (link_params.speed.advertised_speeds &
5745 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
5746 if_link->supported_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5748 if (link_params.speed.advertised_speeds &
5749 NVM_CFG1_PORT_DRV_LINK_SPEED_40G)
5750 if_link->supported_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5752 if (link_params.speed.advertised_speeds &
5753 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
5754 if_link->supported_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5756 if (link_params.speed.advertised_speeds &
5757 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
5758 if_link->supported_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5760 if_link->advertised_caps = if_link->supported_caps;
5762 if_link->autoneg = link_params.speed.autoneg;
5763 if_link->duplex = QLNX_LINK_DUPLEX;
5765 /* Link partner capabilities */
5767 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_HD)
5768 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Half;
5770 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_FD)
5771 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Full;
5773 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_10G)
5774 if_link->link_partner_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5776 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_25G)
5777 if_link->link_partner_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5779 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_40G)
5780 if_link->link_partner_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5782 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_50G)
5783 if_link->link_partner_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5785 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_100G)
5786 if_link->link_partner_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5788 if (link_state.an_complete)
5789 if_link->link_partner_caps |= QLNX_LINK_CAP_Autoneg;
5791 if (link_state.partner_adv_pause)
5792 if_link->link_partner_caps |= QLNX_LINK_CAP_Pause;
5794 if ((link_state.partner_adv_pause ==
5795 ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE) ||
5796 (link_state.partner_adv_pause ==
5797 ECORE_LINK_PARTNER_BOTH_PAUSE))
5798 if_link->link_partner_caps |= QLNX_LINK_CAP_Asym_Pause;
5804 qlnx_schedule_recovery(void *p_hwfn)
5808 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5810 if (qlnx_vf_device(ha) != 0) {
5811 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
5818 qlnx_nic_setup(struct ecore_dev *cdev, struct ecore_pf_params *func_params)
5822 for (i = 0; i < cdev->num_hwfns; i++) {
5823 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
5824 p_hwfn->pf_params = *func_params;
5826 #ifdef QLNX_ENABLE_IWARP
5827 if (qlnx_vf_device((qlnx_host_t *)cdev) != 0) {
5828 p_hwfn->using_ll2 = true;
5830 #endif /* #ifdef QLNX_ENABLE_IWARP */
5834 rc = ecore_resc_alloc(cdev);
5836 goto qlnx_nic_setup_exit;
5838 ecore_resc_setup(cdev);
5840 qlnx_nic_setup_exit:
5846 qlnx_nic_start(struct ecore_dev *cdev)
5849 struct ecore_hw_init_params params;
5851 bzero(¶ms, sizeof (struct ecore_hw_init_params));
5853 params.p_tunn = NULL;
5854 params.b_hw_start = true;
5855 params.int_mode = cdev->int_mode;
5856 params.allow_npar_tx_switch = true;
5857 params.bin_fw_data = NULL;
5859 rc = ecore_hw_init(cdev, ¶ms);
5861 ecore_resc_free(cdev);
5869 qlnx_slowpath_start(qlnx_host_t *ha)
5871 struct ecore_dev *cdev;
5872 struct ecore_pf_params pf_params;
5875 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
5876 pf_params.eth_pf_params.num_cons =
5877 (ha->num_rss) * (ha->num_tc + 1);
5879 #ifdef QLNX_ENABLE_IWARP
5880 if (qlnx_vf_device(ha) != 0) {
5881 if(ha->personality == ECORE_PCI_ETH_IWARP) {
5882 device_printf(ha->pci_dev, "setting parameters required by iWARP dev\n");
5883 pf_params.rdma_pf_params.num_qps = 1024;
5884 pf_params.rdma_pf_params.num_srqs = 1024;
5885 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5886 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_IWARP;
5887 } else if(ha->personality == ECORE_PCI_ETH_ROCE) {
5888 device_printf(ha->pci_dev, "setting parameters required by RoCE dev\n");
5889 pf_params.rdma_pf_params.num_qps = 8192;
5890 pf_params.rdma_pf_params.num_srqs = 8192;
5891 //pf_params.rdma_pf_params.min_dpis = 0;
5892 pf_params.rdma_pf_params.min_dpis = 8;
5893 pf_params.rdma_pf_params.roce_edpm_mode = 0;
5894 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5895 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_ROCE;
5898 #endif /* #ifdef QLNX_ENABLE_IWARP */
5902 rc = qlnx_nic_setup(cdev, &pf_params);
5904 goto qlnx_slowpath_start_exit;
5906 cdev->int_mode = ECORE_INT_MODE_MSIX;
5907 cdev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
5909 #ifdef QLNX_MAX_COALESCE
5910 cdev->rx_coalesce_usecs = 255;
5911 cdev->tx_coalesce_usecs = 255;
5914 rc = qlnx_nic_start(cdev);
5916 ha->rx_coalesce_usecs = cdev->rx_coalesce_usecs;
5917 ha->tx_coalesce_usecs = cdev->tx_coalesce_usecs;
5919 #ifdef QLNX_USER_LLDP
5920 (void)qlnx_set_lldp_tlvx(ha, NULL);
5921 #endif /* #ifdef QLNX_USER_LLDP */
5923 qlnx_slowpath_start_exit:
5929 qlnx_slowpath_stop(qlnx_host_t *ha)
5931 struct ecore_dev *cdev;
5932 device_t dev = ha->pci_dev;
5937 ecore_hw_stop(cdev);
5939 for (i = 0; i < ha->cdev.num_hwfns; i++) {
5941 if (ha->sp_handle[i])
5942 (void)bus_teardown_intr(dev, ha->sp_irq[i],
5945 ha->sp_handle[i] = NULL;
5948 (void) bus_release_resource(dev, SYS_RES_IRQ,
5949 ha->sp_irq_rid[i], ha->sp_irq[i]);
5950 ha->sp_irq[i] = NULL;
5953 ecore_resc_free(cdev);
5959 qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
5960 char ver_str[VER_SIZE])
5964 memcpy(cdev->name, name, NAME_SIZE);
5966 for_each_hwfn(cdev, i) {
5967 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
5970 cdev->drv_type = DRV_ID_DRV_TYPE_FREEBSD;
5976 qlnx_get_protocol_stats(void *cdev, int proto_type, void *proto_stats)
5978 enum ecore_mcp_protocol_type type;
5979 union ecore_mcp_protocol_stats *stats;
5980 struct ecore_eth_stats eth_stats;
5984 stats = proto_stats;
5989 case ECORE_MCP_LAN_STATS:
5990 ecore_get_vport_stats((struct ecore_dev *)cdev, ð_stats);
5991 stats->lan_stats.ucast_rx_pkts = eth_stats.common.rx_ucast_pkts;
5992 stats->lan_stats.ucast_tx_pkts = eth_stats.common.tx_ucast_pkts;
5993 stats->lan_stats.fcs_err = -1;
5997 ha->err_get_proto_invalid_type++;
5999 QL_DPRINT1(ha, "invalid protocol type 0x%x\n", type);
6006 qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver)
6008 struct ecore_hwfn *p_hwfn;
6009 struct ecore_ptt *p_ptt;
6011 p_hwfn = &ha->cdev.hwfns[0];
6012 p_ptt = ecore_ptt_acquire(p_hwfn);
6014 if (p_ptt == NULL) {
6015 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
6018 ecore_mcp_get_mfw_ver(p_hwfn, p_ptt, mfw_ver, NULL);
6020 ecore_ptt_release(p_hwfn, p_ptt);
6026 qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size)
6028 struct ecore_hwfn *p_hwfn;
6029 struct ecore_ptt *p_ptt;
6031 p_hwfn = &ha->cdev.hwfns[0];
6032 p_ptt = ecore_ptt_acquire(p_hwfn);
6034 if (p_ptt == NULL) {
6035 QL_DPRINT1(ha,"ecore_ptt_acquire failed\n");
6038 ecore_mcp_get_flash_size(p_hwfn, p_ptt, flash_size);
6040 ecore_ptt_release(p_hwfn, p_ptt);
6046 qlnx_alloc_mem_arrays(qlnx_host_t *ha)
6048 struct ecore_dev *cdev;
6052 bzero(&ha->txq_array[0], (sizeof(struct qlnx_tx_queue) * QLNX_MAX_RSS));
6053 bzero(&ha->rxq_array[0], (sizeof(struct qlnx_rx_queue) * QLNX_MAX_RSS));
6054 bzero(&ha->sb_array[0], (sizeof(struct ecore_sb_info) * QLNX_MAX_RSS));
6060 qlnx_init_fp(qlnx_host_t *ha)
6062 int rss_id, txq_array_index, tc;
6064 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
6066 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
6068 fp->rss_id = rss_id;
6070 fp->sb_info = &ha->sb_array[rss_id];
6071 fp->rxq = &ha->rxq_array[rss_id];
6072 fp->rxq->rxq_id = rss_id;
6074 for (tc = 0; tc < ha->num_tc; tc++) {
6075 txq_array_index = tc * ha->num_rss + rss_id;
6076 fp->txq[tc] = &ha->txq_array[txq_array_index];
6077 fp->txq[tc]->index = txq_array_index;
6080 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", qlnx_name_str,
6083 fp->tx_ring_full = 0;
6085 /* reset all the statistics counters */
6087 fp->tx_pkts_processed = 0;
6088 fp->tx_pkts_freed = 0;
6089 fp->tx_pkts_transmitted = 0;
6090 fp->tx_pkts_completed = 0;
6092 #ifdef QLNX_TRACE_PERF_DATA
6093 fp->tx_pkts_trans_ctx = 0;
6094 fp->tx_pkts_compl_ctx = 0;
6095 fp->tx_pkts_trans_fp = 0;
6096 fp->tx_pkts_compl_fp = 0;
6097 fp->tx_pkts_compl_intr = 0;
6099 fp->tx_lso_wnd_min_len = 0;
6101 fp->tx_nsegs_gt_elem_left = 0;
6102 fp->tx_tso_max_nsegs = 0;
6103 fp->tx_tso_min_nsegs = 0;
6104 fp->err_tx_nsegs_gt_elem_left = 0;
6105 fp->err_tx_dmamap_create = 0;
6106 fp->err_tx_defrag_dmamap_load = 0;
6107 fp->err_tx_non_tso_max_seg = 0;
6108 fp->err_tx_dmamap_load = 0;
6109 fp->err_tx_defrag = 0;
6110 fp->err_tx_free_pkt_null = 0;
6111 fp->err_tx_cons_idx_conflict = 0;
6114 fp->err_m_getcl = 0;
6115 fp->err_m_getjcl = 0;
6121 qlnx_free_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info)
6123 struct ecore_dev *cdev;
6127 if (sb_info->sb_virt) {
6128 OSAL_DMA_FREE_COHERENT(cdev, ((void *)sb_info->sb_virt),
6129 (sb_info->sb_phys), (sizeof(*sb_info->sb_virt)));
6130 sb_info->sb_virt = NULL;
6135 qlnx_sb_init(struct ecore_dev *cdev, struct ecore_sb_info *sb_info,
6136 void *sb_virt_addr, bus_addr_t sb_phy_addr, u16 sb_id)
6138 struct ecore_hwfn *p_hwfn;
6142 hwfn_index = sb_id % cdev->num_hwfns;
6143 p_hwfn = &cdev->hwfns[hwfn_index];
6144 rel_sb_id = sb_id / cdev->num_hwfns;
6146 QL_DPRINT2(((qlnx_host_t *)cdev),
6147 "hwfn_index = %d p_hwfn = %p sb_id = 0x%x rel_sb_id = 0x%x \
6148 sb_info = %p sb_virt_addr = %p sb_phy_addr = %p\n",
6149 hwfn_index, p_hwfn, sb_id, rel_sb_id, sb_info,
6150 sb_virt_addr, (void *)sb_phy_addr);
6152 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
6153 sb_virt_addr, sb_phy_addr, rel_sb_id);
6158 /* This function allocates fast-path status block memory */
6160 qlnx_alloc_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info, u16 sb_id)
6162 struct status_block_e4 *sb_virt;
6166 struct ecore_dev *cdev;
6170 size = sizeof(*sb_virt);
6171 sb_virt = OSAL_DMA_ALLOC_COHERENT(cdev, (&sb_phys), size);
6174 QL_DPRINT1(ha, "Status block allocation failed\n");
6178 rc = qlnx_sb_init(cdev, sb_info, sb_virt, sb_phys, sb_id);
6180 OSAL_DMA_FREE_COHERENT(cdev, sb_virt, sb_phys, size);
6187 qlnx_free_rx_buffers(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6190 struct sw_rx_data *rx_buf;
6192 for (i = 0; i < rxq->num_rx_buffers; i++) {
6194 rx_buf = &rxq->sw_rx_ring[i];
6196 if (rx_buf->data != NULL) {
6197 if (rx_buf->map != NULL) {
6198 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
6199 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
6202 m_freem(rx_buf->data);
6203 rx_buf->data = NULL;
6210 qlnx_free_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6212 struct ecore_dev *cdev;
6217 qlnx_free_rx_buffers(ha, rxq);
6219 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
6220 qlnx_free_tpa_mbuf(ha, &rxq->tpa_info[i]);
6221 if (rxq->tpa_info[i].mpf != NULL)
6222 m_freem(rxq->tpa_info[i].mpf);
6225 bzero((void *)&rxq->sw_rx_ring[0],
6226 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
6228 /* Free the real RQ ring used by FW */
6229 if (rxq->rx_bd_ring.p_virt_addr) {
6230 ecore_chain_free(cdev, &rxq->rx_bd_ring);
6231 rxq->rx_bd_ring.p_virt_addr = NULL;
6234 /* Free the real completion ring used by FW */
6235 if (rxq->rx_comp_ring.p_virt_addr &&
6236 rxq->rx_comp_ring.pbl_sp.p_virt_table) {
6237 ecore_chain_free(cdev, &rxq->rx_comp_ring);
6238 rxq->rx_comp_ring.p_virt_addr = NULL;
6239 rxq->rx_comp_ring.pbl_sp.p_virt_table = NULL;
6242 #ifdef QLNX_SOFT_LRO
6244 struct lro_ctrl *lro;
6249 #endif /* #ifdef QLNX_SOFT_LRO */
6255 qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6257 register struct mbuf *mp;
6258 uint16_t rx_buf_size;
6259 struct sw_rx_data *sw_rx_data;
6260 struct eth_rx_bd *rx_bd;
6261 dma_addr_t dma_addr;
6263 bus_dma_segment_t segs[1];
6266 struct ecore_dev *cdev;
6270 rx_buf_size = rxq->rx_buf_size;
6272 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
6275 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
6279 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
6281 map = (bus_dmamap_t)0;
6283 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6285 dma_addr = segs[0].ds_addr;
6287 if (ret || !dma_addr || (nsegs != 1)) {
6289 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6290 ret, (long long unsigned int)dma_addr, nsegs);
6294 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
6295 sw_rx_data->data = mp;
6296 sw_rx_data->dma_addr = dma_addr;
6297 sw_rx_data->map = map;
6299 /* Advance PROD and get BD pointer */
6300 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
6301 rx_bd->addr.hi = htole32(U64_HI(dma_addr));
6302 rx_bd->addr.lo = htole32(U64_LO(dma_addr));
6303 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6305 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6311 qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
6312 struct qlnx_agg_info *tpa)
6315 dma_addr_t dma_addr;
6317 bus_dma_segment_t segs[1];
6320 struct sw_rx_data *rx_buf;
6322 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
6325 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
6329 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
6331 map = (bus_dmamap_t)0;
6333 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6335 dma_addr = segs[0].ds_addr;
6337 if (ret || !dma_addr || (nsegs != 1)) {
6339 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6340 ret, (long long unsigned int)dma_addr, nsegs);
6344 rx_buf = &tpa->rx_buf;
6346 memset(rx_buf, 0, sizeof (struct sw_rx_data));
6349 rx_buf->dma_addr = dma_addr;
6352 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6358 qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa)
6360 struct sw_rx_data *rx_buf;
6362 rx_buf = &tpa->rx_buf;
6364 if (rx_buf->data != NULL) {
6365 if (rx_buf->map != NULL) {
6366 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
6367 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
6370 m_freem(rx_buf->data);
6371 rx_buf->data = NULL;
6376 /* This function allocates all memory needed per Rx queue */
6378 qlnx_alloc_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6380 int i, rc, num_allocated;
6382 struct ecore_dev *cdev;
6387 rxq->num_rx_buffers = RX_RING_SIZE;
6389 rxq->rx_buf_size = ha->rx_buf_size;
6391 /* Allocate the parallel driver ring for Rx buffers */
6392 bzero((void *)&rxq->sw_rx_ring[0],
6393 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
6395 /* Allocate FW Rx ring */
6397 rc = ecore_chain_alloc(cdev,
6398 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6399 ECORE_CHAIN_MODE_NEXT_PTR,
6400 ECORE_CHAIN_CNT_TYPE_U16,
6402 sizeof(struct eth_rx_bd),
6403 &rxq->rx_bd_ring, NULL);
6408 /* Allocate FW completion ring */
6409 rc = ecore_chain_alloc(cdev,
6410 ECORE_CHAIN_USE_TO_CONSUME,
6411 ECORE_CHAIN_MODE_PBL,
6412 ECORE_CHAIN_CNT_TYPE_U16,
6414 sizeof(union eth_rx_cqe),
6415 &rxq->rx_comp_ring, NULL);
6420 /* Allocate buffers for the Rx ring */
6422 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
6423 rc = qlnx_alloc_tpa_mbuf(ha, rxq->rx_buf_size,
6430 for (i = 0; i < rxq->num_rx_buffers; i++) {
6431 rc = qlnx_alloc_rx_buffer(ha, rxq);
6436 if (!num_allocated) {
6437 QL_DPRINT1(ha, "Rx buffers allocation failed\n");
6439 } else if (num_allocated < rxq->num_rx_buffers) {
6440 QL_DPRINT1(ha, "Allocated less buffers than"
6441 " desired (%d allocated)\n", num_allocated);
6444 #ifdef QLNX_SOFT_LRO
6447 struct lro_ctrl *lro;
6451 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
6452 if (tcp_lro_init_args(lro, ifp, 0, rxq->num_rx_buffers)) {
6453 QL_DPRINT1(ha, "tcp_lro_init[%d] failed\n",
6458 if (tcp_lro_init(lro)) {
6459 QL_DPRINT1(ha, "tcp_lro_init[%d] failed\n",
6463 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
6467 #endif /* #ifdef QLNX_SOFT_LRO */
6471 qlnx_free_mem_rxq(ha, rxq);
6477 qlnx_free_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6478 struct qlnx_tx_queue *txq)
6480 struct ecore_dev *cdev;
6484 bzero((void *)&txq->sw_tx_ring[0],
6485 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6487 /* Free the real RQ ring used by FW */
6488 if (txq->tx_pbl.p_virt_addr) {
6489 ecore_chain_free(cdev, &txq->tx_pbl);
6490 txq->tx_pbl.p_virt_addr = NULL;
6495 /* This function allocates all memory needed per Tx queue */
6497 qlnx_alloc_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6498 struct qlnx_tx_queue *txq)
6500 int ret = ECORE_SUCCESS;
6501 union eth_tx_bd_types *p_virt;
6502 struct ecore_dev *cdev;
6506 bzero((void *)&txq->sw_tx_ring[0],
6507 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6509 /* Allocate the real Tx ring to be used by FW */
6510 ret = ecore_chain_alloc(cdev,
6511 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6512 ECORE_CHAIN_MODE_PBL,
6513 ECORE_CHAIN_CNT_TYPE_U16,
6516 &txq->tx_pbl, NULL);
6518 if (ret != ECORE_SUCCESS) {
6522 txq->num_tx_buffers = TX_RING_SIZE;
6527 qlnx_free_mem_txq(ha, fp, txq);
6532 qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6535 struct ifnet *ifp = ha->ifp;
6537 if (mtx_initialized(&fp->tx_mtx)) {
6539 if (fp->tx_br != NULL) {
6541 mtx_lock(&fp->tx_mtx);
6543 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
6544 fp->tx_pkts_freed++;
6548 mtx_unlock(&fp->tx_mtx);
6550 buf_ring_free(fp->tx_br, M_DEVBUF);
6553 mtx_destroy(&fp->tx_mtx);
6559 qlnx_free_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6563 qlnx_free_mem_sb(ha, fp->sb_info);
6565 qlnx_free_mem_rxq(ha, fp->rxq);
6567 for (tc = 0; tc < ha->num_tc; tc++)
6568 qlnx_free_mem_txq(ha, fp, fp->txq[tc]);
6574 qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6576 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
6577 "qlnx%d_fp%d_tx_mq_lock", ha->dev_unit, fp->rss_id);
6579 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
6581 fp->tx_br = buf_ring_alloc(TX_RING_SIZE, M_DEVBUF,
6582 M_NOWAIT, &fp->tx_mtx);
6583 if (fp->tx_br == NULL) {
6584 QL_DPRINT1(ha, "buf_ring_alloc failed for fp[%d, %d]\n",
6585 ha->dev_unit, fp->rss_id);
6592 qlnx_alloc_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6596 rc = qlnx_alloc_mem_sb(ha, fp->sb_info, fp->rss_id);
6600 if (ha->rx_jumbo_buf_eq_mtu) {
6601 if (ha->max_frame_size <= MCLBYTES)
6602 ha->rx_buf_size = MCLBYTES;
6603 else if (ha->max_frame_size <= MJUMPAGESIZE)
6604 ha->rx_buf_size = MJUMPAGESIZE;
6605 else if (ha->max_frame_size <= MJUM9BYTES)
6606 ha->rx_buf_size = MJUM9BYTES;
6607 else if (ha->max_frame_size <= MJUM16BYTES)
6608 ha->rx_buf_size = MJUM16BYTES;
6610 if (ha->max_frame_size <= MCLBYTES)
6611 ha->rx_buf_size = MCLBYTES;
6613 ha->rx_buf_size = MJUMPAGESIZE;
6616 rc = qlnx_alloc_mem_rxq(ha, fp->rxq);
6620 for (tc = 0; tc < ha->num_tc; tc++) {
6621 rc = qlnx_alloc_mem_txq(ha, fp, fp->txq[tc]);
6629 qlnx_free_mem_fp(ha, fp);
6634 qlnx_free_mem_load(qlnx_host_t *ha)
6637 struct ecore_dev *cdev;
6641 for (i = 0; i < ha->num_rss; i++) {
6642 struct qlnx_fastpath *fp = &ha->fp_array[i];
6644 qlnx_free_mem_fp(ha, fp);
6650 qlnx_alloc_mem_load(qlnx_host_t *ha)
6654 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
6655 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
6657 rc = qlnx_alloc_mem_fp(ha, fp);
6665 qlnx_start_vport(struct ecore_dev *cdev,
6669 u8 inner_vlan_removal_en_flg,
6674 struct ecore_sp_vport_start_params vport_start_params = { 0 };
6677 ha = (qlnx_host_t *)cdev;
6679 vport_start_params.remove_inner_vlan = inner_vlan_removal_en_flg;
6680 vport_start_params.tx_switching = 0;
6681 vport_start_params.handle_ptp_pkts = 0;
6682 vport_start_params.only_untagged = 0;
6683 vport_start_params.drop_ttl0 = drop_ttl0_flg;
6685 vport_start_params.tpa_mode =
6686 (hw_lro_enable ? ECORE_TPA_MODE_RSC : ECORE_TPA_MODE_NONE);
6687 vport_start_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
6689 vport_start_params.vport_id = vport_id;
6690 vport_start_params.mtu = mtu;
6693 QL_DPRINT2(ha, "Setting mtu to %d and VPORT ID = %d\n", mtu, vport_id);
6695 for_each_hwfn(cdev, i) {
6696 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
6698 vport_start_params.concrete_fid = p_hwfn->hw_info.concrete_fid;
6699 vport_start_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6701 rc = ecore_sp_vport_start(p_hwfn, &vport_start_params);
6704 QL_DPRINT1(ha, "Failed to start VPORT V-PORT %d"
6705 " with MTU %d\n" , vport_id, mtu);
6709 ecore_hw_start_fastpath(p_hwfn);
6711 QL_DPRINT2(ha, "Started V-PORT %d with MTU %d\n",
6719 qlnx_update_vport(struct ecore_dev *cdev,
6720 struct qlnx_update_vport_params *params)
6722 struct ecore_sp_vport_update_params sp_params;
6723 int rc, i, j, fp_index;
6724 struct ecore_hwfn *p_hwfn;
6725 struct ecore_rss_params *rss;
6726 qlnx_host_t *ha = (qlnx_host_t *)cdev;
6727 struct qlnx_fastpath *fp;
6729 memset(&sp_params, 0, sizeof(sp_params));
6730 /* Translate protocol params into sp params */
6731 sp_params.vport_id = params->vport_id;
6733 sp_params.update_vport_active_rx_flg =
6734 params->update_vport_active_rx_flg;
6735 sp_params.vport_active_rx_flg = params->vport_active_rx_flg;
6737 sp_params.update_vport_active_tx_flg =
6738 params->update_vport_active_tx_flg;
6739 sp_params.vport_active_tx_flg = params->vport_active_tx_flg;
6741 sp_params.update_inner_vlan_removal_flg =
6742 params->update_inner_vlan_removal_flg;
6743 sp_params.inner_vlan_removal_flg = params->inner_vlan_removal_flg;
6745 sp_params.sge_tpa_params = params->sge_tpa_params;
6747 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
6748 * We need to re-fix the rss values per engine for CMT.
6750 if (params->rss_params->update_rss_config)
6751 sp_params.rss_params = params->rss_params;
6753 sp_params.rss_params = NULL;
6755 for_each_hwfn(cdev, i) {
6757 p_hwfn = &cdev->hwfns[i];
6759 if ((cdev->num_hwfns > 1) &&
6760 params->rss_params->update_rss_config &&
6761 params->rss_params->rss_enable) {
6763 rss = params->rss_params;
6765 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE; j++) {
6767 fp_index = ((cdev->num_hwfns * j) + i) %
6770 fp = &ha->fp_array[fp_index];
6771 rss->rss_ind_table[j] = fp->rxq->handle;
6774 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE;) {
6775 QL_DPRINT3(ha, "%p %p %p %p %p %p %p %p \n",
6776 rss->rss_ind_table[j],
6777 rss->rss_ind_table[j+1],
6778 rss->rss_ind_table[j+2],
6779 rss->rss_ind_table[j+3],
6780 rss->rss_ind_table[j+4],
6781 rss->rss_ind_table[j+5],
6782 rss->rss_ind_table[j+6],
6783 rss->rss_ind_table[j+7]);
6788 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6790 QL_DPRINT1(ha, "Update sp vport ID=%d\n", params->vport_id);
6792 rc = ecore_sp_vport_update(p_hwfn, &sp_params,
6793 ECORE_SPQ_MODE_EBLOCK, NULL);
6795 QL_DPRINT1(ha, "Failed to update VPORT\n");
6799 QL_DPRINT2(ha, "Updated V-PORT %d: tx_active_flag %d, \
6800 rx_active_flag %d [tx_update %d], [rx_update %d]\n",
6801 params->vport_id, params->vport_active_tx_flg,
6802 params->vport_active_rx_flg,
6803 params->update_vport_active_tx_flg,
6804 params->update_vport_active_rx_flg);
6811 qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq)
6813 struct eth_rx_bd *rx_bd_cons =
6814 ecore_chain_consume(&rxq->rx_bd_ring);
6815 struct eth_rx_bd *rx_bd_prod =
6816 ecore_chain_produce(&rxq->rx_bd_ring);
6817 struct sw_rx_data *sw_rx_data_cons =
6818 &rxq->sw_rx_ring[rxq->sw_rx_cons];
6819 struct sw_rx_data *sw_rx_data_prod =
6820 &rxq->sw_rx_ring[rxq->sw_rx_prod];
6822 sw_rx_data_prod->data = sw_rx_data_cons->data;
6823 memcpy(rx_bd_prod, rx_bd_cons, sizeof(struct eth_rx_bd));
6825 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
6826 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6832 qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn, struct qlnx_rx_queue *rxq)
6838 struct eth_rx_prod_data rx_prod_data;
6842 bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
6843 cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
6845 /* Update producers */
6846 rx_prods.rx_prod_data.bd_prod = htole16(bd_prod);
6847 rx_prods.rx_prod_data.cqe_prod = htole16(cqe_prod);
6849 /* Make sure that the BD and SGE data is updated before updating the
6850 * producers since FW might read the BD/SGE right after the producer
6855 internal_ram_wr(p_hwfn, rxq->hw_rxq_prod_addr,
6856 sizeof(rx_prods), &rx_prods.data32);
6858 /* mmiowb is needed to synchronize doorbell writes from more than one
6859 * processor. It guarantees that the write arrives to the device before
6860 * the napi lock is released and another qlnx_poll is called (possibly
6861 * on another CPU). Without this barrier, the next doorbell can bypass
6862 * this doorbell. This is applicable to IA64/Altix systems.
6869 static uint32_t qlnx_hash_key[] = {
6870 ((0x6d << 24)|(0x5a << 16)|(0x56 << 8)|0xda),
6871 ((0x25 << 24)|(0x5b << 16)|(0x0e << 8)|0xc2),
6872 ((0x41 << 24)|(0x67 << 16)|(0x25 << 8)|0x3d),
6873 ((0x43 << 24)|(0xa3 << 16)|(0x8f << 8)|0xb0),
6874 ((0xd0 << 24)|(0xca << 16)|(0x2b << 8)|0xcb),
6875 ((0xae << 24)|(0x7b << 16)|(0x30 << 8)|0xb4),
6876 ((0x77 << 24)|(0xcb << 16)|(0x2d << 8)|0xa3),
6877 ((0x80 << 24)|(0x30 << 16)|(0xf2 << 8)|0x0c),
6878 ((0x6a << 24)|(0x42 << 16)|(0xb7 << 8)|0x3b),
6879 ((0xbe << 24)|(0xac << 16)|(0x01 << 8)|0xfa)};
6882 qlnx_start_queues(qlnx_host_t *ha)
6884 int rc, tc, i, vport_id = 0,
6885 drop_ttl0_flg = 1, vlan_removal_en = 1,
6886 tx_switching = 0, hw_lro_enable = 0;
6887 struct ecore_dev *cdev = &ha->cdev;
6888 struct ecore_rss_params *rss_params = &ha->rss_params;
6889 struct qlnx_update_vport_params vport_update_params;
6891 struct ecore_hwfn *p_hwfn;
6892 struct ecore_sge_tpa_params tpa_params;
6893 struct ecore_queue_start_common_params qparams;
6894 struct qlnx_fastpath *fp;
6898 QL_DPRINT1(ha, "Num RSS = %d\n", ha->num_rss);
6901 QL_DPRINT1(ha, "Cannot update V-VPORT as active as there"
6902 " are no Rx queues\n");
6906 #ifndef QLNX_SOFT_LRO
6907 hw_lro_enable = ifp->if_capenable & IFCAP_LRO;
6908 #endif /* #ifndef QLNX_SOFT_LRO */
6910 rc = qlnx_start_vport(cdev, vport_id, ifp->if_mtu, drop_ttl0_flg,
6911 vlan_removal_en, tx_switching, hw_lro_enable);
6914 QL_DPRINT1(ha, "Start V-PORT failed %d\n", rc);
6918 QL_DPRINT2(ha, "Start vport ramrod passed, "
6919 "vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
6920 vport_id, (int)(ifp->if_mtu + 0xe), vlan_removal_en);
6923 struct ecore_rxq_start_ret_params rx_ret_params;
6924 struct ecore_txq_start_ret_params tx_ret_params;
6926 fp = &ha->fp_array[i];
6927 p_hwfn = &cdev->hwfns[(fp->rss_id % cdev->num_hwfns)];
6929 bzero(&qparams, sizeof(struct ecore_queue_start_common_params));
6930 bzero(&rx_ret_params,
6931 sizeof (struct ecore_rxq_start_ret_params));
6933 qparams.queue_id = i ;
6934 qparams.vport_id = vport_id;
6935 qparams.stats_id = vport_id;
6936 qparams.p_sb = fp->sb_info;
6937 qparams.sb_idx = RX_PI;
6940 rc = ecore_eth_rx_queue_start(p_hwfn,
6941 p_hwfn->hw_info.opaque_fid,
6943 fp->rxq->rx_buf_size, /* bd_max_bytes */
6944 /* bd_chain_phys_addr */
6945 fp->rxq->rx_bd_ring.p_phys_addr,
6947 ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring),
6949 ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring),
6953 QL_DPRINT1(ha, "Start RXQ #%d failed %d\n", i, rc);
6957 fp->rxq->hw_rxq_prod_addr = rx_ret_params.p_prod;
6958 fp->rxq->handle = rx_ret_params.p_handle;
6959 fp->rxq->hw_cons_ptr =
6960 &fp->sb_info->sb_virt->pi_array[RX_PI];
6962 qlnx_update_rx_prod(p_hwfn, fp->rxq);
6964 for (tc = 0; tc < ha->num_tc; tc++) {
6965 struct qlnx_tx_queue *txq = fp->txq[tc];
6968 sizeof(struct ecore_queue_start_common_params));
6969 bzero(&tx_ret_params,
6970 sizeof (struct ecore_txq_start_ret_params));
6972 qparams.queue_id = txq->index / cdev->num_hwfns ;
6973 qparams.vport_id = vport_id;
6974 qparams.stats_id = vport_id;
6975 qparams.p_sb = fp->sb_info;
6976 qparams.sb_idx = TX_PI(tc);
6978 rc = ecore_eth_tx_queue_start(p_hwfn,
6979 p_hwfn->hw_info.opaque_fid,
6981 /* bd_chain_phys_addr */
6982 ecore_chain_get_pbl_phys(&txq->tx_pbl),
6983 ecore_chain_get_page_cnt(&txq->tx_pbl),
6987 QL_DPRINT1(ha, "Start TXQ #%d failed %d\n",
6992 txq->doorbell_addr = tx_ret_params.p_doorbell;
6993 txq->handle = tx_ret_params.p_handle;
6996 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
6997 SET_FIELD(txq->tx_db.data.params,
6998 ETH_DB_DATA_DEST, DB_DEST_XCM);
6999 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
7001 SET_FIELD(txq->tx_db.data.params,
7002 ETH_DB_DATA_AGG_VAL_SEL,
7003 DQ_XCM_ETH_TX_BD_PROD_CMD);
7005 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
7009 /* Fill struct with RSS params */
7010 if (ha->num_rss > 1) {
7012 rss_params->update_rss_config = 1;
7013 rss_params->rss_enable = 1;
7014 rss_params->update_rss_capabilities = 1;
7015 rss_params->update_rss_ind_table = 1;
7016 rss_params->update_rss_key = 1;
7017 rss_params->rss_caps = ECORE_RSS_IPV4 | ECORE_RSS_IPV6 |
7018 ECORE_RSS_IPV4_TCP | ECORE_RSS_IPV6_TCP;
7019 rss_params->rss_table_size_log = 7; /* 2^7 = 128 */
7021 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
7022 fp = &ha->fp_array[(i % ha->num_rss)];
7023 rss_params->rss_ind_table[i] = fp->rxq->handle;
7026 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
7027 rss_params->rss_key[i] = (__le32)qlnx_hash_key[i];
7030 memset(rss_params, 0, sizeof(*rss_params));
7034 /* Prepare and send the vport enable */
7035 memset(&vport_update_params, 0, sizeof(vport_update_params));
7036 vport_update_params.vport_id = vport_id;
7037 vport_update_params.update_vport_active_tx_flg = 1;
7038 vport_update_params.vport_active_tx_flg = 1;
7039 vport_update_params.update_vport_active_rx_flg = 1;
7040 vport_update_params.vport_active_rx_flg = 1;
7041 vport_update_params.rss_params = rss_params;
7042 vport_update_params.update_inner_vlan_removal_flg = 1;
7043 vport_update_params.inner_vlan_removal_flg = 1;
7045 if (hw_lro_enable) {
7046 memset(&tpa_params, 0, sizeof (struct ecore_sge_tpa_params));
7048 tpa_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
7050 tpa_params.update_tpa_en_flg = 1;
7051 tpa_params.tpa_ipv4_en_flg = 1;
7052 tpa_params.tpa_ipv6_en_flg = 1;
7054 tpa_params.update_tpa_param_flg = 1;
7055 tpa_params.tpa_pkt_split_flg = 0;
7056 tpa_params.tpa_hdr_data_split_flg = 0;
7057 tpa_params.tpa_gro_consistent_flg = 0;
7058 tpa_params.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
7059 tpa_params.tpa_max_size = (uint16_t)(-1);
7060 tpa_params.tpa_min_size_to_start = ifp->if_mtu/2;
7061 tpa_params.tpa_min_size_to_cont = ifp->if_mtu/2;
7063 vport_update_params.sge_tpa_params = &tpa_params;
7066 rc = qlnx_update_vport(cdev, &vport_update_params);
7068 QL_DPRINT1(ha, "Update V-PORT failed %d\n", rc);
7076 qlnx_drain_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
7077 struct qlnx_tx_queue *txq)
7079 uint16_t hw_bd_cons;
7080 uint16_t ecore_cons_idx;
7082 QL_DPRINT2(ha, "enter\n");
7084 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
7086 while (hw_bd_cons !=
7087 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
7089 mtx_lock(&fp->tx_mtx);
7091 (void)qlnx_tx_int(ha, fp, txq);
7093 mtx_unlock(&fp->tx_mtx);
7095 qlnx_mdelay(__func__, 2);
7097 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
7100 QL_DPRINT2(ha, "[%d, %d]: done\n", fp->rss_id, txq->index);
7106 qlnx_stop_queues(qlnx_host_t *ha)
7108 struct qlnx_update_vport_params vport_update_params;
7109 struct ecore_dev *cdev;
7110 struct qlnx_fastpath *fp;
7115 /* Disable the vport */
7117 memset(&vport_update_params, 0, sizeof(vport_update_params));
7119 vport_update_params.vport_id = 0;
7120 vport_update_params.update_vport_active_tx_flg = 1;
7121 vport_update_params.vport_active_tx_flg = 0;
7122 vport_update_params.update_vport_active_rx_flg = 1;
7123 vport_update_params.vport_active_rx_flg = 0;
7124 vport_update_params.rss_params = &ha->rss_params;
7125 vport_update_params.rss_params->update_rss_config = 0;
7126 vport_update_params.rss_params->rss_enable = 0;
7127 vport_update_params.update_inner_vlan_removal_flg = 0;
7128 vport_update_params.inner_vlan_removal_flg = 0;
7130 QL_DPRINT1(ha, "Update vport ID= %d\n", vport_update_params.vport_id);
7132 rc = qlnx_update_vport(cdev, &vport_update_params);
7134 QL_DPRINT1(ha, "Failed to update vport\n");
7138 /* Flush Tx queues. If needed, request drain from MCP */
7140 fp = &ha->fp_array[i];
7142 for (tc = 0; tc < ha->num_tc; tc++) {
7143 struct qlnx_tx_queue *txq = fp->txq[tc];
7145 rc = qlnx_drain_txq(ha, fp, txq);
7151 /* Stop all Queues in reverse order*/
7152 for (i = ha->num_rss - 1; i >= 0; i--) {
7154 struct ecore_hwfn *p_hwfn = &cdev->hwfns[(i % cdev->num_hwfns)];
7156 fp = &ha->fp_array[i];
7158 /* Stop the Tx Queue(s)*/
7159 for (tc = 0; tc < ha->num_tc; tc++) {
7162 tx_queue_id = tc * ha->num_rss + i;
7163 rc = ecore_eth_tx_queue_stop(p_hwfn,
7164 fp->txq[tc]->handle);
7167 QL_DPRINT1(ha, "Failed to stop TXQ #%d\n",
7173 /* Stop the Rx Queue*/
7174 rc = ecore_eth_rx_queue_stop(p_hwfn, fp->rxq->handle, false,
7177 QL_DPRINT1(ha, "Failed to stop RXQ #%d\n", i);
7182 /* Stop the vport */
7183 for_each_hwfn(cdev, i) {
7185 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
7187 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 0);
7190 QL_DPRINT1(ha, "Failed to stop VPORT\n");
7199 qlnx_set_ucast_rx_mac(qlnx_host_t *ha,
7200 enum ecore_filter_opcode opcode,
7201 unsigned char mac[ETH_ALEN])
7203 struct ecore_filter_ucast ucast;
7204 struct ecore_dev *cdev;
7209 bzero(&ucast, sizeof(struct ecore_filter_ucast));
7211 ucast.opcode = opcode;
7212 ucast.type = ECORE_FILTER_MAC;
7213 ucast.is_rx_filter = 1;
7214 ucast.vport_to_add_to = 0;
7215 memcpy(&ucast.mac[0], mac, ETH_ALEN);
7217 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
7223 qlnx_remove_all_ucast_mac(qlnx_host_t *ha)
7225 struct ecore_filter_ucast ucast;
7226 struct ecore_dev *cdev;
7229 bzero(&ucast, sizeof(struct ecore_filter_ucast));
7231 ucast.opcode = ECORE_FILTER_REPLACE;
7232 ucast.type = ECORE_FILTER_MAC;
7233 ucast.is_rx_filter = 1;
7237 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
7243 qlnx_remove_all_mcast_mac(qlnx_host_t *ha)
7245 struct ecore_filter_mcast *mcast;
7246 struct ecore_dev *cdev;
7251 mcast = &ha->ecore_mcast;
7252 bzero(mcast, sizeof(struct ecore_filter_mcast));
7254 mcast->opcode = ECORE_FILTER_REMOVE;
7256 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
7258 if (ha->mcast[i].addr[0] || ha->mcast[i].addr[1] ||
7259 ha->mcast[i].addr[2] || ha->mcast[i].addr[3] ||
7260 ha->mcast[i].addr[4] || ha->mcast[i].addr[5]) {
7262 memcpy(&mcast->mac[i][0], &ha->mcast[i].addr[0], ETH_ALEN);
7263 mcast->num_mc_addrs++;
7266 mcast = &ha->ecore_mcast;
7268 rc = ecore_filter_mcast_cmd(cdev, mcast, ECORE_SPQ_MODE_CB, NULL);
7270 bzero(ha->mcast, (sizeof(qlnx_mcast_t) * QLNX_MAX_NUM_MULTICAST_ADDRS));
7277 qlnx_clean_filters(qlnx_host_t *ha)
7281 /* Remove all unicast macs */
7282 rc = qlnx_remove_all_ucast_mac(ha);
7286 /* Remove all multicast macs */
7287 rc = qlnx_remove_all_mcast_mac(ha);
7291 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_FLUSH, ha->primary_mac);
7297 qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter)
7299 struct ecore_filter_accept_flags accept;
7301 struct ecore_dev *cdev;
7305 bzero(&accept, sizeof(struct ecore_filter_accept_flags));
7307 accept.update_rx_mode_config = 1;
7308 accept.rx_accept_filter = filter;
7310 accept.update_tx_mode_config = 1;
7311 accept.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
7312 ECORE_ACCEPT_MCAST_MATCHED | ECORE_ACCEPT_BCAST;
7314 rc = ecore_filter_accept_cmd(cdev, 0, accept, false, false,
7315 ECORE_SPQ_MODE_CB, NULL);
7321 qlnx_set_rx_mode(qlnx_host_t *ha)
7326 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_REPLACE, ha->primary_mac);
7330 rc = qlnx_remove_all_mcast_mac(ha);
7334 filter = ECORE_ACCEPT_UCAST_MATCHED |
7335 ECORE_ACCEPT_MCAST_MATCHED |
7338 if (qlnx_vf_device(ha) == 0) {
7339 filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
7340 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
7342 ha->filter = filter;
7344 rc = qlnx_set_rx_accept_filter(ha, filter);
7350 qlnx_set_link(qlnx_host_t *ha, bool link_up)
7353 struct ecore_dev *cdev;
7354 struct ecore_hwfn *hwfn;
7355 struct ecore_ptt *ptt;
7357 if (qlnx_vf_device(ha) == 0)
7362 for_each_hwfn(cdev, i) {
7364 hwfn = &cdev->hwfns[i];
7366 ptt = ecore_ptt_acquire(hwfn);
7370 rc = ecore_mcp_set_link(hwfn, ptt, link_up);
7372 ecore_ptt_release(hwfn, ptt);
7380 #if __FreeBSD_version >= 1100000
7382 qlnx_get_counter(if_t ifp, ift_counter cnt)
7387 ha = (qlnx_host_t *)if_getsoftc(ifp);
7391 case IFCOUNTER_IPACKETS:
7392 count = ha->hw_stats.common.rx_ucast_pkts +
7393 ha->hw_stats.common.rx_mcast_pkts +
7394 ha->hw_stats.common.rx_bcast_pkts;
7397 case IFCOUNTER_IERRORS:
7398 count = ha->hw_stats.common.rx_crc_errors +
7399 ha->hw_stats.common.rx_align_errors +
7400 ha->hw_stats.common.rx_oversize_packets +
7401 ha->hw_stats.common.rx_undersize_packets;
7404 case IFCOUNTER_OPACKETS:
7405 count = ha->hw_stats.common.tx_ucast_pkts +
7406 ha->hw_stats.common.tx_mcast_pkts +
7407 ha->hw_stats.common.tx_bcast_pkts;
7410 case IFCOUNTER_OERRORS:
7411 count = ha->hw_stats.common.tx_err_drop_pkts;
7414 case IFCOUNTER_COLLISIONS:
7417 case IFCOUNTER_IBYTES:
7418 count = ha->hw_stats.common.rx_ucast_bytes +
7419 ha->hw_stats.common.rx_mcast_bytes +
7420 ha->hw_stats.common.rx_bcast_bytes;
7423 case IFCOUNTER_OBYTES:
7424 count = ha->hw_stats.common.tx_ucast_bytes +
7425 ha->hw_stats.common.tx_mcast_bytes +
7426 ha->hw_stats.common.tx_bcast_bytes;
7429 case IFCOUNTER_IMCASTS:
7430 count = ha->hw_stats.common.rx_mcast_bytes;
7433 case IFCOUNTER_OMCASTS:
7434 count = ha->hw_stats.common.tx_mcast_bytes;
7437 case IFCOUNTER_IQDROPS:
7438 case IFCOUNTER_OQDROPS:
7439 case IFCOUNTER_NOPROTO:
7442 return (if_get_counter_default(ifp, cnt));
7450 qlnx_timer(void *arg)
7454 ha = (qlnx_host_t *)arg;
7456 if (ha->error_recovery) {
7457 ha->error_recovery = 0;
7458 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
7462 ecore_get_vport_stats(&ha->cdev, &ha->hw_stats);
7464 if (ha->storm_stats_gather)
7465 qlnx_sample_storm_stats(ha);
7467 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7473 qlnx_load(qlnx_host_t *ha)
7477 struct ecore_dev *cdev;
7483 QL_DPRINT2(ha, "enter\n");
7485 rc = qlnx_alloc_mem_arrays(ha);
7487 goto qlnx_load_exit0;
7491 rc = qlnx_alloc_mem_load(ha);
7493 goto qlnx_load_exit1;
7495 QL_DPRINT2(ha, "Allocated %d RSS queues on %d TC/s\n",
7496 ha->num_rss, ha->num_tc);
7498 for (i = 0; i < ha->num_rss; i++) {
7500 if ((rc = bus_setup_intr(dev, ha->irq_vec[i].irq,
7501 (INTR_TYPE_NET | INTR_MPSAFE),
7502 NULL, qlnx_fp_isr, &ha->irq_vec[i],
7503 &ha->irq_vec[i].handle))) {
7505 QL_DPRINT1(ha, "could not setup interrupt\n");
7506 goto qlnx_load_exit2;
7509 QL_DPRINT2(ha, "rss_id = %d irq_rid %d \
7510 irq %p handle %p\n", i,
7511 ha->irq_vec[i].irq_rid,
7512 ha->irq_vec[i].irq, ha->irq_vec[i].handle);
7514 bus_bind_intr(dev, ha->irq_vec[i].irq, (i % mp_ncpus));
7517 rc = qlnx_start_queues(ha);
7519 goto qlnx_load_exit2;
7521 QL_DPRINT2(ha, "Start VPORT, RXQ and TXQ succeeded\n");
7523 /* Add primary mac and set Rx filters */
7524 rc = qlnx_set_rx_mode(ha);
7526 goto qlnx_load_exit2;
7528 /* Ask for link-up using current configuration */
7529 qlnx_set_link(ha, true);
7531 if (qlnx_vf_device(ha) == 0)
7532 qlnx_link_update(&ha->cdev.hwfns[0]);
7534 ha->state = QLNX_STATE_OPEN;
7536 bzero(&ha->hw_stats, sizeof(struct ecore_eth_stats));
7538 if (ha->flags.callout_init)
7539 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7541 goto qlnx_load_exit0;
7544 qlnx_free_mem_load(ha);
7550 QL_DPRINT2(ha, "exit [%d]\n", rc);
7555 qlnx_drain_soft_lro(qlnx_host_t *ha)
7557 #ifdef QLNX_SOFT_LRO
7565 if (ifp->if_capenable & IFCAP_LRO) {
7567 for (i = 0; i < ha->num_rss; i++) {
7569 struct qlnx_fastpath *fp = &ha->fp_array[i];
7570 struct lro_ctrl *lro;
7572 lro = &fp->rxq->lro;
7574 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
7576 tcp_lro_flush_all(lro);
7579 struct lro_entry *queued;
7581 while ((!SLIST_EMPTY(&lro->lro_active))){
7582 queued = SLIST_FIRST(&lro->lro_active);
7583 SLIST_REMOVE_HEAD(&lro->lro_active, next);
7584 tcp_lro_flush(lro, queued);
7587 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
7592 #endif /* #ifdef QLNX_SOFT_LRO */
7598 qlnx_unload(qlnx_host_t *ha)
7600 struct ecore_dev *cdev;
7607 QL_DPRINT2(ha, "enter\n");
7608 QL_DPRINT1(ha, " QLNX STATE = %d\n",ha->state);
7610 if (ha->state == QLNX_STATE_OPEN) {
7612 qlnx_set_link(ha, false);
7613 qlnx_clean_filters(ha);
7614 qlnx_stop_queues(ha);
7615 ecore_hw_stop_fastpath(cdev);
7617 for (i = 0; i < ha->num_rss; i++) {
7618 if (ha->irq_vec[i].handle) {
7619 (void)bus_teardown_intr(dev,
7621 ha->irq_vec[i].handle);
7622 ha->irq_vec[i].handle = NULL;
7626 qlnx_drain_fp_taskqueues(ha);
7627 qlnx_drain_soft_lro(ha);
7628 qlnx_free_mem_load(ha);
7631 if (ha->flags.callout_init)
7632 callout_drain(&ha->qlnx_callout);
7634 qlnx_mdelay(__func__, 1000);
7636 ha->state = QLNX_STATE_CLOSED;
7638 QL_DPRINT2(ha, "exit\n");
7643 qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7646 struct ecore_hwfn *p_hwfn;
7647 struct ecore_ptt *p_ptt;
7649 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7651 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7652 p_ptt = ecore_ptt_acquire(p_hwfn);
7655 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7659 rval = ecore_dbg_grc_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7661 if (rval == DBG_STATUS_OK)
7664 QL_DPRINT1(ha, "ecore_dbg_grc_get_dump_buf_size failed"
7668 ecore_ptt_release(p_hwfn, p_ptt);
7674 qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7677 struct ecore_hwfn *p_hwfn;
7678 struct ecore_ptt *p_ptt;
7680 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7682 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7683 p_ptt = ecore_ptt_acquire(p_hwfn);
7686 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7690 rval = ecore_dbg_idle_chk_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7692 if (rval == DBG_STATUS_OK)
7695 QL_DPRINT1(ha, "ecore_dbg_idle_chk_get_dump_buf_size failed"
7699 ecore_ptt_release(p_hwfn, p_ptt);
7706 qlnx_sample_storm_stats(qlnx_host_t *ha)
7709 struct ecore_dev *cdev;
7710 qlnx_storm_stats_t *s_stats;
7712 struct ecore_ptt *p_ptt;
7713 struct ecore_hwfn *hwfn;
7715 if (ha->storm_stats_index >= QLNX_STORM_STATS_SAMPLES_PER_HWFN) {
7716 ha->storm_stats_gather = 0;
7722 for_each_hwfn(cdev, i) {
7724 hwfn = &cdev->hwfns[i];
7726 p_ptt = ecore_ptt_acquire(hwfn);
7730 index = ha->storm_stats_index +
7731 (i * QLNX_STORM_STATS_SAMPLES_PER_HWFN);
7733 s_stats = &ha->storm_stats[index];
7736 reg = XSEM_REG_FAST_MEMORY +
7737 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7738 s_stats->xstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7740 reg = XSEM_REG_FAST_MEMORY +
7741 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7742 s_stats->xstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7744 reg = XSEM_REG_FAST_MEMORY +
7745 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7746 s_stats->xstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7748 reg = XSEM_REG_FAST_MEMORY +
7749 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7750 s_stats->xstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7753 reg = YSEM_REG_FAST_MEMORY +
7754 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7755 s_stats->ystorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7757 reg = YSEM_REG_FAST_MEMORY +
7758 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7759 s_stats->ystorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7761 reg = YSEM_REG_FAST_MEMORY +
7762 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7763 s_stats->ystorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7765 reg = YSEM_REG_FAST_MEMORY +
7766 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7767 s_stats->ystorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7770 reg = PSEM_REG_FAST_MEMORY +
7771 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7772 s_stats->pstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7774 reg = PSEM_REG_FAST_MEMORY +
7775 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7776 s_stats->pstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7778 reg = PSEM_REG_FAST_MEMORY +
7779 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7780 s_stats->pstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7782 reg = PSEM_REG_FAST_MEMORY +
7783 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7784 s_stats->pstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7787 reg = TSEM_REG_FAST_MEMORY +
7788 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7789 s_stats->tstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7791 reg = TSEM_REG_FAST_MEMORY +
7792 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7793 s_stats->tstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7795 reg = TSEM_REG_FAST_MEMORY +
7796 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7797 s_stats->tstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7799 reg = TSEM_REG_FAST_MEMORY +
7800 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7801 s_stats->tstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7804 reg = MSEM_REG_FAST_MEMORY +
7805 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7806 s_stats->mstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7808 reg = MSEM_REG_FAST_MEMORY +
7809 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7810 s_stats->mstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7812 reg = MSEM_REG_FAST_MEMORY +
7813 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7814 s_stats->mstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7816 reg = MSEM_REG_FAST_MEMORY +
7817 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7818 s_stats->mstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7821 reg = USEM_REG_FAST_MEMORY +
7822 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7823 s_stats->ustorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7825 reg = USEM_REG_FAST_MEMORY +
7826 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7827 s_stats->ustorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7829 reg = USEM_REG_FAST_MEMORY +
7830 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7831 s_stats->ustorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7833 reg = USEM_REG_FAST_MEMORY +
7834 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7835 s_stats->ustorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7837 ecore_ptt_release(hwfn, p_ptt);
7840 ha->storm_stats_index++;
7846 * Name: qlnx_dump_buf8
7847 * Function: dumps a buffer as bytes
7850 qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf, uint32_t len)
7859 device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
7862 device_printf(dev,"0x%08x:"
7863 " %02x %02x %02x %02x %02x %02x %02x %02x"
7864 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7865 buf[0], buf[1], buf[2], buf[3],
7866 buf[4], buf[5], buf[6], buf[7],
7867 buf[8], buf[9], buf[10], buf[11],
7868 buf[12], buf[13], buf[14], buf[15]);
7875 device_printf(dev,"0x%08x: %02x\n", i, buf[0]);
7878 device_printf(dev,"0x%08x: %02x %02x\n", i, buf[0], buf[1]);
7881 device_printf(dev,"0x%08x: %02x %02x %02x\n",
7882 i, buf[0], buf[1], buf[2]);
7885 device_printf(dev,"0x%08x: %02x %02x %02x %02x\n", i,
7886 buf[0], buf[1], buf[2], buf[3]);
7889 device_printf(dev,"0x%08x:"
7890 " %02x %02x %02x %02x %02x\n", i,
7891 buf[0], buf[1], buf[2], buf[3], buf[4]);
7894 device_printf(dev,"0x%08x:"
7895 " %02x %02x %02x %02x %02x %02x\n", i,
7896 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
7899 device_printf(dev,"0x%08x:"
7900 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7901 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
7904 device_printf(dev,"0x%08x:"
7905 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7906 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7910 device_printf(dev,"0x%08x:"
7911 " %02x %02x %02x %02x %02x %02x %02x %02x"
7913 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7917 device_printf(dev,"0x%08x:"
7918 " %02x %02x %02x %02x %02x %02x %02x %02x"
7920 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7921 buf[7], buf[8], buf[9]);
7924 device_printf(dev,"0x%08x:"
7925 " %02x %02x %02x %02x %02x %02x %02x %02x"
7926 " %02x %02x %02x\n", i,
7927 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7928 buf[7], buf[8], buf[9], buf[10]);
7931 device_printf(dev,"0x%08x:"
7932 " %02x %02x %02x %02x %02x %02x %02x %02x"
7933 " %02x %02x %02x %02x\n", i,
7934 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7935 buf[7], buf[8], buf[9], buf[10], buf[11]);
7938 device_printf(dev,"0x%08x:"
7939 " %02x %02x %02x %02x %02x %02x %02x %02x"
7940 " %02x %02x %02x %02x %02x\n", i,
7941 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7942 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12]);
7945 device_printf(dev,"0x%08x:"
7946 " %02x %02x %02x %02x %02x %02x %02x %02x"
7947 " %02x %02x %02x %02x %02x %02x\n", i,
7948 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7949 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7953 device_printf(dev,"0x%08x:"
7954 " %02x %02x %02x %02x %02x %02x %02x %02x"
7955 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7956 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7957 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7964 device_printf(dev, "%s: %s dump end\n", __func__, msg);
7969 #ifdef CONFIG_ECORE_SRIOV
7972 __qlnx_osal_iov_vf_cleanup(struct ecore_hwfn *p_hwfn, uint8_t rel_vf_id)
7974 struct ecore_public_vf_info *vf_info;
7976 vf_info = ecore_iov_get_public_vf_info(p_hwfn, rel_vf_id, false);
7981 /* Clear the VF mac */
7982 memset(vf_info->forced_mac, 0, ETH_ALEN);
7984 vf_info->forced_vlan = 0;
7990 qlnx_osal_iov_vf_cleanup(void *p_hwfn, uint8_t relative_vf_id)
7992 __qlnx_osal_iov_vf_cleanup(p_hwfn, relative_vf_id);
7997 __qlnx_iov_chk_ucast(struct ecore_hwfn *p_hwfn, int vfid,
7998 struct ecore_filter_ucast *params)
8000 struct ecore_public_vf_info *vf;
8002 if (!ecore_iov_vf_has_vport_instance(p_hwfn, vfid)) {
8003 QL_DPRINT1(((qlnx_host_t *)p_hwfn->p_dev),
8004 "VF[%d] vport not initialized\n", vfid);
8008 vf = ecore_iov_get_public_vf_info(p_hwfn, vfid, true);
8012 /* No real decision to make; Store the configured MAC */
8013 if (params->type == ECORE_FILTER_MAC ||
8014 params->type == ECORE_FILTER_MAC_VLAN)
8015 memcpy(params->mac, vf->forced_mac, ETH_ALEN);
8021 qlnx_iov_chk_ucast(void *p_hwfn, int vfid, void *params)
8023 return (__qlnx_iov_chk_ucast(p_hwfn, vfid, params));
8027 __qlnx_iov_update_vport(struct ecore_hwfn *hwfn, uint8_t vfid,
8028 struct ecore_sp_vport_update_params *params, uint16_t * tlvs)
8031 struct ecore_filter_accept_flags *flags;
8033 if (!ecore_iov_vf_has_vport_instance(hwfn, vfid)) {
8034 QL_DPRINT1(((qlnx_host_t *)hwfn->p_dev),
8035 "VF[%d] vport not initialized\n", vfid);
8039 /* Untrusted VFs can't even be trusted to know that fact.
8040 * Simply indicate everything is configured fine, and trace
8041 * configuration 'behind their back'.
8043 mask = ECORE_ACCEPT_UCAST_UNMATCHED | ECORE_ACCEPT_MCAST_UNMATCHED;
8044 flags = ¶ms->accept_flags;
8045 if (!(*tlvs & BIT(ECORE_IOV_VP_UPDATE_ACCEPT_PARAM)))
8052 qlnx_iov_update_vport(void *hwfn, uint8_t vfid, void *params, uint16_t *tlvs)
8054 return(__qlnx_iov_update_vport(hwfn, vfid, params, tlvs));
8058 qlnx_find_hwfn_index(struct ecore_hwfn *p_hwfn)
8061 struct ecore_dev *cdev;
8063 cdev = p_hwfn->p_dev;
8065 for (i = 0; i < cdev->num_hwfns; i++) {
8066 if (&cdev->hwfns[i] == p_hwfn)
8070 if (i >= cdev->num_hwfns)
8077 __qlnx_pf_vf_msg(struct ecore_hwfn *p_hwfn, uint16_t rel_vf_id)
8079 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
8082 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p rel_vf_id = %d\n",
8083 ha, p_hwfn->p_dev, p_hwfn, rel_vf_id);
8085 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8088 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8090 atomic_testandset_32(&ha->sriov_task[i].flags,
8091 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG);
8093 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
8094 &ha->sriov_task[i].pf_task);
8098 return (ECORE_SUCCESS);
8103 qlnx_pf_vf_msg(void *p_hwfn, uint16_t relative_vf_id)
8105 return (__qlnx_pf_vf_msg(p_hwfn, relative_vf_id));
8109 __qlnx_vf_flr_update(struct ecore_hwfn *p_hwfn)
8111 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
8114 if (!ha->sriov_initialized)
8117 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
8118 ha, p_hwfn->p_dev, p_hwfn);
8120 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8124 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8126 atomic_testandset_32(&ha->sriov_task[i].flags,
8127 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE);
8129 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
8130 &ha->sriov_task[i].pf_task);
8138 qlnx_vf_flr_update(void *p_hwfn)
8140 __qlnx_vf_flr_update(p_hwfn);
8148 qlnx_vf_bulleting_update(struct ecore_hwfn *p_hwfn)
8150 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
8153 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
8154 ha, p_hwfn->p_dev, p_hwfn);
8156 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8159 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p i = %d\n",
8160 ha, p_hwfn->p_dev, p_hwfn, i);
8162 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8164 atomic_testandset_32(&ha->sriov_task[i].flags,
8165 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE);
8167 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
8168 &ha->sriov_task[i].pf_task);
8173 qlnx_initialize_sriov(qlnx_host_t *ha)
8176 nvlist_t *pf_schema, *vf_schema;
8181 pf_schema = pci_iov_schema_alloc_node();
8182 vf_schema = pci_iov_schema_alloc_node();
8184 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
8185 pci_iov_schema_add_bool(vf_schema, "allow-set-mac",
8186 IOV_SCHEMA_HASDEFAULT, FALSE);
8187 pci_iov_schema_add_bool(vf_schema, "allow-promisc",
8188 IOV_SCHEMA_HASDEFAULT, FALSE);
8189 pci_iov_schema_add_uint16(vf_schema, "num-queues",
8190 IOV_SCHEMA_HASDEFAULT, 1);
8192 iov_error = pci_iov_attach(dev, pf_schema, vf_schema);
8194 if (iov_error != 0) {
8195 ha->sriov_initialized = 0;
8197 device_printf(dev, "SRIOV initialized\n");
8198 ha->sriov_initialized = 1;
8205 qlnx_sriov_disable(qlnx_host_t *ha)
8207 struct ecore_dev *cdev;
8212 ecore_iov_set_vfs_to_disable(cdev, true);
8215 for_each_hwfn(cdev, i) {
8217 struct ecore_hwfn *hwfn = &cdev->hwfns[i];
8218 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
8221 QL_DPRINT1(ha, "Failed to acquire ptt\n");
8224 /* Clean WFQ db and configure equal weight for all vports */
8225 ecore_clean_wfq_db(hwfn, ptt);
8227 ecore_for_each_vf(hwfn, j) {
8230 if (!ecore_iov_is_valid_vfid(hwfn, j, true, false))
8233 if (ecore_iov_is_vf_started(hwfn, j)) {
8234 /* Wait until VF is disabled before releasing */
8236 for (k = 0; k < 100; k++) {
8237 if (!ecore_iov_is_vf_stopped(hwfn, j)) {
8238 qlnx_mdelay(__func__, 10);
8245 ecore_iov_release_hw_for_vf(&cdev->hwfns[i],
8249 "Timeout waiting for VF's FLR to end\n");
8252 ecore_ptt_release(hwfn, ptt);
8255 ecore_iov_set_vfs_to_disable(cdev, false);
8262 qlnx_sriov_enable_qid_config(struct ecore_hwfn *hwfn, u16 vfid,
8263 struct ecore_iov_vf_init_params *params)
8267 /* Since we have an equal resource distribution per-VF, and we assume
8268 * PF has acquired the ECORE_PF_L2_QUE first queues, we start setting
8269 * sequentially from there.
8271 base = FEAT_NUM(hwfn, ECORE_PF_L2_QUE) + vfid * params->num_queues;
8273 params->rel_vf_id = vfid;
8275 for (i = 0; i < params->num_queues; i++) {
8276 params->req_rx_queue[i] = base + i;
8277 params->req_tx_queue[i] = base + i;
8280 /* PF uses indices 0 for itself; Set vport/RSS afterwards */
8281 params->vport_id = vfid + 1;
8282 params->rss_eng_id = vfid + 1;
8288 qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *nvlist_params)
8291 struct ecore_dev *cdev;
8292 struct ecore_iov_vf_init_params params;
8296 if ((ha = device_get_softc(dev)) == NULL) {
8297 device_printf(dev, "%s: cannot get softc\n", __func__);
8301 if (qlnx_create_pf_taskqueues(ha) != 0)
8302 goto qlnx_iov_init_err0;
8306 max_vfs = RESC_NUM(&cdev->hwfns[0], ECORE_VPORT);
8308 QL_DPRINT2(ha," dev = %p enter num_vfs = %d max_vfs = %d\n",
8309 dev, num_vfs, max_vfs);
8311 if (num_vfs >= max_vfs) {
8312 QL_DPRINT1(ha, "Can start at most %d VFs\n",
8313 (RESC_NUM(&cdev->hwfns[0], ECORE_VPORT) - 1));
8314 goto qlnx_iov_init_err0;
8317 ha->vf_attr = malloc(((sizeof (qlnx_vf_attr_t) * num_vfs)), M_QLNXBUF,
8320 if (ha->vf_attr == NULL)
8321 goto qlnx_iov_init_err0;
8324 memset(¶ms, 0, sizeof(params));
8326 /* Initialize HW for VF access */
8327 for_each_hwfn(cdev, j) {
8328 struct ecore_hwfn *hwfn = &cdev->hwfns[j];
8329 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
8331 /* Make sure not to use more than 16 queues per VF */
8332 params.num_queues = min_t(int,
8333 (FEAT_NUM(hwfn, ECORE_VF_L2_QUE) / num_vfs),
8337 QL_DPRINT1(ha, "Failed to acquire ptt\n");
8338 goto qlnx_iov_init_err1;
8341 for (i = 0; i < num_vfs; i++) {
8343 if (!ecore_iov_is_valid_vfid(hwfn, i, false, true))
8346 qlnx_sriov_enable_qid_config(hwfn, i, ¶ms);
8348 ret = ecore_iov_init_hw_for_vf(hwfn, ptt, ¶ms);
8351 QL_DPRINT1(ha, "Failed to enable VF[%d]\n", i);
8352 ecore_ptt_release(hwfn, ptt);
8353 goto qlnx_iov_init_err1;
8357 ecore_ptt_release(hwfn, ptt);
8360 ha->num_vfs = num_vfs;
8361 qlnx_inform_vf_link_state(&cdev->hwfns[0], ha);
8363 QL_DPRINT2(ha," dev = %p exit num_vfs = %d\n", dev, num_vfs);
8368 qlnx_sriov_disable(ha);
8371 qlnx_destroy_pf_taskqueues(ha);
8378 qlnx_iov_uninit(device_t dev)
8382 if ((ha = device_get_softc(dev)) == NULL) {
8383 device_printf(dev, "%s: cannot get softc\n", __func__);
8387 QL_DPRINT2(ha," dev = %p enter\n", dev);
8389 qlnx_sriov_disable(ha);
8390 qlnx_destroy_pf_taskqueues(ha);
8392 free(ha->vf_attr, M_QLNXBUF);
8397 QL_DPRINT2(ha," dev = %p exit\n", dev);
8402 qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
8405 qlnx_vf_attr_t *vf_attr;
8406 unsigned const char *mac;
8408 struct ecore_hwfn *p_hwfn;
8410 if ((ha = device_get_softc(dev)) == NULL) {
8411 device_printf(dev, "%s: cannot get softc\n", __func__);
8415 QL_DPRINT2(ha," dev = %p enter vfnum = %d\n", dev, vfnum);
8417 if (vfnum > (ha->num_vfs - 1)) {
8418 QL_DPRINT1(ha, " VF[%d] is greater than max allowed [%d]\n",
8419 vfnum, (ha->num_vfs - 1));
8422 vf_attr = &ha->vf_attr[vfnum];
8424 if (nvlist_exists_binary(params, "mac-addr")) {
8425 mac = nvlist_get_binary(params, "mac-addr", &size);
8426 bcopy(mac, vf_attr->mac_addr, ETHER_ADDR_LEN);
8428 "%s: mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n",
8429 __func__, vf_attr->mac_addr[0],
8430 vf_attr->mac_addr[1], vf_attr->mac_addr[2],
8431 vf_attr->mac_addr[3], vf_attr->mac_addr[4],
8432 vf_attr->mac_addr[5]);
8433 p_hwfn = &ha->cdev.hwfns[0];
8434 ecore_iov_bulletin_set_mac(p_hwfn, vf_attr->mac_addr,
8438 QL_DPRINT2(ha," dev = %p exit vfnum = %d\n", dev, vfnum);
8443 qlnx_handle_vf_msg(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8445 uint64_t events[ECORE_VF_ARRAY_LENGTH];
8446 struct ecore_ptt *ptt;
8449 ptt = ecore_ptt_acquire(p_hwfn);
8451 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8452 __qlnx_pf_vf_msg(p_hwfn, 0);
8456 ecore_iov_pf_get_pending_events(p_hwfn, events);
8458 QL_DPRINT2(ha, "Event mask of VF events:"
8459 "0x%" PRIu64 "0x%" PRIu64 " 0x%" PRIu64 "\n",
8460 events[0], events[1], events[2]);
8462 ecore_for_each_vf(p_hwfn, i) {
8464 /* Skip VFs with no pending messages */
8465 if (!(events[i / 64] & (1ULL << (i % 64))))
8469 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
8470 i, p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
8472 /* Copy VF's message to PF's request buffer for that VF */
8473 if (ecore_iov_copy_vf_msg(p_hwfn, ptt, i))
8476 ecore_iov_process_mbx_req(p_hwfn, ptt, i);
8479 ecore_ptt_release(p_hwfn, ptt);
8485 qlnx_handle_vf_flr_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8487 struct ecore_ptt *ptt;
8490 ptt = ecore_ptt_acquire(p_hwfn);
8493 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8494 __qlnx_vf_flr_update(p_hwfn);
8498 ret = ecore_iov_vf_flr_cleanup(p_hwfn, ptt);
8501 QL_DPRINT1(ha, "ecore_iov_vf_flr_cleanup failed; re-scheduling\n");
8504 ecore_ptt_release(p_hwfn, ptt);
8510 qlnx_handle_bulletin_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8512 struct ecore_ptt *ptt;
8515 ptt = ecore_ptt_acquire(p_hwfn);
8518 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8519 qlnx_vf_bulleting_update(p_hwfn);
8523 ecore_for_each_vf(p_hwfn, i) {
8524 QL_DPRINT1(ha, "ecore_iov_post_vf_bulletin[%p, %d]\n",
8526 ecore_iov_post_vf_bulletin(p_hwfn, i, ptt);
8529 ecore_ptt_release(p_hwfn, ptt);
8535 qlnx_pf_taskqueue(void *context, int pending)
8537 struct ecore_hwfn *p_hwfn;
8546 ha = (qlnx_host_t *)(p_hwfn->p_dev);
8548 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8551 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8552 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG))
8553 qlnx_handle_vf_msg(ha, p_hwfn);
8555 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8556 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE))
8557 qlnx_handle_vf_flr_update(ha, p_hwfn);
8559 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8560 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE))
8561 qlnx_handle_bulletin_update(ha, p_hwfn);
8567 qlnx_create_pf_taskqueues(qlnx_host_t *ha)
8570 uint8_t tq_name[32];
8572 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8574 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
8576 bzero(tq_name, sizeof (tq_name));
8577 snprintf(tq_name, sizeof (tq_name), "ql_pf_tq_%d", i);
8579 TASK_INIT(&ha->sriov_task[i].pf_task, 0, qlnx_pf_taskqueue, p_hwfn);
8581 ha->sriov_task[i].pf_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
8582 taskqueue_thread_enqueue,
8583 &ha->sriov_task[i].pf_taskqueue);
8585 if (ha->sriov_task[i].pf_taskqueue == NULL)
8588 taskqueue_start_threads(&ha->sriov_task[i].pf_taskqueue, 1,
8589 PI_NET, "%s", tq_name);
8591 QL_DPRINT1(ha, "%p\n", ha->sriov_task[i].pf_taskqueue);
8598 qlnx_destroy_pf_taskqueues(qlnx_host_t *ha)
8602 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8603 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8604 taskqueue_drain(ha->sriov_task[i].pf_taskqueue,
8605 &ha->sriov_task[i].pf_task);
8606 taskqueue_free(ha->sriov_task[i].pf_taskqueue);
8607 ha->sriov_task[i].pf_taskqueue = NULL;
8614 qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha)
8616 struct ecore_mcp_link_capabilities caps;
8617 struct ecore_mcp_link_params params;
8618 struct ecore_mcp_link_state link;
8621 if (!p_hwfn->pf_iov_info)
8624 memset(¶ms, 0, sizeof(struct ecore_mcp_link_params));
8625 memset(&link, 0, sizeof(struct ecore_mcp_link_state));
8626 memset(&caps, 0, sizeof(struct ecore_mcp_link_capabilities));
8628 memcpy(&caps, ecore_mcp_get_link_capabilities(p_hwfn), sizeof(caps));
8629 memcpy(&link, ecore_mcp_get_link_state(p_hwfn), sizeof(link));
8630 memcpy(¶ms, ecore_mcp_get_link_params(p_hwfn), sizeof(params));
8632 QL_DPRINT2(ha, "called\n");
8634 /* Update bulletin of all future possible VFs with link configuration */
8635 for (i = 0; i < p_hwfn->p_dev->p_iov_info->total_vfs; i++) {
8637 /* Modify link according to the VF's configured link state */
8639 link.link_up = false;
8642 link.link_up = true;
8643 /* Set speed according to maximum supported by HW.
8644 * that is 40G for regular devices and 100G for CMT
8647 link.speed = (p_hwfn->p_dev->num_hwfns > 1) ?
8648 100000 : link.speed;
8650 QL_DPRINT2(ha, "link [%d] = %d\n", i, link.link_up);
8651 ecore_iov_set_link(p_hwfn, i, ¶ms, &link, &caps);
8654 qlnx_vf_bulleting_update(p_hwfn);
8658 #endif /* #ifndef QLNX_VF */
8659 #endif /* #ifdef CONFIG_ECORE_SRIOV */