2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 /****************************************************************************
34 * Description: Global definitions
38 ****************************************************************************/
40 * Spad Layout NVM CFG MCP public
41 *==========================================================================================================
42 * MCP_REG_SCRATCH REG_RD(MISC_REG_GEN_PURP_CR0) REG_RD(MISC_REG_SHARED_MEM_ADDR)
43 * +------------------+ +-------------------------+ +-------------------+
44 * | Num Sections(4B)|Currently 4 | Num Sections(4B) | | Num Sections(4B)|Currently 6
45 * +------------------+ +-------------------------+ +-------------------+
46 * | Offsize(Trace) |4B -+ +-- | Offset(NVM_CFG1) | | Offsize(drv_mb) |
47 * +-| Offsize(NVM_CFG) |4B | | | (Size is fixed) | | Offsize(mfw_mb) |
48 *+-|-| Offsize(Public) |4B | +-> +-------------------------+ | Offsize(global) |
49 *| | | Offsize(Private) |4B | | | | Offsize(path) |
50 *| | +------------------+ <--+ | nvm_cfg1_glob | | Offsize(port) |
51 *| | | | +-------------------------+ | Offsize(func) |
52 *| | | Trace | | nvm_cfg1_path 0 | +-------------------+
53 *| +>+------------------+ | nvm_cfg1_path 1 | | drv_mb PF0/2/4..|8 Funcs of engine0
54 *| | | +-------------------------+ | drv_mb PF1/3/5..|8 Funcs of engine1
55 *| | NVM_CFG | | nvm_cfg1_port 0 | +-------------------+
56 *+-> +------------------+ | .... | | mfw_mb PF0/2/4..|8 Funcs of engine0
57 * | | | nvm_cfg1_port 3 | | mfw_mb PF1/3/5..|8 Funcs of engine1
58 * | Public Data | +-------------------------+ +-------------------+
59 * +------------------+ 8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..| | |
60 * | | 8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..| | public_global |
61 * | Private Data | +-------------------------+ +-------------------+
62 * +------------------+ | public_path 0 |
63 * | Code | | public_path 1 |
64 * | Static Area | +-------------------+
65 * +--- ---+ | public_port 0 |
67 * | PIM Area | | public_port 3 |
68 * +------------------+ +-------------------+
69 * | public_func 0/2/4.|8 Funcs of engine0
70 * | public_func 1/3/5.|8 Funcs of engine1
71 * +-------------------+
76 #ifndef MDUMP_PARSE_TOOL
83 #include "mcp_public.h"
88 #include "mcp_private.h"
91 extern struct spad_layout g_spad;
93 /* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */
94 #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
96 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
97 #endif /* MDUMP_PARSE_TOOL */
99 #define TO_OFFSIZE(_offset, _size) \
100 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_OFFSET) | \
101 (((u32)(_size) >> 2) << OFFSIZE_SIZE_OFFSET))
105 SPAD_SECTION_NVM_CFG,
107 SPAD_SECTION_PRIVATE,
111 #ifndef MDUMP_PARSE_TOOL
113 struct nvm_cfg nvm_cfg;
114 struct mcp_public_data public_data;
115 #ifdef MFW /* Drivers will not be compiled with this flag. */
116 /* Linux should remove this appearance at all. */
117 struct mcp_private_data private_data;
121 #endif /* MDUMP_PARSE_TOOL */
123 #define MCP_TRACE_SIZE 2048 /* 2kb */
124 #define STRUCT_OFFSET(f) (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f))
126 /* This section is located at a fixed location in the beginning of the scratchpad,
127 * to ensure that the MCP trace is not run over during MFW upgrade.
128 * All the rest of data has a floating location which differs from version to version,
129 * and is pointed by the mcp_meta_data below.
130 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it
131 * from nvram in order to clear this portion.
134 u32 num_sections; /* 0xe20000 */
135 offsize_t sections[SPAD_SECTION_MAX]; /* 0xe20004 */
136 #define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_])))
138 struct mcp_trace trace; /* 0xe20014 */
139 #define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace)))
140 u8 trace_buffer[MCP_TRACE_SIZE]; /* 0xe20030 */
141 #define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer)))
142 /* running_mfw has the same definition as in nvm_map.h.
143 * This bit indicate both the running dir, and the running bundle.
144 * It is set once when the LIM is loaded.
146 u32 running_mfw; /* 0xe20830 */
147 #define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw)))
148 u32 build_time; /* 0xe20834 */
149 #define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time)))
150 u32 reset_type; /* 0xe20838 */
151 #define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type)))
152 u32 mfw_secure_mode; /* 0xe2083c */
153 #define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode)))
154 u16 pme_status_pf_bitmap; /* 0xe20840 */
155 #define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap)))
156 u16 pme_enable_pf_bitmap;
157 #define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap)))
158 u32 mim_nvm_addr; /* 0xe20844 */
159 u32 mim_start_addr; /* 0xe20848 */
160 u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */
161 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
162 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_OFFSET (0)
163 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
164 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_OFFSET (8)
165 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
166 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_OFFSET (16)
167 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
168 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_OFFSET (24)
169 #define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params)))
171 u32 flags; /* 0xe20850 */
172 #define M_GLOB_FLAGS *((u32*)(STRUCT_OFFSET(flags)))
173 #define FLAGS_VAUX_REQUIRED (1 << 0)
174 #define FLAGS_WAIT_AVS_READY (1 << 1)
175 #define FLAGS_FAILURE_ISSUED (1 << 2)
176 #define FLAGS_FAILURE_DETECTED (1 << 3)
177 #define FLAGS_VAUX (1 << 4)
178 #define FLAGS_PERST_ASSERT_OCCURED (1 << 5)
179 #define FLAGS_HOT_RESET_STEP2 (1 << 6)
180 #define FLAGS_MSIX_SYNC_ALLOWED (1 << 7)
181 #define FLAGS_PROGRAM_PCI_COMPLETED (1 << 8)
182 #define FLAGS_SMBUS_AUX_MODE (1 << 9)
183 #define FLAGS_PEND_SMBUS_VMAIN_TO_AUX (1 << 10)
184 #define FLAGS_NVM_CFG_EFUSE_FAILURE (1 << 11)
185 #define FLAGS_POWER_TRANSITION (1 << 12)
186 #define FLAGS_OS_DRV_LOADED (1 << 29)
187 #define FLAGS_OVER_TEMP_OCCUR (1 << 30)
188 #define FLAGS_FAN_FAIL_OCCUR (1 << 31)
189 u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */
193 #ifndef MDUMP_PARSE_TOOL
194 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
195 #define NVM_GLOB(x) NVM_CFG1(glob).x
196 #define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o)
197 #endif /* MDUMP_PARSE_TOOL */
199 #endif /* SPAD_LAYOUT_H */