2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011-2013 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
38 #define Q8_MAX_NUM_MULTICAST_ADDRS 128
39 #define Q8_MAC_ADDR_LEN 6
46 * Command Response Interface - Commands
48 typedef struct qla_cdrp {
59 #define Q8_CMD_RD_MAX_RDS_PER_CNTXT 0x80000002
60 #define Q8_CMD_RD_MAX_SDS_PER_CNTXT 0x80000003
61 #define Q8_CMD_RD_MAX_RULES_PER_CNTXT 0x80000004
62 #define Q8_CMD_RD_MAX_RX_CNTXT 0x80000005
63 #define Q8_CMD_RD_MAX_TX_CNTXT 0x80000006
64 #define Q8_CMD_CREATE_RX_CNTXT 0x80000007
65 #define Q8_CMD_DESTROY_RX_CNTXT 0x80000008
66 #define Q8_CMD_CREATE_TX_CNTXT 0x80000009
67 #define Q8_CMD_DESTROY_TX_CNTXT 0x8000000A
68 #define Q8_CMD_SETUP_STATS 0x8000000E
69 #define Q8_CMD_GET_STATS 0x8000000F
70 #define Q8_CMD_DELETE_STATS 0x80000010
71 #define Q8_CMD_GEN_INT 0x80000011
72 #define Q8_CMD_SET_MTU 0x80000012
73 #define Q8_CMD_GET_FLOW_CNTRL 0x80000016
74 #define Q8_CMD_SET_FLOW_CNTRL 0x80000017
75 #define Q8_CMD_RD_MAX_MTU 0x80000018
76 #define Q8_CMD_RD_MAX_LRO 0x80000019
79 * Command Response Interface - Response
81 #define Q8_RSP_SUCCESS 0x00000000
82 #define Q8_RSP_NO_HOST_MEM 0x00000001
83 #define Q8_RSP_NO_HOST_RSRC 0x00000002
84 #define Q8_RSP_NO_CARD_CRB 0x00000003
85 #define Q8_RSP_NO_CARD_MEM 0x00000004
86 #define Q8_RSP_NO_CARD_RSRC 0x00000005
87 #define Q8_RSP_INVALID_ARGS 0x00000006
88 #define Q8_RSP_INVALID_ACTION 0x00000007
89 #define Q8_RSP_INVALID_STATE 0x00000008
90 #define Q8_RSP_NOT_SUPPORTED 0x00000009
91 #define Q8_RSP_NOT_PERMITTED 0x0000000A
92 #define Q8_RSP_NOT_READY 0x0000000B
93 #define Q8_RSP_DOES_NOT_EXIST 0x0000000C
94 #define Q8_RSP_ALREADY_EXISTS 0x0000000D
95 #define Q8_RSP_BAD_SIGNATURE 0x0000000E
96 #define Q8_RSP_CMD_NOT_IMPLEMENTED 0x0000000F
97 #define Q8_RSP_CMD_INVALID 0x00000010
98 #define Q8_RSP_TIMEOUT 0x00000011
102 * Transmit Related Definitions
106 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
109 typedef struct _q80_tx_cntxt_req {
110 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */
111 uint64_t cmd_cons_dma_addr;
114 uint32_t caps[4]; /* capabilities - bit vector*/
115 #define CNTXT_CAP0_BASEFW 0x0001
116 #define CNTXT_CAP0_LEGACY_MN 0x0004
117 #define CNTXT_CAP0_LSO 0x0040
119 uint32_t intr_mode; /* Interrupt Mode */
120 #define CNTXT_INTR_MODE_UNIQUE 0x0000
121 #define CNTXT_INTR_MODE_SHARED 0x0001
126 uint64_t phys_addr; /* physical address of transmit ring
127 * in system memory */
128 uint32_t num_entries; /* number of entries in transmit ring */
130 } __packed q80_tx_cntxt_req_t; /* 188 bytes total */
134 * Transmit Context - Response from Firmware to Q8_CMD_CREATE_TX_CNTXT
137 typedef struct _q80_tx_cntxt_rsp {
138 uint32_t cntxt_state; /* starting state */
139 #define CNTXT_STATE_ALLOCATED_NOT_ACTIVE 0x0001
140 #define CNTXT_STATE_ACTIVE 0x0002
141 #define CNTXT_STATE_QUIESCED 0x0004
143 uint16_t cntxt_id; /* handle for context */
144 uint8_t phys_port_id; /* physical id of port */
145 uint8_t virt_port_id; /* virtual or logical id of port */
146 uint32_t producer_reg; /* producer register for transmit ring */
147 uint32_t intr_mask_reg; /* interrupt mask register */
149 } __packed q80_tx_cntxt_rsp_t; /* 144 bytes */
152 * Transmit Command Descriptor
153 * These commands are issued on the Transmit Ring associated with a Transmit
156 typedef struct _q80_tx_cmd {
157 uint8_t tcp_hdr_off; /* TCP Header Offset */
158 uint8_t ip_hdr_off; /* IP Header Offset */
159 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */
162 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01
163 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02
164 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10
165 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40
168 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7)
169 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7)
170 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7)
171 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7)
172 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7)
173 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7)
174 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7)
176 uint8_t n_bufs; /* # of data segs in data buffer */
177 uint8_t data_len_lo; /* data length lower 8 bits */
178 uint16_t data_len_hi; /* data length upper 16 bits */
180 uint64_t buf2_addr; /* buffer 2 address */
183 uint16_t mss; /* MSS for this packet */
184 uint8_t port_cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */
186 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
188 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */
191 uint64_t buf3_addr; /* buffer 3 address */
192 uint64_t buf1_addr; /* buffer 1 address */
194 uint16_t buf1_len; /* length of buffer 1 */
195 uint16_t buf2_len; /* length of buffer 2 */
196 uint16_t buf3_len; /* length of buffer 3 */
197 uint16_t buf4_len; /* length of buffer 4 */
199 uint64_t buf4_addr; /* buffer 4 address */
203 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/
205 } __packed q80_tx_cmd_t; /* 64 bytes */
207 #define Q8_TX_CMD_MAX_SEGMENTS 4
208 #define Q8_TX_CMD_TSO_ALIGN 2
209 #define Q8_TX_MAX_SEGMENTS 14
213 * Receive Related Definitions
216 * Receive Context - Q8_CMD_CREATE_RX_CNTXT Command Configuration Data
219 typedef struct _q80_rq_sds_ring {
220 uint64_t phys_addr; /* physical addr of status ring in system memory */
221 uint32_t size; /* number of entries in status ring */
224 } __packed q80_rq_sds_ring_t; /* 16 bytes */
226 typedef struct _q80_rq_rds_ring {
227 uint64_t phys_addr; /* physical addr of rcv ring in system memory */
228 uint64_t buf_size; /* packet buffer size */
229 uint32_t size; /* number of entries in ring */
231 } __packed q80_rq_rds_ring_t; /* 24 bytes */
233 typedef struct _q80_rq_rcv_cntxt {
234 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */
235 uint32_t caps[4]; /* bit vector */
236 #define CNTXT_CAP0_JUMBO 0x0080 /* Contiguous Jumbo buffers*/
237 #define CNTXT_CAP0_LRO 0x0100
238 #define CNTXT_CAP0_HW_LRO 0x0800 /* HW LRO */
240 uint32_t intr_mode; /* same as q80_tx_cntxt_req_t */
241 uint32_t rds_intr_mode; /* same as q80_tx_cntxt_req_t */
243 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */
244 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */
246 uint16_t num_rds_rings;
247 uint16_t num_sds_rings;
250 } __packed q80_rq_rcv_cntxt_t; /* 176 bytes header + rds + sds ring rqsts */
253 * Receive Context - Response from Firmware to Q8_CMD_CREATE_RX_CNTXT
256 typedef struct _q80_rsp_rds_ring {
257 uint32_t producer_reg;
259 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
261 typedef struct _q80_rsp_sds_ring {
262 uint32_t consumer_reg;
263 uint32_t intr_mask_reg;
264 } __packed q80_rsp_sds_ring_t; /* 8 bytes */
266 typedef struct _q80_rsp_rcv_cntxt {
267 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */
268 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */
270 uint32_t cntxt_state; /* starting state */
271 uint32_t funcs_per_port; /* number of PCI functions sharing each port */
273 uint16_t num_rds_rings;
274 uint16_t num_sds_rings;
276 uint16_t cntxt_id; /* handle for context */
278 uint8_t phys_port; /* physical id of port */
279 uint8_t virt_port; /* virtual or logical id of port */
283 } __packed q80_rsp_rcv_cntxt_t; /* 152 bytes header + rds + sds ring rspncs */
289 * 188 (rq) + 144 (rsp) = 332 bytes are required
292 * 1 RDS and 1 SDS rings: (16+24+176)+(8+8+152) = 384 bytes
294 * 3 RDS and 4 SDS rings: (((16+24)*3)+176) + (((8+8)*4)+152) =
295 * = 296 + 216 = 512 bytes
296 * Clearly this within the minimum PAGE size of most O.S platforms
297 * (typically 4Kbytes). Hence it is simpler to simply allocate one PAGE
298 * and then carve out space for each context. It is also a good idea to
299 * to throw in the shadown register for the consumer index of the transmit
304 * Receive Descriptor corresponding to each entry in the receive ring
306 typedef struct _q80_rcv_desc {
309 uint32_t buf_size; /* buffer size in bytes */
310 uint64_t buf_addr; /* physical address of buffer */
311 } __packed q80_recv_desc_t;
314 * Status Descriptor corresponding to each entry in the Status ring
316 typedef struct _q80_stat_desc {
318 } __packed q80_stat_desc_t;
321 * definitions for data[0] field of Status Descriptor
323 #define Q8_STAT_DESC_OWNER(data) ((data >> 56) & 0x3)
324 #define Q8_STAT_DESC_OWNER_HOST 0x1
325 #define Q8_STAT_DESC_OWNER_FW 0x2
327 #define Q8_STAT_DESC_OWNER_MASK (((uint64_t)0x3) << 56)
328 #define Q8_STAT_DESC_SET_OWNER(owner) (uint64_t)(((uint64_t)owner) << 56)
330 #define Q8_STAT_DESC_OPCODE(data) ((data >> 58) & 0x003F)
331 #define Q8_STAT_DESC_OPCODE_SYN_OFFLOAD 0x03
332 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x04
333 #define Q8_STAT_DESC_OPCODE_CTRL_MSG 0x05
334 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x12
337 * definitions for data[0] field of Status Descriptor for standard frames
338 * status descriptor opcode equals 0x04
340 #define Q8_STAT_DESC_PORT(data) ((data) & 0x000F)
341 #define Q8_STAT_DESC_STATUS(data) ((data >> 4) & 0x000F)
342 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01
343 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02
344 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03
346 #define Q8_STAT_DESC_TYPE(data) ((data >> 8) & 0x000F)
347 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 12) & 0xFFFF)
348 #define Q8_STAT_DESC_HANDLE(data) ((data >> 28) & 0xFFFF)
349 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F)
350 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F)
351 #define Q8_STAT_DESC_COUNT(data) ((data >> 53) & 0x0007)
354 * definitions for data[0-1] fields of Status Descriptor for LRO
355 * status descriptor opcode equals 0x05
357 /* definitions for data[0] field */
358 #define Q8_LRO_STAT_DESC_HANDLE(data) ((data) & 0xFFFF)
359 #define Q8_LRO_STAT_DESC_PAYLOAD_LENGTH(data) ((data >> 16) & 0xFFFF)
360 #define Q8_LRO_STAT_DESC_L2_OFFSET(data) ((data >> 32) & 0xFF)
361 #define Q8_LRO_STAT_DESC_L4_OFFSET(data) ((data >> 40) & 0xFF)
362 #define Q8_LRO_STAT_DESC_TS_PRESENT(data) ((data >> 48) & 0x1)
363 #define Q8_LRO_STAT_DESC_TYPE(data) ((data >> 49) & 0x7)
364 #define Q8_LRO_STAT_DESC_PUSH_BIT(data) ((data >> 52) & 0x1)
366 /* definitions for data[1] field */
367 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data)
369 /** Driver Related Definitions Begin **/
371 #define MAX_RDS_RINGS 2 /* Max# of Receive Descriptor Rings */
372 #define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */
373 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */
375 /* The number of descriptors should be a power of 2 */
376 #define NUM_TX_DESCRIPTORS 2048
377 #define NUM_RX_DESCRIPTORS 8192
378 //#define NUM_RX_JUMBO_DESCRIPTORS 1024
379 #define NUM_RX_JUMBO_DESCRIPTORS 2048
380 //#define NUM_STATUS_DESCRIPTORS 8192
381 #define NUM_STATUS_DESCRIPTORS 2048
383 typedef struct _q80_rcv_cntxt_req {
384 q80_rq_rcv_cntxt_t rx_req;
385 q80_rq_rds_ring_t rds_req[MAX_RDS_RINGS];
386 q80_rq_sds_ring_t sds_req[MAX_SDS_RINGS];
387 } __packed q80_rcv_cntxt_req_t;
389 typedef struct _q80_rcv_cntxt_rsp {
390 q80_rsp_rcv_cntxt_t rx_rsp;
391 q80_rsp_rds_ring_t rds_rsp[MAX_RDS_RINGS];
392 q80_rsp_sds_ring_t sds_rsp[MAX_SDS_RINGS];
393 } __packed q80_rcv_cntxt_rsp_t;
396 * structure describing various dma buffers
398 #define RDS_RING_INDEX_NORMAL 0
399 #define RDS_RING_INDEX_JUMBO 1
401 typedef struct qla_dmabuf {
410 qla_dma_t rds_ring[MAX_RDS_RINGS];
411 qla_dma_t sds_ring[MAX_SDS_RINGS];
415 /** Driver Related Definitions End **/
418 * Firmware Control Descriptor
420 typedef struct _qla_fw_cds_hdr {
422 #define Q8_FWCD_CNTRL_REQ (0x13 << 23)
427 #define Q8_FW_CDS_HDR_COMPLETION 0x1
430 } __packed qla_fw_cds_hdr_t;
433 * definitions for opcode in qla_fw_cds_hdr_t
435 #define Q8_FWCD_OPCODE_CONFIG_RSS 0x01
436 #define Q8_FWCD_OPCODE_CONFIG_RSS_TABLE 0x02
437 #define Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING 0x03
438 #define Q8_FWCD_OPCODE_CONFIG_LED 0x04
439 #define Q8_FWCD_OPCODE_CONFIG_MAC_ADDR 0x06
440 #define Q8_FWCD_OPCODE_LRO_FLOW 0x07
441 #define Q8_FWCD_OPCODE_GET_SNMP_STATS 0x08
442 #define Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE 0x0C
443 #define Q8_FWCD_OPCODE_STATISTICS 0x10
444 #define Q8_FWCD_OPCODE_CONFIG_IPADDR 0x12
445 #define Q8_FWCD_OPCODE_CONFIG_LOOPBACK 0x13
446 #define Q8_FWCD_OPCODE_LINK_EVENT_REQ 0x15
447 #define Q8_FWCD_OPCODE_CONFIG_BRIDGING 0x17
448 #define Q8_FWCD_OPCODE_CONFIG_LRO 0x18
453 typedef struct _qla_fw_cds_config_rss {
454 qla_fw_cds_hdr_t hdr;
456 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4)
457 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_IP (0x1 << 4)
458 #define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4)
459 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6)
460 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_IP (0x1 << 6)
461 #define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6)
464 #define Q8_FWCD_RSS_FLAGS_ENABLE_RSS 0x1
465 #define Q8_FWCD_RSS_FLAGS_USE_IND_TABLE 0x2
467 uint16_t ind_tbl_mask;
469 } __packed qla_fw_cds_config_rss_t;
472 * Configure RSS Table
474 typedef struct _qla_fw_cds_config_rss_table {
475 qla_fw_cds_hdr_t hdr;
478 } __packed qla_fw_cds_config_rss_table_t;
481 * Configure Interrupt Coalescing
483 typedef struct _qla_fw_cds_config_intr_coalesc {
484 qla_fw_cds_hdr_t hdr;
490 uint16_t max_rcv_pkts;
491 uint16_t max_rcv_usecs;
492 uint16_t max_snd_pkts;
493 uint16_t max_snd_usecs;
498 #define Q8_FWCMD_INTR_COALESC_TIMER_NONE 0x00
499 #define Q8_FWCMD_INTR_COALESC_TIMER_ONCE 0x01
500 #define Q8_FWCMD_INTR_COALESC_TIMER_PERIODIC 0x02
502 uint8_t sds_ring_bitmask;
503 #define Q8_FWCMD_INTR_COALESC_SDS_RING_0 0x01
504 #define Q8_FWCMD_INTR_COALESC_SDS_RING_1 0x02
505 #define Q8_FWCMD_INTR_COALESC_SDS_RING_2 0x04
506 #define Q8_FWCMD_INTR_COALESC_SDS_RING_3 0x08
509 } __packed qla_fw_cds_config_intr_coalesc_t;
512 * Configure LED Parameters
514 typedef struct _qla_fw_cds_config_led {
515 qla_fw_cds_hdr_t hdr;
518 uint32_t blink_state;
520 } __packed qla_fw_cds_config_led_t;
523 * Configure MAC Address
525 typedef struct _qla_fw_cds_config_mac_addr {
526 qla_fw_cds_hdr_t hdr;
528 #define Q8_FWCD_ADD_MAC_ADDR 0x1
529 #define Q8_FWCD_DEL_MAC_ADDR 0x2
532 } __packed qla_fw_cds_config_mac_addr_t;
535 * Configure Add/Delete LRO
537 typedef struct _qla_fw_cds_config_lro {
538 qla_fw_cds_hdr_t hdr;
539 uint32_t dst_ip_addr;
540 uint32_t src_ip_addr;
541 uint16_t dst_tcp_port;
542 uint16_t src_tcp_port;
547 uint32_t host_handle;
548 } __packed qla_fw_cds_config_lro_t;
551 * Get SNMP Statistics
553 typedef struct _qla_fw_cds_get_snmp {
554 qla_fw_cds_hdr_t hdr;
559 } __packed qla_fw_cds_get_snmp_t;
561 typedef struct _qla_snmp_stats {
562 uint64_t jabber_state;
563 uint64_t false_carrier;
566 uint64_t align_errors;
567 uint64_t chksum_errors;
568 uint64_t oversize_frames;
570 uint64_t mac_rcv_errors;
571 uint64_t phy_rcv_errors;
574 } __packed qla_snmp_stats_t;
577 * Enable Link Event Requests
579 typedef struct _qla_link_event_req {
580 qla_fw_cds_hdr_t hdr;
582 uint8_t get_clnk_params;
584 } __packed qla_link_event_req_t;
588 * Set MAC Receive Mode
590 typedef struct _qla_set_mac_rcv_mode {
591 qla_fw_cds_hdr_t hdr;
594 #define Q8_MAC_RCV_RESET_PROMISC_ALLMULTI 0x00
595 #define Q8_MAC_RCV_ENABLE_PROMISCUOUS 0x01
596 #define Q8_MAC_RCV_ENABLE_ALLMULTI 0x02
599 } __packed qla_set_mac_rcv_mode_t;
602 * Configure IP Address
604 typedef struct _qla_config_ipv4 {
605 qla_fw_cds_hdr_t hdr;
608 #define Q8_CONFIG_CMD_IP_ENABLE 0x02
609 #define Q8_CONFIG_CMD_IP_DISABLE 0x03
612 } __packed qla_config_ipv4_t;
617 typedef struct _qla_config_lro {
618 qla_fw_cds_hdr_t hdr;
621 #define Q8_CONFIG_LRO_ENABLE 0x08
622 } __packed qla_config_lro_t;
626 * Control Messages Received on SDS Ring
629 typedef struct _qla_cntrl_msg_hdr {
635 #define Q8_CTRL_MSG_TAG_DESC_COUNT_MASK (0x7 << 5)
636 #define Q8_CTRL_MSG_TAG_OWNER_MASK (0x3 << 8)
637 #define Q8_CTRL_MSG_TAG_OPCODE_MASK (0x3F << 10)
638 } __packed qla_cntrl_msg_hdr_t;
641 * definitions for rsp_type in qla_cntrl_msg_hdr_t
643 #define Q8_CTRL_CONFIG_MAC_RSP 0x85
644 #define Q8_CTRL_LRO_FLOW_DELETE_RSP 0x86
645 #define Q8_CTRL_LRO_FLOW_ADD_FAILURE_RSP 0x87
646 #define Q8_CTRL_GET_SNMP_STATS_RSP 0x88
647 #define Q8_CTRL_GET_NETWORK_STATS_RSP 0x8C
648 #define Q8_CTRL_LINK_EVENT_NOTIFICATION 0x8D
651 * Configure MAC Response
653 typedef struct _qla_config_mac_rsp {
656 } __packed qla_config_mac_rsp_t;
659 * LRO Flow Response (can be LRO Flow Delete and LRO Flow Add Failure)
661 typedef struct _qla_lro_flow_rsp {
666 uint16_t dst_tcp_port;
667 uint16_t src_tcp_port;
671 } __packed qla_lro_flow_rsp_t;
674 * Get SNMP Statistics Response
676 typedef struct _qla_get_snmp_stats_rsp {
678 } __packed qla_get_snmp_stats_rsp_t;
681 * Get Network Statistics Response
683 typedef struct _qla_get_net_stats_rsp {
685 } __packed qla_get_net_stats_rsp_t;
688 * Link Event Notification
690 typedef struct _qla_link_event {
692 uint16_t cable_length;
695 #define Q8_LE_SPEED_MASK 0xFFF
696 #define Q8_LE_SPEED_10GBPS 0x710
697 #define Q8_LE_SPEED_1GBPS 0x3E8
698 #define Q8_LE_SPEED_100MBPS 0x064
699 #define Q8_LE_SPEED_10MBPS 0x00A
701 uint8_t link_up;/* 0 = down; else up */
704 #define Q8_LE_MI_MODULE_NOT_PRESENT 0x01
705 #define Q8_LE_MI_UNKNOWN_OPTICAL_MODULE 0x02
706 #define Q8_LE_MI_SR_LR_OPTICAL_MODULE 0x03
707 #define Q8_LE_MI_LRM_OPTICAL_MODULE 0x04
708 #define Q8_LE_MI_SFP_1G_MODULE 0x05
709 #define Q8_LE_MI_UNSUPPORTED_TWINAX 0x06
710 #define Q8_LE_MI_UNSUPPORTED_TWINAX_LENGTH 0x07
711 #define Q8_LE_MI_SUPPORTED_TWINAX 0x08
713 uint8_t fduplex; /* 1 = full duplex; 0 = half duplex */
714 uint8_t autoneg; /* 1 = autoneg enable; 0 = disabled */
716 } __packed qla_link_event_t;
718 typedef struct _qla_sds {
719 q80_stat_desc_t *sds_ring_base; /* start of sds ring */
720 uint32_t sdsr_next; /* next entry in SDS ring to process */
726 volatile uint32_t rcv_active;
729 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
730 sizeof (struct ip) + sizeof (struct tcphdr) + 16)
732 * struct for storing hardware specific information for a given interface
734 typedef struct _qla_hw {
746 uint16_t cable_length;
751 uint32_t max_rds_per_cntxt;
752 uint32_t max_sds_per_cntxt;
753 uint32_t max_rules_per_cntxt;
754 uint32_t max_rcv_cntxts;
755 uint32_t max_xmt_cntxts;
759 uint8_t mac_addr[ETHER_ADDR_LEN];
761 uint16_t num_rds_rings;
762 uint16_t num_sds_rings;
764 qla_dmabuf_t dma_buf;
768 q80_tx_cmd_t *tx_ring_base;
770 q80_tx_cntxt_req_t *tx_cntxt_req; /* TX Context Request */
771 bus_addr_t tx_cntxt_req_paddr;
773 q80_tx_cntxt_rsp_t *tx_cntxt_rsp; /* TX Context Response */
774 bus_addr_t tx_cntxt_rsp_paddr;
776 uint32_t *tx_cons; /* tx consumer shadow reg */
777 bus_addr_t tx_cons_paddr;
779 volatile uint32_t txr_free; /* # of free entries in tx ring */
780 volatile uint32_t txr_next; /* # next available tx ring entry */
781 volatile uint32_t txr_comp; /* index of last tx entry completed */
783 uint32_t tx_prod_reg;
786 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
787 volatile int32_t rxj_next; /* next jumbo rcv ring to arm fw */
789 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */
790 volatile int32_t rxj_in; /* next jumbo rcv ring to add mbufs */
792 q80_rcv_cntxt_req_t *rx_cntxt_req; /* Rcv Context Request */
793 bus_addr_t rx_cntxt_req_paddr;
794 q80_rcv_cntxt_rsp_t *rx_cntxt_rsp; /* Rcv Context Response */
795 bus_addr_t rx_cntxt_rsp_paddr;
797 qla_sds_t sds[MAX_SDS_RINGS];
799 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
802 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, i, val) \
803 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\
806 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val) \
807 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val)
809 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
810 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\
813 #define QL_CLEAR_INTERRUPTS(ha) \
814 if (ha->pci_func == 0) {\
815 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\
817 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\
820 #define QL_ENABLE_INTERRUPTS(ha, sds_index) \
822 q80_rsp_sds_ring_t *rsp_sds;\
823 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\
824 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\
827 #define QL_DISABLE_INTERRUPTS(ha, sds_index) \
829 q80_rsp_sds_ring_t *rsp_sds;\
830 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\
831 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
835 #define QL_BUFFER_ALIGN 16
837 #endif /* #ifndef _QLA_HW_H_ */