2 * Copyright (c) 2011-2013 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 #ifndef _QLA_INLINE_H_
34 #define _QLA_INLINE_H_
37 * Function: qla_hw_reset
39 static __inline void qla_hw_reset(qla_host_t *ha)
41 WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0xFFFFFFFF);
44 #define QL8_SEMLOCK_TIMEOUT 1000/* QLA8020 Semaphore Lock Timeout 10ms */
48 * Inline functions for hardware semaphores
53 * Function: Locks one of the semaphore registers (semaphore 2,3,5 & 7)
54 * If the id_reg is valid, then id_val is written into it.
55 * This is for debugging purpose
56 * Returns: 0 on success; otherwise its failed.
59 qla_sem_lock(qla_host_t *ha, uint32_t sem_reg, uint32_t id_reg, uint32_t id_val)
61 int count = QL8_SEMLOCK_TIMEOUT;
64 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT))
70 qla_mdelay(__func__, 10);
73 WRITE_OFFSET32(ha, id_reg, id_val);
79 * Name: qla_sem_unlock
80 * Function: Unlocks the semaphore registers (semaphore 2,3,5 & 7)
81 * previously locked by qla_sem_lock()
84 qla_sem_unlock(qla_host_t *ha, uint32_t sem_reg)
86 READ_REG32(ha, sem_reg);
90 qla_get_ifq_snd_maxlen(qla_host_t *ha)
92 return((NUM_TX_DESCRIPTORS - 1));
95 static __inline uint32_t
96 qla_get_optics(qla_host_t *ha)
100 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
101 if (ha->pci_func == 0)
102 link_speed = link_speed & 0xFF;
104 link_speed = (link_speed >> 8) & 0xFF;
106 switch (link_speed) {
108 link_speed = IFM_100_FX;
112 link_speed = IFM_1000_SX;
116 link_speed = (IFM_10G_LR | IFM_10G_SR);
123 static __inline uint8_t *
124 qla_get_mac_addr(qla_host_t *ha)
126 return (ha->hw.mac_addr);
130 qla_read_mac_addr(qla_host_t *ha)
132 uint32_t mac_crb_addr;
137 mac_crb_addr = Q8_CRB_MAC_BLOCK_START +
138 (((ha->pci_func >> 1) * 3) << 2) + ((ha->pci_func & 0x01) << 2);
140 mac_lo = READ_REG32(ha, mac_crb_addr);
141 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
143 if (ha->pci_func & 0x01) {
144 mac_lo = mac_lo >> 16;
146 macp = (uint8_t *)&mac_lo;
148 ha->hw.mac_addr[5] = macp[0];
149 ha->hw.mac_addr[4] = macp[1];
151 macp = (uint8_t *)&mac_hi;
153 ha->hw.mac_addr[3] = macp[0];
154 ha->hw.mac_addr[2] = macp[1];
155 ha->hw.mac_addr[1] = macp[2];
156 ha->hw.mac_addr[0] = macp[3];
158 macp = (uint8_t *)&mac_lo;
160 ha->hw.mac_addr[5] = macp[0];
161 ha->hw.mac_addr[4] = macp[1];
162 ha->hw.mac_addr[3] = macp[2];
163 ha->hw.mac_addr[2] = macp[3];
165 macp = (uint8_t *)&mac_hi;
167 ha->hw.mac_addr[1] = macp[0];
168 ha->hw.mac_addr[0] = macp[1];
174 qla_set_hw_rcv_desc(qla_host_t *ha, uint32_t ridx, uint32_t index,
175 uint32_t handle, bus_addr_t paddr, uint32_t buf_size)
177 q80_recv_desc_t *rcv_desc;
179 rcv_desc = (q80_recv_desc_t *)ha->hw.dma_buf.rds_ring[ridx].dma_b;
183 rcv_desc->handle = (uint16_t)handle;
184 rcv_desc->buf_size = buf_size;
185 rcv_desc->buf_addr = paddr;
191 qla_init_hw_rcv_descriptors(qla_host_t *ha, uint32_t ridx)
193 if (ridx == RDS_RING_INDEX_NORMAL)
194 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
195 (sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS));
196 else if (ridx == RDS_RING_INDEX_JUMBO)
197 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
198 (sizeof(q80_recv_desc_t) * NUM_RX_JUMBO_DESCRIPTORS));
200 QL_ASSERT(0, ("%s: invalid rds index [%d]\n", __func__, ridx));
204 qla_lock(qla_host_t *ha, const char *str)
207 mtx_lock(&ha->hw_lock);
208 if (!ha->hw_lock_held) {
209 ha->hw_lock_held = 1;
211 mtx_unlock(&ha->hw_lock);
214 mtx_unlock(&ha->hw_lock);
215 qla_mdelay(__func__, 1);
221 qla_unlock(qla_host_t *ha, const char *str)
223 mtx_lock(&ha->hw_lock);
224 ha->hw_lock_held = 0;
225 ha->qla_unlock = str;
226 mtx_unlock(&ha->hw_lock);
229 #endif /* #ifndef _QLA_INLINE_H_ */