2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011-2013 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
35 #ifndef _QLA_INLINE_H_
36 #define _QLA_INLINE_H_
39 * Function: qla_hw_reset
41 static __inline void qla_hw_reset(qla_host_t *ha)
43 WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0xFFFFFFFF);
46 #define QL8_SEMLOCK_TIMEOUT 1000/* QLA8020 Semaphore Lock Timeout 10ms */
50 * Inline functions for hardware semaphores
55 * Function: Locks one of the semaphore registers (semaphore 2,3,5 & 7)
56 * If the id_reg is valid, then id_val is written into it.
57 * This is for debugging purpose
58 * Returns: 0 on success; otherwise its failed.
61 qla_sem_lock(qla_host_t *ha, uint32_t sem_reg, uint32_t id_reg, uint32_t id_val)
63 int count = QL8_SEMLOCK_TIMEOUT;
66 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT))
72 qla_mdelay(__func__, 10);
75 WRITE_OFFSET32(ha, id_reg, id_val);
81 * Name: qla_sem_unlock
82 * Function: Unlocks the semaphore registers (semaphore 2,3,5 & 7)
83 * previously locked by qla_sem_lock()
86 qla_sem_unlock(qla_host_t *ha, uint32_t sem_reg)
88 READ_REG32(ha, sem_reg);
92 qla_get_ifq_snd_maxlen(qla_host_t *ha)
94 return((NUM_TX_DESCRIPTORS - 1));
97 static __inline uint32_t
98 qla_get_optics(qla_host_t *ha)
102 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
103 if (ha->pci_func == 0)
104 link_speed = link_speed & 0xFF;
106 link_speed = (link_speed >> 8) & 0xFF;
108 switch (link_speed) {
110 link_speed = IFM_100_FX;
114 link_speed = IFM_1000_SX;
118 link_speed = (IFM_10G_LR | IFM_10G_SR);
125 static __inline uint8_t *
126 qla_get_mac_addr(qla_host_t *ha)
128 return (ha->hw.mac_addr);
132 qla_read_mac_addr(qla_host_t *ha)
134 uint32_t mac_crb_addr;
139 mac_crb_addr = Q8_CRB_MAC_BLOCK_START +
140 (((ha->pci_func >> 1) * 3) << 2) + ((ha->pci_func & 0x01) << 2);
142 mac_lo = READ_REG32(ha, mac_crb_addr);
143 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
145 if (ha->pci_func & 0x01) {
146 mac_lo = mac_lo >> 16;
148 macp = (uint8_t *)&mac_lo;
150 ha->hw.mac_addr[5] = macp[0];
151 ha->hw.mac_addr[4] = macp[1];
153 macp = (uint8_t *)&mac_hi;
155 ha->hw.mac_addr[3] = macp[0];
156 ha->hw.mac_addr[2] = macp[1];
157 ha->hw.mac_addr[1] = macp[2];
158 ha->hw.mac_addr[0] = macp[3];
160 macp = (uint8_t *)&mac_lo;
162 ha->hw.mac_addr[5] = macp[0];
163 ha->hw.mac_addr[4] = macp[1];
164 ha->hw.mac_addr[3] = macp[2];
165 ha->hw.mac_addr[2] = macp[3];
167 macp = (uint8_t *)&mac_hi;
169 ha->hw.mac_addr[1] = macp[0];
170 ha->hw.mac_addr[0] = macp[1];
176 qla_set_hw_rcv_desc(qla_host_t *ha, uint32_t ridx, uint32_t index,
177 uint32_t handle, bus_addr_t paddr, uint32_t buf_size)
179 q80_recv_desc_t *rcv_desc;
181 rcv_desc = (q80_recv_desc_t *)ha->hw.dma_buf.rds_ring[ridx].dma_b;
185 rcv_desc->handle = (uint16_t)handle;
186 rcv_desc->buf_size = buf_size;
187 rcv_desc->buf_addr = paddr;
193 qla_init_hw_rcv_descriptors(qla_host_t *ha, uint32_t ridx)
195 if (ridx == RDS_RING_INDEX_NORMAL)
196 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
197 (sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS));
198 else if (ridx == RDS_RING_INDEX_JUMBO)
199 bzero((void *)ha->hw.dma_buf.rds_ring[ridx].dma_b,
200 (sizeof(q80_recv_desc_t) * NUM_RX_JUMBO_DESCRIPTORS));
202 QL_ASSERT(0, ("%s: invalid rds index [%d]\n", __func__, ridx));
206 qla_lock(qla_host_t *ha, const char *str)
209 mtx_lock(&ha->hw_lock);
210 if (!ha->hw_lock_held) {
211 ha->hw_lock_held = 1;
213 mtx_unlock(&ha->hw_lock);
216 mtx_unlock(&ha->hw_lock);
217 qla_mdelay(__func__, 1);
223 qla_unlock(qla_host_t *ha, const char *str)
225 mtx_lock(&ha->hw_lock);
226 ha->hw_lock_held = 0;
227 ha->qla_unlock = str;
228 mtx_unlock(&ha->hw_lock);
231 #endif /* #ifndef _QLA_INLINE_H_ */