2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011-2013 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
40 * Begin Definitions for QLA82xx Registers
44 * Register offsets for QLA8022
47 /******************************
49 ******************************/
50 #define Q8_CRB_WINDOW_2M 0x130060
52 #define Q8_INT_VECTOR 0x130100
53 #define Q8_INT_MASK 0x130104
55 #define Q8_INT_TARGET_STATUS_F0 0x130118
56 #define Q8_INT_TARGET_MASK_F0 0x130128
57 #define Q8_INT_TARGET_STATUS_F1 0x130160
58 #define Q8_INT_TARGET_MASK_F1 0x130170
59 #define Q8_INT_TARGET_STATUS_F2 0x130164
60 #define Q8_INT_TARGET_MASK_F2 0x130174
61 #define Q8_INT_TARGET_STATUS_F3 0x130168
62 #define Q8_INT_TARGET_MASK_F3 0x130178
63 #define Q8_INT_TARGET_STATUS_F4 0x130360
64 #define Q8_INT_TARGET_MASK_F4 0x130370
65 #define Q8_INT_TARGET_STATUS_F5 0x130364
66 #define Q8_INT_TARGET_MASK_F5 0x130374
67 #define Q8_INT_TARGET_STATUS_F6 0x130368
68 #define Q8_INT_TARGET_MASK_F6 0x130378
69 #define Q8_INT_TARGET_STATUS_F7 0x13036C
70 #define Q8_INT_TARGET_MASK_F7 0x13037C
72 #define Q8_SEM2_LOCK 0x13C010
73 #define Q8_SEM2_UNLOCK 0x13C014
74 #define Q8_SEM3_LOCK 0x13C018
75 #define Q8_SEM3_UNLOCK 0x13C01C
76 #define Q8_SEM5_LOCK 0x13C028
77 #define Q8_SEM5_UNLOCK 0x13C02C
78 #define Q8_SEM7_LOCK 0x13C038
79 #define Q8_SEM7_UNLOCK 0x13C03C
81 /* Valid bit for a SEM<N>_LOCK registers */
82 #define SEM_LOCK_BIT 0x00000001
84 #define Q8_ROM_LOCKID 0x1B2100
86 /*******************************
87 * Firmware Interface Registers
88 *******************************/
89 #define Q8_FW_VER_MAJOR 0x1B2150
90 #define Q8_FW_VER_MINOR 0x1B2154
91 #define Q8_FW_VER_SUB 0x1B2158
92 #define Q8_FW_VER_BUILD 0x1B2168
94 #define Q8_CMDPEG_STATE 0x1B2250
95 #define Q8_RCVPEG_STATE 0x1B233C
97 * definitions for Q8_CMDPEG_STATE
99 #define CMDPEG_PHAN_INIT_COMPLETE 0xFF01
101 #define Q8_ROM_STATUS 0x1A0004
103 * definitions for Q8_ROM_STATUS
104 * bit definitions for Q8_UNM_ROMUSB_GLB_STATUS
105 * 31:3 Reserved; Rest as below
107 #define ROM_STATUS_RDY 0x0004
108 #define ROM_STATUS_DONE 0x0002
109 #define ROM_STATUS_AUTO_ROM_SHDW 0x0001
111 #define Q8_ASIC_RESET 0x1A0008
113 * definitions for Q8_ASIC_RESET
115 #define ASIC_RESET_RST_XDMA 0x00800000 /* Reset XDMA */
116 #define ASIC_RESET_PEG_ICACHE 0x00000020 /* Reset PEG_ICACHE */
117 #define ASIC_RESET_PEG_DCACHE 0x00000010 /* Reset PEG_DCACHE */
118 #define ASIC_RESET_PEG_3 0x00000008 /* Reset PEG_3 */
119 #define ASIC_RESET_PEG_2 0x00000004 /* Reset PEG_2 */
120 #define ASIC_RESET_PEG_1 0x00000002 /* Reset PEG_1 */
121 #define ASIC_RESET_PEG_0 0x00000001 /* Reset PEG_0 */
123 #define Q8_COLD_BOOT 0x1B21FC
125 * definitions for Q8_COLD_BOOT
127 #define COLD_BOOT_VALUE 0x12345678
129 #define Q8_MIU_TEST_AGT_CTRL 0x180090
130 #define Q8_MIU_TEST_AGT_ADDR_LO 0x180094
131 #define Q8_MIU_TEST_AGT_ADDR_HI 0x180098
132 #define Q8_MIU_TEST_AGT_WRDATA_LO 0x1800A0
133 #define Q8_MIU_TEST_AGT_WRDATA_HI 0x1800A4
134 #define Q8_MIU_TEST_AGT_RDDATA_LO 0x1800A8
135 #define Q8_MIU_TEST_AGT_RDDATA_HI 0x1800AC
136 #define Q8_MIU_TEST_AGT_WRDATA_ULO 0x1800B0
137 #define Q8_MIU_TEST_AGT_WRDATA_UHI 0x1800B4
138 #define Q8_MIU_TEST_AGT_RDDATA_ULO 0x1800B8
139 #define Q8_MIU_TEST_AGT_RDDATA_UHI 0x1800BC
141 #define Q8_PEG_0_RESET 0x160018
142 #define Q8_PEG_0_CLR1 0x160008
143 #define Q8_PEG_0_CLR2 0x16000C
144 #define Q8_PEG_1_CLR1 0x161008
145 #define Q8_PEG_1_CLR2 0x16100C
146 #define Q8_PEG_2_CLR1 0x162008
147 #define Q8_PEG_2_CLR2 0x16200C
148 #define Q8_PEG_3_CLR1 0x163008
149 #define Q8_PEG_3_CLR2 0x16300C
150 #define Q8_PEG_4_CLR1 0x164008
151 #define Q8_PEG_4_CLR2 0x16400C
152 #define Q8_PEG_D_RESET1 0x1650EC
153 #define Q8_PEG_D_RESET2 0x16504C
154 #define Q8_PEG_HALT_STATUS1 0x1B20A8
155 #define Q8_PEG_HALT_STATUS2 0x1B20AC
156 #define Q8_FIRMWARE_HEARTBEAT 0x1B20B0
157 #define Q8_PEG_I_RESET 0x16604C
159 #define Q8_CRB_MAC_BLOCK_START 0x1B21C0
161 /***************************************************
162 * Flash ROM Access Registers ( Indirect Registers )
163 ***************************************************/
165 #define Q8_ROM_INSTR_OPCODE 0x03310004
167 * bit definitions for Q8_ROM_INSTR_OPCODE
168 * 31:8 Reserved; Rest Below
170 #define ROM_OPCODE_WR_STATUS_REG 0x01
171 #define ROM_OPCODE_PROG_PAGE 0x02
172 #define ROM_OPCODE_RD_BYTE 0x03
173 #define ROM_OPCODE_WR_DISABLE 0x04
174 #define ROM_OPCODE_RD_STATUS_REG 0x05
175 #define ROM_OPCODE_WR_ENABLE 0x06
176 #define ROM_OPCODE_FAST_RD 0x0B
177 #define ROM_OPCODE_REL_DEEP_PWR_DWN 0xAB
178 #define ROM_OPCODE_BULK_ERASE 0xC7
179 #define ROM_OPCODE_DEEP_PWR_DWN 0xC9
180 #define ROM_OPCODE_SECTOR_ERASE 0xD8
182 #define Q8_ROM_ADDRESS 0x03310008
184 * bit definitions for Q8_ROM_ADDRESS
186 * 23:0 Physical ROM Address in bytes
189 #define Q8_ROM_ADDR_BYTE_COUNT 0x03310010
191 * bit definitions for Q8_ROM_ADDR_BYTE_COUNT
193 * 1:0 max address bytes for ROM Interface
196 #define Q8_ROM_DUMMY_BYTE_COUNT 0x03310014
198 * bit definitions for Q8_ROM_DUMMY_BYTE_COUNT
200 * 1:0 dummy bytes for ROM Instructions
203 #define Q8_ROM_RD_DATA 0x03310018
204 #define Q8_ROM_WR_DATA 0x0331000C
205 #define Q8_ROM_DIRECT_WINDOW 0x03310030
206 #define Q8_ROM_DIRECT_DATA_OFFSET 0x03310000
208 #define Q8_NX_CDRP_CMD_RSP 0x1B2218
209 #define Q8_NX_CDRP_ARG1 0x1B221C
210 #define Q8_NX_CDRP_ARG2 0x1B2220
211 #define Q8_NX_CDRP_ARG3 0x1B2224
212 #define Q8_NX_CDRP_SIGNATURE 0x1B2228
214 #define Q8_LINK_STATE 0x1B2298
215 #define Q8_LINK_SPEED_0 0x1B22E8
217 * Macros for reading and writing registers
220 #if defined(__i386__) || defined(__amd64__)
221 #define Q8_MB() __asm volatile("mfence" ::: "memory")
222 #define Q8_WMB() __asm volatile("sfence" ::: "memory")
223 #define Q8_RMB() __asm volatile("lfence" ::: "memory")
230 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
231 #define READ_OFFSET32(ha, off) READ_REG32(ha, off)
233 #define WRITE_REG32(ha, reg, val) \
235 bus_write_4((ha->pci_reg), reg, val);\
236 bus_read_4((ha->pci_reg), reg);\
239 #define WRITE_REG32_MB(ha, reg, val) \
242 bus_write_4((ha->pci_reg), reg, val);\
245 #define WRITE_OFFSET32(ha, off, val)\
247 bus_write_4((ha->pci_reg), off, val);\
248 bus_read_4((ha->pci_reg), off);\
251 #endif /* #ifndef _QLA_REG_H_ */