2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2016 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
34 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
40 #define BIT_0 (0x1 << 0)
41 #define BIT_1 (0x1 << 1)
42 #define BIT_2 (0x1 << 2)
43 #define BIT_3 (0x1 << 3)
44 #define BIT_4 (0x1 << 4)
45 #define BIT_5 (0x1 << 5)
46 #define BIT_6 (0x1 << 6)
47 #define BIT_7 (0x1 << 7)
48 #define BIT_8 (0x1 << 8)
49 #define BIT_9 (0x1 << 9)
50 #define BIT_10 (0x1 << 10)
51 #define BIT_11 (0x1 << 11)
52 #define BIT_12 (0x1 << 12)
53 #define BIT_13 (0x1 << 13)
54 #define BIT_14 (0x1 << 14)
55 #define BIT_15 (0x1 << 15)
56 #define BIT_16 (0x1 << 16)
57 #define BIT_17 (0x1 << 17)
58 #define BIT_18 (0x1 << 18)
59 #define BIT_19 (0x1 << 19)
60 #define BIT_20 (0x1 << 20)
61 #define BIT_21 (0x1 << 21)
62 #define BIT_22 (0x1 << 22)
63 #define BIT_23 (0x1 << 23)
64 #define BIT_24 (0x1 << 24)
65 #define BIT_25 (0x1 << 25)
66 #define BIT_26 (0x1 << 26)
67 #define BIT_27 (0x1 << 27)
68 #define BIT_28 (0x1 << 28)
69 #define BIT_29 (0x1 << 29)
70 #define BIT_30 (0x1 << 30)
71 #define BIT_31 (0x1 << 31)
80 typedef struct qla_rx_buf qla_rx_buf_t;
83 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
85 typedef struct qla_rx_ring qla_rx_ring_t;
91 typedef struct qla_tx_buf qla_tx_buf_t;
93 #define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */
94 #define QLA_MAX_MTU 9000
95 #define QLA_STD_FRAME_SIZE 1514
96 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
98 /* Number of MSIX/MSI Vectors required */
103 struct resource *irq;
108 typedef struct qla_ivec qla_ivec_t;
110 #define QLA_WATCHDOG_CALLOUT_TICKS 2
112 typedef struct _qla_tx_ring {
113 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
115 uint64_t iscsi_pkt_count;
118 typedef struct _qla_tx_fp {
120 char tx_mtx_name[32];
121 struct buf_ring *tx_br;
123 struct taskqueue *fp_taskqueue;
129 * Adapter structure contains the hardware independant information of the
136 qla_watchdog_active :1,
141 volatile uint32_t qla_interface_up;
142 volatile uint32_t stop_rcv;
143 volatile uint32_t qla_watchdog_exit;
144 volatile uint32_t qla_watchdog_exited;
145 volatile uint32_t qla_watchdog_pause;
146 volatile uint32_t qla_watchdog_paused;
147 volatile uint32_t qla_initiate_recovery;
148 volatile uint32_t qla_detach_active;
149 volatile uint32_t offline;
153 volatile uint16_t watchdog_ticks;
157 struct cdev *ioctl_dev;
159 /* register mapping */
160 struct resource *pci_reg;
162 struct resource *pci_reg1;
166 struct resource *mbx_irq;
172 qla_ivec_t irq_vec[MAX_SDS_RINGS];
175 bus_dma_tag_t parent_tag;
177 /* interface to o.s */
180 struct ifmedia media;
181 uint16_t max_frame_size;
185 /* hardware access lock */
187 struct mtx sp_log_lock;
189 volatile uint32_t hw_lock_held;
190 uint64_t hw_lock_failed;
192 /* transmit and receive buffers */
193 uint32_t txr_idx; /* index of the current tx ring */
194 qla_tx_ring_t tx_ring[NUM_TX_RINGS];
196 bus_dma_tag_t tx_tag;
197 struct callout tx_callout;
199 qla_tx_fp_t tx_fp[MAX_SDS_RINGS];
201 qla_rx_ring_t rx_ring[MAX_RDS_RINGS];
202 bus_dma_tag_t rx_tag;
203 uint32_t std_replenish;
205 qla_rx_buf_t *rxb_free;
206 uint32_t rxb_free_count;
209 uint32_t err_m_getcl;
210 uint32_t err_m_getjcl;
211 uint32_t err_tx_dmamap_create;
212 uint32_t err_tx_dmamap_load;
213 uint32_t err_tx_defrag;
218 uint64_t lro_pkt_count;
226 uint64_t tx_tso_frames;
227 uint64_t hw_vlan_tx_frames;
229 struct task stats_task;
230 struct taskqueue *stats_tq;
232 uint32_t fw_ver_major;
233 uint32_t fw_ver_minor;
235 uint32_t fw_ver_build;
237 /* hardware specific */
241 volatile const char *qla_lock;
242 volatile const char *qla_unlock;
244 uint32_t enable_minidump;
245 uint32_t enable_driverstate_dump;
246 uint32_t enable_error_recovery;
247 uint32_t ms_delay_after_init;
249 uint8_t fw_ver_str[32];
251 /* Error Injection Related */
253 struct task err_task;
254 struct taskqueue *err_tq;
256 /* Async Event Related */
257 uint32_t async_event;
258 struct task async_event_task;
259 struct taskqueue *async_event_tq;
264 volatile uint32_t msg_from_peer;
265 #define QL_PEER_MSG_RESET 0x01
266 #define QL_PEER_MSG_ACK 0x02
269 typedef struct qla_host qla_host_t;
271 /* note that align has to be a power of 2 */
272 #define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
273 #define QL_MIN(x, y) ((x < y) ? x : y)
275 #define QL_RUNNING(ifp) (ifp->if_drv_flags & IFF_DRV_RUNNING)
277 /* Return 0, if identical, else 1 */
278 #define QL_MAC_CMP(mac1, mac2) \
279 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
280 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
282 #define QL_INITIATE_RECOVERY(ha) qla_set_error_recovery(ha)
284 #endif /* #ifndef _QL_DEF_H_ */