2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
38 #define BIT_0 (0x1 << 0)
39 #define BIT_1 (0x1 << 1)
40 #define BIT_2 (0x1 << 2)
41 #define BIT_3 (0x1 << 3)
42 #define BIT_4 (0x1 << 4)
43 #define BIT_5 (0x1 << 5)
44 #define BIT_6 (0x1 << 6)
45 #define BIT_7 (0x1 << 7)
46 #define BIT_8 (0x1 << 8)
47 #define BIT_9 (0x1 << 9)
48 #define BIT_10 (0x1 << 10)
49 #define BIT_11 (0x1 << 11)
50 #define BIT_12 (0x1 << 12)
51 #define BIT_13 (0x1 << 13)
52 #define BIT_14 (0x1 << 14)
53 #define BIT_15 (0x1 << 15)
54 #define BIT_16 (0x1 << 16)
55 #define BIT_17 (0x1 << 17)
56 #define BIT_18 (0x1 << 18)
57 #define BIT_19 (0x1 << 19)
58 #define BIT_20 (0x1 << 20)
59 #define BIT_21 (0x1 << 21)
60 #define BIT_22 (0x1 << 22)
61 #define BIT_23 (0x1 << 23)
62 #define BIT_24 (0x1 << 24)
63 #define BIT_25 (0x1 << 25)
64 #define BIT_26 (0x1 << 26)
65 #define BIT_27 (0x1 << 27)
66 #define BIT_28 (0x1 << 28)
67 #define BIT_29 (0x1 << 29)
68 #define BIT_30 (0x1 << 30)
69 #define BIT_31 (0x1 << 31)
78 typedef struct qla_rx_buf qla_rx_buf_t;
81 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
83 typedef struct qla_rx_ring qla_rx_ring_t;
89 typedef struct qla_tx_buf qla_tx_buf_t;
91 #define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */
92 #define QLA_MAX_MTU 9000
93 #define QLA_STD_FRAME_SIZE 1514
94 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
96 /* Number of MSIX/MSI Vectors required */
101 struct resource *irq;
106 typedef struct qla_ivec qla_ivec_t;
108 #define QLA_WATCHDOG_CALLOUT_TICKS 2
110 typedef struct _qla_tx_ring {
111 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
113 uint64_t iscsi_pkt_count;
116 typedef struct _qla_tx_fp {
118 char tx_mtx_name[32];
119 struct buf_ring *tx_br;
121 struct taskqueue *fp_taskqueue;
127 * Adapter structure contains the hardware independant information of the
134 qla_watchdog_active :1,
139 volatile uint32_t qla_interface_up;
140 volatile uint32_t stop_rcv;
141 volatile uint32_t qla_watchdog_exit;
142 volatile uint32_t qla_watchdog_exited;
143 volatile uint32_t qla_watchdog_pause;
144 volatile uint32_t qla_watchdog_paused;
145 volatile uint32_t qla_initiate_recovery;
146 volatile uint32_t qla_detach_active;
150 uint16_t watchdog_ticks;
155 struct cdev *ioctl_dev;
157 /* register mapping */
158 struct resource *pci_reg;
160 struct resource *pci_reg1;
164 struct resource *mbx_irq;
170 qla_ivec_t irq_vec[MAX_SDS_RINGS];
173 bus_dma_tag_t parent_tag;
175 /* interface to o.s */
178 struct ifmedia media;
179 uint16_t max_frame_size;
183 /* hardware access lock */
186 volatile uint32_t hw_lock_held;
187 uint64_t hw_lock_failed;
189 /* transmit and receive buffers */
190 uint32_t txr_idx; /* index of the current tx ring */
191 qla_tx_ring_t tx_ring[NUM_TX_RINGS];
193 bus_dma_tag_t tx_tag;
194 struct callout tx_callout;
196 qla_tx_fp_t tx_fp[MAX_SDS_RINGS];
198 qla_rx_ring_t rx_ring[MAX_RDS_RINGS];
199 bus_dma_tag_t rx_tag;
200 uint32_t std_replenish;
202 qla_rx_buf_t *rxb_free;
203 uint32_t rxb_free_count;
206 uint32_t err_m_getcl;
207 uint32_t err_m_getjcl;
208 uint32_t err_tx_dmamap_create;
209 uint32_t err_tx_dmamap_load;
210 uint32_t err_tx_defrag;
215 uint64_t lro_pkt_count;
223 uint64_t tx_tso_frames;
224 uint64_t hw_vlan_tx_frames;
226 struct task stats_task;
227 struct taskqueue *stats_tq;
229 uint32_t fw_ver_major;
230 uint32_t fw_ver_minor;
232 uint32_t fw_ver_build;
234 /* hardware specific */
238 volatile const char *qla_lock;
239 volatile const char *qla_unlock;
241 uint32_t enable_minidump;
243 uint8_t fw_ver_str[32];
245 /* Error Injection Related */
247 struct task err_task;
248 struct taskqueue *err_tq;
250 /* Async Event Related */
251 uint32_t async_event;
252 struct task async_event_task;
253 struct taskqueue *async_event_tq;
258 volatile uint32_t msg_from_peer;
259 #define QL_PEER_MSG_RESET 0x01
260 #define QL_PEER_MSG_ACK 0x02
263 typedef struct qla_host qla_host_t;
265 /* note that align has to be a power of 2 */
266 #define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
267 #define QL_MIN(x, y) ((x < y) ? x : y)
269 #define QL_RUNNING(ifp) (ifp->if_drv_flags & IFF_DRV_RUNNING)
271 /* Return 0, if identical, else 1 */
272 #define QL_MAC_CMP(mac1, mac2) \
273 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
274 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
276 #endif /* #ifndef _QL_DEF_H_ */